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[ARM] MVE big endian bitcasts
[llvm-complete.git] / lib / Target / ARM / ARMExpandPseudoInsts.cpp
blobb32ba3eeea189a1846de05299a3915f9a882f09f
1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions to allow proper scheduling, if-conversion, and other late
11 // optimizations. This pass should be run after register allocation but before
12 // the post-regalloc scheduling pass.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "ARM.h"
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMBaseRegisterInfo.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/CodeGen/LivePhysRegs.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/Support/Debug.h"
27
28 using namespace llvm;
29
30 #define DEBUG_TYPE "arm-pseudo"
31
32 static cl::opt<bool>
33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34 cl::desc("Verify machine code after expanding ARM pseudos"));
35
36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
37
38 namespace {
39 class ARMExpandPseudo : public MachineFunctionPass {
40 public:
41 static char ID;
42 ARMExpandPseudo() : MachineFunctionPass(ID) {}
43
44 const ARMBaseInstrInfo *TII;
45 const TargetRegisterInfo *TRI;
46 const ARMSubtarget *STI;
47 ARMFunctionInfo *AFI;
48
49 bool runOnMachineFunction(MachineFunction &Fn) override;
50
51 MachineFunctionProperties getRequiredProperties() const override {
52 return MachineFunctionProperties().set(
53 MachineFunctionProperties::Property::NoVRegs);
54 }
55
56 StringRef getPassName() const override {
57 return ARM_EXPAND_PSEUDO_NAME;
58 }
59
60 private:
61 void TransferImpOps(MachineInstr &OldMI,
62 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
63 bool ExpandMI(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator MBBI,
65 MachineBasicBlock::iterator &NextMBBI);
66 bool ExpandMBB(MachineBasicBlock &MBB);
67 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
68 void ExpandVST(MachineBasicBlock::iterator &MBBI);
69 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
70 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
71 unsigned Opc, bool IsExt);
72 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator &MBBI);
74 bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
76 unsigned StrexOp, unsigned UxtOp,
77 MachineBasicBlock::iterator &NextMBBI);
78
79 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator MBBI,
81 MachineBasicBlock::iterator &NextMBBI);
82 };
83 char ARMExpandPseudo::ID = 0;
84 }
85
86 INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false,
87 false)
88
89 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
90 /// the instructions created from the expansion.
91 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
92 MachineInstrBuilder &UseMI,
93 MachineInstrBuilder &DefMI) {
94 const MCInstrDesc &Desc = OldMI.getDesc();
95 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
96 i != e; ++i) {
97 const MachineOperand &MO = OldMI.getOperand(i);
98 assert(MO.isReg() && MO.getReg());
99 if (MO.isUse())
100 UseMI.add(MO);
101 else
102 DefMI.add(MO);
103 }
104 }
105
106 namespace {
107 // Constants for register spacing in NEON load/store instructions.
108 // For quad-register load-lane and store-lane pseudo instructors, the
109 // spacing is initially assumed to be EvenDblSpc, and that is changed to
110 // OddDblSpc depending on the lane number operand.
111 enum NEONRegSpacing {
112 SingleSpc,
113 SingleLowSpc , // Single spacing, low registers, three and four vectors.
114 SingleHighQSpc, // Single spacing, high registers, four vectors.
115 SingleHighTSpc, // Single spacing, high registers, three vectors.
116 EvenDblSpc,
117 OddDblSpc
118 };
119
120 // Entries for NEON load/store information table. The table is sorted by
121 // PseudoOpc for fast binary-search lookups.
122 struct NEONLdStTableEntry {
123 uint16_t PseudoOpc;
124 uint16_t RealOpc;
125 bool IsLoad;
126 bool isUpdating;
127 bool hasWritebackOperand;
128 uint8_t RegSpacing; // One of type NEONRegSpacing
129 uint8_t NumRegs; // D registers loaded or stored
130 uint8_t RegElts; // elements per D register; used for lane ops
131 // FIXME: Temporary flag to denote whether the real instruction takes
132 // a single register (like the encoding) or all of the registers in
133 // the list (like the asm syntax and the isel DAG). When all definitions
134 // are converted to take only the single encoded register, this will
135 // go away.
136 bool copyAllListRegs;
137
138 // Comparison methods for binary search of the table.
139 bool operator<(const NEONLdStTableEntry &TE) const {
140 return PseudoOpc < TE.PseudoOpc;
141 }
142 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
143 return TE.PseudoOpc < PseudoOpc;
144 }
145 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
146 const NEONLdStTableEntry &TE) {
147 return PseudoOpc < TE.PseudoOpc;
148 }
149 };
150 }
151
152 static const NEONLdStTableEntry NEONLdStTable[] = {
153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
157 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
158 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
159
160 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
161 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
162 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
163 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
164 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
165 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
166 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false},
167 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
168 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
169 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false},
170 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false},
171 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false},
172 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false},
173 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false},
174 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false},
175 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false},
176 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false},
177 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false},
178 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false},
179 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false},
180 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false},
181 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false},
182 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false},
183 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false},
184 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false},
185 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false},
186 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false},
187 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false},
188
189 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false},
190 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false},
191 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false},
192 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false},
193 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false},
194 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false},
195
196 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
197 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
198 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
199 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
200 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
201 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
202 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
203 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
204 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
205 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
206
207 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
208 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
209 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
210 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
211 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
212 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
213 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
214 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
215 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
216
217 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
218 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
219 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
220 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
221 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
222 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
223 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true},
224 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true},
225 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true},
226 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true},
227 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true},
228 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true},
229
230 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
231 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
232 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
233 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
234 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
235 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
236 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
237 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
238 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
239 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
240
241 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
242 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
243 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
244 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
245 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
246 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
247
248 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
249 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
250 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
251 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
252 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
253 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
254 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
255 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
256 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
257
258 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
259 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
260 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
261 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
262 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
263 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
264 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true},
265 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true},
266 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true},
267 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true},
268 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true},
269 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true},
270
271 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
272 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
273 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
274 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
275 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
276 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
277 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
278 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
279 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
280 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
281
282 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
283 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
284 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
285 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
286 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
287 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
288
289 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
290 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
291 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
292 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
293 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
294 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
295 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
296 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
297 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
298
299 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
300 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
301 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
302 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
303 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
304 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
305
306 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false},
307 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false},
308 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false},
309 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false},
310 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
311 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
312 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
313 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
314 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
315 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
316 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false},
317 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false},
318 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false},
319 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false},
320 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false},
321 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false},
322 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false},
323 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false},
324 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false},
325 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false},
326 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false},
327 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false},
328 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false},
329 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false},
330 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false},
331 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false},
332 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false},
333 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false},
334
335 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
336 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
337 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
338 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
339 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
340 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
341 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
342 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
343 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
344 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
345
346 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
347 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
348 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
349 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
350 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
351 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
352 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
353 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
354 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
355
356 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
357 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
358 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
359 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
360 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
361 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
362 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
363 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
364 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
365 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
366
367 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
368 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
369 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
370 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
371 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
372 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
373
374 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
375 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
376 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
377 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
378 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
379 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
380 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
381 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
382 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
383
384 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
385 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
386 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
387 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
388 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
389 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
390 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
391 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
392 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
393 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
394
395 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
396 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
397 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
398 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
399 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
400 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
401
402 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
403 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
404 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
405 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
406 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
407 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
408 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
409 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
410 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
411 };
412
413 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
414 /// load or store pseudo instruction.
415 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
416 #ifndef NDEBUG
417 // Make sure the table is sorted.
418 static std::atomic<bool> TableChecked(false);
419 if (!TableChecked.load(std::memory_order_relaxed)) {
420 assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) &&
421 "NEONLdStTable is not sorted!");
422 TableChecked.store(true, std::memory_order_relaxed);
423 }
424 #endif
425
426 auto I = llvm::lower_bound(NEONLdStTable, Opcode);
427 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode)
428 return I;
429 return nullptr;
430 }
431
432 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
433 /// corresponding to the specified register spacing. Not all of the results
434 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
435 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
436 const TargetRegisterInfo *TRI, unsigned &D0,
437 unsigned &D1, unsigned &D2, unsigned &D3) {
438 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
439 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
440 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
441 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
442 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
443 } else if (RegSpc == SingleHighQSpc) {
444 D0 = TRI->getSubReg(Reg, ARM::dsub_4);
445 D1 = TRI->getSubReg(Reg, ARM::dsub_5);
446 D2 = TRI->getSubReg(Reg, ARM::dsub_6);
447 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
448 } else if (RegSpc == SingleHighTSpc) {
449 D0 = TRI->getSubReg(Reg, ARM::dsub_3);
450 D1 = TRI->getSubReg(Reg, ARM::dsub_4);
451 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
452 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
453 } else if (RegSpc == EvenDblSpc) {
454 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
455 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
456 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
457 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
458 } else {
459 assert(RegSpc == OddDblSpc && "unknown register spacing");
460 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
461 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
462 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
463 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
464 }
465 }
466
467 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
468 /// operands to real VLD instructions with D register operands.
469 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
470 MachineInstr &MI = *MBBI;
471 MachineBasicBlock &MBB = *MI.getParent();
472 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
473
474 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
475 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
476 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
477 unsigned NumRegs = TableEntry->NumRegs;
478
479 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
480 TII->get(TableEntry->RealOpc));
481 unsigned OpIdx = 0;
482
483 bool DstIsDead = MI.getOperand(OpIdx).isDead();
484 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
485 if(TableEntry->RealOpc == ARM::VLD2DUPd8x2 ||
486 TableEntry->RealOpc == ARM::VLD2DUPd16x2 ||
487 TableEntry->RealOpc == ARM::VLD2DUPd32x2) {
488 unsigned SubRegIndex;
489 if (RegSpc == EvenDblSpc) {
490 SubRegIndex = ARM::dsub_0;
491 } else {
492 assert(RegSpc == OddDblSpc && "Unexpected spacing!");
493 SubRegIndex = ARM::dsub_1;
494 }
495 unsigned SubReg = TRI->getSubReg(DstReg, SubRegIndex);
496 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,
497 &ARM::DPairSpcRegClass);
498 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
499 } else {
500 unsigned D0, D1, D2, D3;
501 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
502 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
503 if (NumRegs > 1 && TableEntry->copyAllListRegs)
504 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
505 if (NumRegs > 2 && TableEntry->copyAllListRegs)
506 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
507 if (NumRegs > 3 && TableEntry->copyAllListRegs)
508 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
509 }
510
511 if (TableEntry->isUpdating)
512 MIB.add(MI.getOperand(OpIdx++));
513
514 // Copy the addrmode6 operands.
515 MIB.add(MI.getOperand(OpIdx++));
516 MIB.add(MI.getOperand(OpIdx++));
517
518 // Copy the am6offset operand.
519 if (TableEntry->hasWritebackOperand) {
520 // TODO: The writing-back pseudo instructions we translate here are all
521 // defined to take am6offset nodes that are capable to represent both fixed
522 // and register forms. Some real instructions, however, do not rely on
523 // am6offset and have separate definitions for such forms. When this is the
524 // case, fixed forms do not take any offset nodes, so here we skip them for
525 // such instructions. Once all real and pseudo writing-back instructions are
526 // rewritten without use of am6offset nodes, this code will go away.
527 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
528 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed ||
529 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed ||
530 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed ||
531 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed ||
532 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed ||
533 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed ||
534 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed ||
535 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed) {
536 assert(AM6Offset.getReg() == 0 &&
537 "A fixed writing-back pseudo instruction provides an offset "
538 "register!");
539 } else {
540 MIB.add(AM6Offset);
541 }
542 }
543
544 // For an instruction writing double-spaced subregs, the pseudo instruction
545 // has an extra operand that is a use of the super-register. Record the
546 // operand index and skip over it.
547 unsigned SrcOpIdx = 0;
548 if(TableEntry->RealOpc != ARM::VLD2DUPd8x2 &&
549 TableEntry->RealOpc != ARM::VLD2DUPd16x2 &&
550 TableEntry->RealOpc != ARM::VLD2DUPd32x2) {
551 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc ||
552 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc ||
553 RegSpc == SingleHighTSpc)
554 SrcOpIdx = OpIdx++;
555 }
556
557 // Copy the predicate operands.
558 MIB.add(MI.getOperand(OpIdx++));
559 MIB.add(MI.getOperand(OpIdx++));
560
561 // Copy the super-register source operand used for double-spaced subregs over
562 // to the new instruction as an implicit operand.
563 if (SrcOpIdx != 0) {
564 MachineOperand MO = MI.getOperand(SrcOpIdx);
565 MO.setImplicit(true);
566 MIB.add(MO);
567 }
568 // Add an implicit def for the super-register.
569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
570 TransferImpOps(MI, MIB, MIB);
571
572 // Transfer memoperands.
573 MIB.cloneMemRefs(MI);
574 MI.eraseFromParent();
575 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
576 }
577
578 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
579 /// operands to real VST instructions with D register operands.
580 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
581 MachineInstr &MI = *MBBI;
582 MachineBasicBlock &MBB = *MI.getParent();
583 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
584
585 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
586 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
587 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
588 unsigned NumRegs = TableEntry->NumRegs;
589
590 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
591 TII->get(TableEntry->RealOpc));
592 unsigned OpIdx = 0;
593 if (TableEntry->isUpdating)
594 MIB.add(MI.getOperand(OpIdx++));
595
596 // Copy the addrmode6 operands.
597 MIB.add(MI.getOperand(OpIdx++));
598 MIB.add(MI.getOperand(OpIdx++));
599
600 if (TableEntry->hasWritebackOperand) {
601 // TODO: The writing-back pseudo instructions we translate here are all
602 // defined to take am6offset nodes that are capable to represent both fixed
603 // and register forms. Some real instructions, however, do not rely on
604 // am6offset and have separate definitions for such forms. When this is the
605 // case, fixed forms do not take any offset nodes, so here we skip them for
606 // such instructions. Once all real and pseudo writing-back instructions are
607 // rewritten without use of am6offset nodes, this code will go away.
608 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
609 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed ||
610 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed ||
611 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed ||
612 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed ||
613 TableEntry->RealOpc == ARM::VST1d8Twb_fixed ||
614 TableEntry->RealOpc == ARM::VST1d16Twb_fixed ||
615 TableEntry->RealOpc == ARM::VST1d32Twb_fixed ||
616 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) {
617 assert(AM6Offset.getReg() == 0 &&
618 "A fixed writing-back pseudo instruction provides an offset "
619 "register!");
620 } else {
621 MIB.add(AM6Offset);
622 }
623 }
624
625 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
626 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
627 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
628 unsigned D0, D1, D2, D3;
629 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
630 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
631 if (NumRegs > 1 && TableEntry->copyAllListRegs)
632 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
633 if (NumRegs > 2 && TableEntry->copyAllListRegs)
634 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
635 if (NumRegs > 3 && TableEntry->copyAllListRegs)
636 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
637
638 // Copy the predicate operands.
639 MIB.add(MI.getOperand(OpIdx++));
640 MIB.add(MI.getOperand(OpIdx++));
641
642 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
643 MIB->addRegisterKilled(SrcReg, TRI, true);
644 else if (!SrcIsUndef)
645 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
646 TransferImpOps(MI, MIB, MIB);
647
648 // Transfer memoperands.
649 MIB.cloneMemRefs(MI);
650 MI.eraseFromParent();
651 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
652 }
653
654 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
655 /// register operands to real instructions with D register operands.
656 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
657 MachineInstr &MI = *MBBI;
658 MachineBasicBlock &MBB = *MI.getParent();
659 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
660
661 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
662 assert(TableEntry && "NEONLdStTable lookup failed");
663 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
664 unsigned NumRegs = TableEntry->NumRegs;
665 unsigned RegElts = TableEntry->RegElts;
666
667 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
668 TII->get(TableEntry->RealOpc));
669 unsigned OpIdx = 0;
670 // The lane operand is always the 3rd from last operand, before the 2
671 // predicate operands.
672 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
673
674 // Adjust the lane and spacing as needed for Q registers.
675 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
676 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
677 RegSpc = OddDblSpc;
678 Lane -= RegElts;
679 }
680 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
681
682 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
683 unsigned DstReg = 0;
684 bool DstIsDead = false;
685 if (TableEntry->IsLoad) {
686 DstIsDead = MI.getOperand(OpIdx).isDead();
687 DstReg = MI.getOperand(OpIdx++).getReg();
688 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
689 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
690 if (NumRegs > 1)
691 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
692 if (NumRegs > 2)
693 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
694 if (NumRegs > 3)
695 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
696 }
697
698 if (TableEntry->isUpdating)
699 MIB.add(MI.getOperand(OpIdx++));
700
701 // Copy the addrmode6 operands.
702 MIB.add(MI.getOperand(OpIdx++));
703 MIB.add(MI.getOperand(OpIdx++));
704 // Copy the am6offset operand.
705 if (TableEntry->hasWritebackOperand)
706 MIB.add(MI.getOperand(OpIdx++));
707
708 // Grab the super-register source.
709 MachineOperand MO = MI.getOperand(OpIdx++);
710 if (!TableEntry->IsLoad)
711 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
712
713 // Add the subregs as sources of the new instruction.
714 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
715 getKillRegState(MO.isKill()));
716 MIB.addReg(D0, SrcFlags);
717 if (NumRegs > 1)
718 MIB.addReg(D1, SrcFlags);
719 if (NumRegs > 2)
720 MIB.addReg(D2, SrcFlags);
721 if (NumRegs > 3)
722 MIB.addReg(D3, SrcFlags);
723
724 // Add the lane number operand.
725 MIB.addImm(Lane);
726 OpIdx += 1;
727
728 // Copy the predicate operands.
729 MIB.add(MI.getOperand(OpIdx++));
730 MIB.add(MI.getOperand(OpIdx++));
731
732 // Copy the super-register source to be an implicit source.
733 MO.setImplicit(true);
734 MIB.add(MO);
735 if (TableEntry->IsLoad)
736 // Add an implicit def for the super-register.
737 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
738 TransferImpOps(MI, MIB, MIB);
739 // Transfer memoperands.
740 MIB.cloneMemRefs(MI);
741 MI.eraseFromParent();
742 }
743
744 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
745 /// register operands to real instructions with D register operands.
746 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
747 unsigned Opc, bool IsExt) {
748 MachineInstr &MI = *MBBI;
749 MachineBasicBlock &MBB = *MI.getParent();
750 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
751
752 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
753 unsigned OpIdx = 0;
754
755 // Transfer the destination register operand.
756 MIB.add(MI.getOperand(OpIdx++));
757 if (IsExt) {
758 MachineOperand VdSrc(MI.getOperand(OpIdx++));
759 MIB.add(VdSrc);
760 }
761
762 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
763 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
764 unsigned D0, D1, D2, D3;
765 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
766 MIB.addReg(D0);
767
768 // Copy the other source register operand.
769 MachineOperand VmSrc(MI.getOperand(OpIdx++));
770 MIB.add(VmSrc);
771
772 // Copy the predicate operands.
773 MIB.add(MI.getOperand(OpIdx++));
774 MIB.add(MI.getOperand(OpIdx++));
775
776 // Add an implicit kill and use for the super-reg.
777 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
778 TransferImpOps(MI, MIB, MIB);
779 MI.eraseFromParent();
780 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
781 }
782
783 static bool IsAnAddressOperand(const MachineOperand &MO) {
784 // This check is overly conservative. Unless we are certain that the machine
785 // operand is not a symbol reference, we return that it is a symbol reference.
786 // This is important as the load pair may not be split up Windows.
787 switch (MO.getType()) {
788 case MachineOperand::MO_Register:
789 case MachineOperand::MO_Immediate:
790 case MachineOperand::MO_CImmediate:
791 case MachineOperand::MO_FPImmediate:
792 return false;
793 case MachineOperand::MO_MachineBasicBlock:
794 return true;
795 case MachineOperand::MO_FrameIndex:
796 return false;
797 case MachineOperand::MO_ConstantPoolIndex:
798 case MachineOperand::MO_TargetIndex:
799 case MachineOperand::MO_JumpTableIndex:
800 case MachineOperand::MO_ExternalSymbol:
801 case MachineOperand::MO_GlobalAddress:
802 case MachineOperand::MO_BlockAddress:
803 return true;
804 case MachineOperand::MO_RegisterMask:
805 case MachineOperand::MO_RegisterLiveOut:
806 return false;
807 case MachineOperand::MO_Metadata:
808 case MachineOperand::MO_MCSymbol:
809 return true;
810 case MachineOperand::MO_CFIIndex:
811 return false;
812 case MachineOperand::MO_IntrinsicID:
813 case MachineOperand::MO_Predicate:
814 llvm_unreachable("should not exist post-isel");
815 }
816 llvm_unreachable("unhandled machine operand type");
817 }
818
819 static MachineOperand makeImplicit(const MachineOperand &MO) {
820 MachineOperand NewMO = MO;
821 NewMO.setImplicit();
822 return NewMO;
823 }
824
825 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
826 MachineBasicBlock::iterator &MBBI) {
827 MachineInstr &MI = *MBBI;
828 unsigned Opcode = MI.getOpcode();
829 unsigned PredReg = 0;
830 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
831 unsigned DstReg = MI.getOperand(0).getReg();
832 bool DstIsDead = MI.getOperand(0).isDead();
833 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
834 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
835 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
836 MachineInstrBuilder LO16, HI16;
837 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
838
839 if (!STI->hasV6T2Ops() &&
840 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
841 // FIXME Windows CE supports older ARM CPUs
842 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
843
844 // Expand into a movi + orr.
845 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
846 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
847 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
848 .addReg(DstReg);
849
850 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
851 unsigned ImmVal = (unsigned)MO.getImm();
852 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
853 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
854 LO16 = LO16.addImm(SOImmValV1);
855 HI16 = HI16.addImm(SOImmValV2);
856 LO16.cloneMemRefs(MI);
857 HI16.cloneMemRefs(MI);
858 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
859 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
860 if (isCC)
861 LO16.add(makeImplicit(MI.getOperand(1)));
862 TransferImpOps(MI, LO16, HI16);
863 MI.eraseFromParent();
864 return;
865 }
866
867 unsigned LO16Opc = 0;
868 unsigned HI16Opc = 0;
869 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
870 LO16Opc = ARM::t2MOVi16;
871 HI16Opc = ARM::t2MOVTi16;
872 } else {
873 LO16Opc = ARM::MOVi16;
874 HI16Opc = ARM::MOVTi16;
875 }
876
877 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
878 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
879 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
880 .addReg(DstReg);
881
882 switch (MO.getType()) {
883 case MachineOperand::MO_Immediate: {
884 unsigned Imm = MO.getImm();
885 unsigned Lo16 = Imm & 0xffff;
886 unsigned Hi16 = (Imm >> 16) & 0xffff;
887 LO16 = LO16.addImm(Lo16);
888 HI16 = HI16.addImm(Hi16);
889 break;
890 }
891 case MachineOperand::MO_ExternalSymbol: {
892 const char *ES = MO.getSymbolName();
893 unsigned TF = MO.getTargetFlags();
894 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16);
895 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16);
896 break;
897 }
898 default: {
899 const GlobalValue *GV = MO.getGlobal();
900 unsigned TF = MO.getTargetFlags();
901 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
902 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
903 break;
904 }
905 }
906
907 LO16.cloneMemRefs(MI);
908 HI16.cloneMemRefs(MI);
909 LO16.addImm(Pred).addReg(PredReg);
910 HI16.addImm(Pred).addReg(PredReg);
911
912 if (RequiresBundling)
913 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
914
915 if (isCC)
916 LO16.add(makeImplicit(MI.getOperand(1)));
917 TransferImpOps(MI, LO16, HI16);
918 MI.eraseFromParent();
919 LLVM_DEBUG(dbgs() << "To: "; LO16.getInstr()->dump(););
920 LLVM_DEBUG(dbgs() << "And: "; HI16.getInstr()->dump(););
921 }
922
923 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
924 /// possible. This only gets used at -O0 so we don't care about efficiency of
925 /// the generated code.
926 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
927 MachineBasicBlock::iterator MBBI,
928 unsigned LdrexOp, unsigned StrexOp,
929 unsigned UxtOp,
930 MachineBasicBlock::iterator &NextMBBI) {
931 bool IsThumb = STI->isThumb();
932 MachineInstr &MI = *MBBI;
933 DebugLoc DL = MI.getDebugLoc();
934 const MachineOperand &Dest = MI.getOperand(0);
935 unsigned TempReg = MI.getOperand(1).getReg();
936 // Duplicating undef operands into 2 instructions does not guarantee the same
937 // value on both; However undef should be replaced by xzr anyway.
938 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
939 unsigned AddrReg = MI.getOperand(2).getReg();
940 unsigned DesiredReg = MI.getOperand(3).getReg();
941 unsigned NewReg = MI.getOperand(4).getReg();
942
943 MachineFunction *MF = MBB.getParent();
944 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
945 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
946 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
947
948 MF->insert(++MBB.getIterator(), LoadCmpBB);
949 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
950 MF->insert(++StoreBB->getIterator(), DoneBB);
951
952 if (UxtOp) {
953 MachineInstrBuilder MIB =
954 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
955 .addReg(DesiredReg, RegState::Kill);
956 if (!IsThumb)
957 MIB.addImm(0);
958 MIB.add(predOps(ARMCC::AL));
959 }
960
961 // .Lloadcmp:
962 // ldrex rDest, [rAddr]
963 // cmp rDest, rDesired
964 // bne .Ldone
965
966 MachineInstrBuilder MIB;
967 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
968 MIB.addReg(AddrReg);
969 if (LdrexOp == ARM::t2LDREX)
970 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
971 MIB.add(predOps(ARMCC::AL));
972
973 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
974 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
975 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
976 .addReg(DesiredReg)
977 .add(predOps(ARMCC::AL));
978 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
979 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
980 .addMBB(DoneBB)
981 .addImm(ARMCC::NE)
982 .addReg(ARM::CPSR, RegState::Kill);
983 LoadCmpBB->addSuccessor(DoneBB);
984 LoadCmpBB->addSuccessor(StoreBB);
985
986 // .Lstore:
987 // strex rTempReg, rNew, [rAddr]
988 // cmp rTempReg, #0
989 // bne .Lloadcmp
990 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
991 .addReg(NewReg)
992 .addReg(AddrReg);
993 if (StrexOp == ARM::t2STREX)
994 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
995 MIB.add(predOps(ARMCC::AL));
996
997 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
998 BuildMI(StoreBB, DL, TII->get(CMPri))
999 .addReg(TempReg, RegState::Kill)
1000 .addImm(0)
1001 .add(predOps(ARMCC::AL));
1002 BuildMI(StoreBB, DL, TII->get(Bcc))
1003 .addMBB(LoadCmpBB)
1004 .addImm(ARMCC::NE)
1005 .addReg(ARM::CPSR, RegState::Kill);
1006 StoreBB->addSuccessor(LoadCmpBB);
1007 StoreBB->addSuccessor(DoneBB);
1008
1009 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
1010 DoneBB->transferSuccessors(&MBB);
1011
1012 MBB.addSuccessor(LoadCmpBB);
1013
1014 NextMBBI = MBB.end();
1015 MI.eraseFromParent();
1016
1017 // Recompute livein lists.
1018 LivePhysRegs LiveRegs;
1019 computeAndAddLiveIns(LiveRegs, *DoneBB);
1020 computeAndAddLiveIns(LiveRegs, *StoreBB);
1021 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1022 // Do an extra pass around the loop to get loop carried registers right.
1023 StoreBB->clearLiveIns();
1024 computeAndAddLiveIns(LiveRegs, *StoreBB);
1025 LoadCmpBB->clearLiveIns();
1026 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1027
1028 return true;
1029 }
1030
1031 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
1032 /// single GPRPair register), Thumb's take two separate registers so we need to
1033 /// extract the subregs from the pair.
1034 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
1035 unsigned Flags, bool IsThumb,
1036 const TargetRegisterInfo *TRI) {
1037 if (IsThumb) {
1038 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1039 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1040 MIB.addReg(RegLo, Flags);
1041 MIB.addReg(RegHi, Flags);
1042 } else
1043 MIB.addReg(Reg.getReg(), Flags);
1044 }
1045
1046 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
1047 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
1048 MachineBasicBlock::iterator MBBI,
1049 MachineBasicBlock::iterator &NextMBBI) {
1050 bool IsThumb = STI->isThumb();
1051 MachineInstr &MI = *MBBI;
1052 DebugLoc DL = MI.getDebugLoc();
1053 MachineOperand &Dest = MI.getOperand(0);
1054 unsigned TempReg = MI.getOperand(1).getReg();
1055 // Duplicating undef operands into 2 instructions does not guarantee the same
1056 // value on both; However undef should be replaced by xzr anyway.
1057 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
1058 unsigned AddrReg = MI.getOperand(2).getReg();
1059 unsigned DesiredReg = MI.getOperand(3).getReg();
1060 MachineOperand New = MI.getOperand(4);
1061 New.setIsKill(false);
1062
1063 unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
1064 unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
1065 unsigned DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
1066 unsigned DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
1067
1068 MachineFunction *MF = MBB.getParent();
1069 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1070 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1071 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1072
1073 MF->insert(++MBB.getIterator(), LoadCmpBB);
1074 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
1075 MF->insert(++StoreBB->getIterator(), DoneBB);
1076
1077 // .Lloadcmp:
1078 // ldrexd rDestLo, rDestHi, [rAddr]
1079 // cmp rDestLo, rDesiredLo
1080 // sbcs dead rTempReg, rDestHi, rDesiredHi
1081 // bne .Ldone
1082 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
1083 MachineInstrBuilder MIB;
1084 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
1085 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
1086 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1087
1088 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1089 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1090 .addReg(DestLo, getKillRegState(Dest.isDead()))
1091 .addReg(DesiredLo)
1092 .add(predOps(ARMCC::AL));
1093
1094 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1095 .addReg(DestHi, getKillRegState(Dest.isDead()))
1096 .addReg(DesiredHi)
1097 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1098
1099 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1100 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
1101 .addMBB(DoneBB)
1102 .addImm(ARMCC::NE)
1103 .addReg(ARM::CPSR, RegState::Kill);
1104 LoadCmpBB->addSuccessor(DoneBB);
1105 LoadCmpBB->addSuccessor(StoreBB);
1106
1107 // .Lstore:
1108 // strexd rTempReg, rNewLo, rNewHi, [rAddr]
1109 // cmp rTempReg, #0
1110 // bne .Lloadcmp
1111 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
1112 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
1113 unsigned Flags = getKillRegState(New.isDead());
1114 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI);
1115 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1116
1117 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
1118 BuildMI(StoreBB, DL, TII->get(CMPri))
1119 .addReg(TempReg, RegState::Kill)
1120 .addImm(0)
1121 .add(predOps(ARMCC::AL));
1122 BuildMI(StoreBB, DL, TII->get(Bcc))
1123 .addMBB(LoadCmpBB)
1124 .addImm(ARMCC::NE)
1125 .addReg(ARM::CPSR, RegState::Kill);
1126 StoreBB->addSuccessor(LoadCmpBB);
1127 StoreBB->addSuccessor(DoneBB);
1128
1129 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
1130 DoneBB->transferSuccessors(&MBB);
1131
1132 MBB.addSuccessor(LoadCmpBB);
1133
1134 NextMBBI = MBB.end();
1135 MI.eraseFromParent();
1136
1137 // Recompute livein lists.
1138 LivePhysRegs LiveRegs;
1139 computeAndAddLiveIns(LiveRegs, *DoneBB);
1140 computeAndAddLiveIns(LiveRegs, *StoreBB);
1141 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1142 // Do an extra pass around the loop to get loop carried registers right.
1143 StoreBB->clearLiveIns();
1144 computeAndAddLiveIns(LiveRegs, *StoreBB);
1145 LoadCmpBB->clearLiveIns();
1146 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1147
1148 return true;
1149 }
1150
1151
1152 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
1153 MachineBasicBlock::iterator MBBI,
1154 MachineBasicBlock::iterator &NextMBBI) {
1155 MachineInstr &MI = *MBBI;
1156 unsigned Opcode = MI.getOpcode();
1157 switch (Opcode) {
1158 default:
1159 return false;
1160
1161 case ARM::TCRETURNdi:
1162 case ARM::TCRETURNri: {
1163 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
1164 assert(MBBI->isReturn() &&
1165 "Can only insert epilog into returning blocks");
1166 unsigned RetOpcode = MBBI->getOpcode();
1167 DebugLoc dl = MBBI->getDebugLoc();
1168 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
1169 MBB.getParent()->getSubtarget().getInstrInfo());
1170
1171 // Tail call return: adjust the stack pointer and jump to callee.
1172 MBBI = MBB.getLastNonDebugInstr();
1173 MachineOperand &JumpTarget = MBBI->getOperand(0);
1174
1175 // Jump to label or value in register.
1176 if (RetOpcode == ARM::TCRETURNdi) {
1177 unsigned TCOpcode =
1178 STI->isThumb()
1179 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
1180 : ARM::TAILJMPd;
1181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1182 if (JumpTarget.isGlobal())
1183 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1184 JumpTarget.getTargetFlags());
1185 else {
1186 assert(JumpTarget.isSymbol());
1187 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1188 JumpTarget.getTargetFlags());
1189 }
1190
1191 // Add the default predicate in Thumb mode.
1192 if (STI->isThumb())
1193 MIB.add(predOps(ARMCC::AL));
1194 } else if (RetOpcode == ARM::TCRETURNri) {
1195 unsigned Opcode =
1196 STI->isThumb() ? ARM::tTAILJMPr
1197 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
1198 BuildMI(MBB, MBBI, dl,
1199 TII.get(Opcode))
1200 .addReg(JumpTarget.getReg(), RegState::Kill);
1201 }
1202
1203 auto NewMI = std::prev(MBBI);
1204 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1205 NewMI->addOperand(MBBI->getOperand(i));
1206
1207 // Delete the pseudo instruction TCRETURN.
1208 MBB.erase(MBBI);
1209 MBBI = NewMI;
1210 return true;
1211 }
1212 case ARM::VMOVScc:
1213 case ARM::VMOVDcc: {
1214 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
1215 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
1216 MI.getOperand(1).getReg())
1217 .add(MI.getOperand(2))
1218 .addImm(MI.getOperand(3).getImm()) // 'pred'
1219 .add(MI.getOperand(4))
1220 .add(makeImplicit(MI.getOperand(1)));
1221
1222 MI.eraseFromParent();
1223 return true;
1224 }
1225 case ARM::t2MOVCCr:
1226 case ARM::MOVCCr: {
1227 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
1228 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1229 MI.getOperand(1).getReg())
1230 .add(MI.getOperand(2))
1231 .addImm(MI.getOperand(3).getImm()) // 'pred'
1232 .add(MI.getOperand(4))
1233 .add(condCodeOp()) // 's' bit
1234 .add(makeImplicit(MI.getOperand(1)));
1235
1236 MI.eraseFromParent();
1237 return true;
1238 }
1239 case ARM::MOVCCsi: {
1240 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1241 (MI.getOperand(1).getReg()))
1242 .add(MI.getOperand(2))
1243 .addImm(MI.getOperand(3).getImm())
1244 .addImm(MI.getOperand(4).getImm()) // 'pred'
1245 .add(MI.getOperand(5))
1246 .add(condCodeOp()) // 's' bit
1247 .add(makeImplicit(MI.getOperand(1)));
1248
1249 MI.eraseFromParent();
1250 return true;
1251 }
1252 case ARM::MOVCCsr: {
1253 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
1254 (MI.getOperand(1).getReg()))
1255 .add(MI.getOperand(2))
1256 .add(MI.getOperand(3))
1257 .addImm(MI.getOperand(4).getImm())
1258 .addImm(MI.getOperand(5).getImm()) // 'pred'
1259 .add(MI.getOperand(6))
1260 .add(condCodeOp()) // 's' bit
1261 .add(makeImplicit(MI.getOperand(1)));
1262
1263 MI.eraseFromParent();
1264 return true;
1265 }
1266 case ARM::t2MOVCCi16:
1267 case ARM::MOVCCi16: {
1268 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
1269 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1270 MI.getOperand(1).getReg())
1271 .addImm(MI.getOperand(2).getImm())
1272 .addImm(MI.getOperand(3).getImm()) // 'pred'
1273 .add(MI.getOperand(4))
1274 .add(makeImplicit(MI.getOperand(1)));
1275 MI.eraseFromParent();
1276 return true;
1277 }
1278 case ARM::t2MOVCCi:
1279 case ARM::MOVCCi: {
1280 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
1281 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1282 MI.getOperand(1).getReg())
1283 .addImm(MI.getOperand(2).getImm())
1284 .addImm(MI.getOperand(3).getImm()) // 'pred'
1285 .add(MI.getOperand(4))
1286 .add(condCodeOp()) // 's' bit
1287 .add(makeImplicit(MI.getOperand(1)));
1288
1289 MI.eraseFromParent();
1290 return true;
1291 }
1292 case ARM::t2MVNCCi:
1293 case ARM::MVNCCi: {
1294 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
1295 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1296 MI.getOperand(1).getReg())
1297 .addImm(MI.getOperand(2).getImm())
1298 .addImm(MI.getOperand(3).getImm()) // 'pred'
1299 .add(MI.getOperand(4))
1300 .add(condCodeOp()) // 's' bit
1301 .add(makeImplicit(MI.getOperand(1)));
1302
1303 MI.eraseFromParent();
1304 return true;
1305 }
1306 case ARM::t2MOVCClsl:
1307 case ARM::t2MOVCClsr:
1308 case ARM::t2MOVCCasr:
1309 case ARM::t2MOVCCror: {
1310 unsigned NewOpc;
1311 switch (Opcode) {
1312 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
1313 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
1314 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
1315 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
1316 default: llvm_unreachable("unexpeced conditional move");
1317 }
1318 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1319 MI.getOperand(1).getReg())
1320 .add(MI.getOperand(2))
1321 .addImm(MI.getOperand(3).getImm())
1322 .addImm(MI.getOperand(4).getImm()) // 'pred'
1323 .add(MI.getOperand(5))
1324 .add(condCodeOp()) // 's' bit
1325 .add(makeImplicit(MI.getOperand(1)));
1326 MI.eraseFromParent();
1327 return true;
1328 }
1329 case ARM::Int_eh_sjlj_dispatchsetup: {
1330 MachineFunction &MF = *MI.getParent()->getParent();
1331 const ARMBaseInstrInfo *AII =
1332 static_cast<const ARMBaseInstrInfo*>(TII);
1333 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
1334 // For functions using a base pointer, we rematerialize it (via the frame
1335 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
1336 // for us. Otherwise, expand to nothing.
1337 if (RI.hasBasePointer(MF)) {
1338 int32_t NumBytes = AFI->getFramePtrSpillOffset();
1339 unsigned FramePtr = RI.getFrameRegister(MF);
1340 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
1341 "base pointer without frame pointer?");
1342
1343 if (AFI->isThumb2Function()) {
1344 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1345 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
1346 } else if (AFI->isThumbFunction()) {
1347 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1348 FramePtr, -NumBytes, *TII, RI);
1349 } else {
1350 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1351 FramePtr, -NumBytes, ARMCC::AL, 0,
1352 *TII);
1353 }
1354 // If there's dynamic realignment, adjust for it.
1355 if (RI.needsStackRealignment(MF)) {
1356 MachineFrameInfo &MFI = MF.getFrameInfo();
1357 unsigned MaxAlign = MFI.getMaxAlignment();
1358 assert (!AFI->isThumb1OnlyFunction());
1359 // Emit bic r6, r6, MaxAlign
1360 assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
1361 "immediates larger than 256 with all lower "
1362 "bits set.");
1363 unsigned bicOpc = AFI->isThumbFunction() ?
1364 ARM::t2BICri : ARM::BICri;
1365 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
1366 .addReg(ARM::R6, RegState::Kill)
1367 .addImm(MaxAlign - 1)
1368 .add(predOps(ARMCC::AL))
1369 .add(condCodeOp());
1370 }
1371
1372 }
1373 MI.eraseFromParent();
1374 return true;
1375 }
1376
1377 case ARM::MOVsrl_flag:
1378 case ARM::MOVsra_flag: {
1379 // These are just fancy MOVs instructions.
1380 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1381 MI.getOperand(0).getReg())
1382 .add(MI.getOperand(1))
1383 .addImm(ARM_AM::getSORegOpc(
1384 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1))
1385 .add(predOps(ARMCC::AL))
1386 .addReg(ARM::CPSR, RegState::Define);
1387 MI.eraseFromParent();
1388 return true;
1389 }
1390 case ARM::RRX: {
1391 // This encodes as "MOVs Rd, Rm, rrx
1392 MachineInstrBuilder MIB =
1393 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1394 MI.getOperand(0).getReg())
1395 .add(MI.getOperand(1))
1396 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
1397 .add(predOps(ARMCC::AL))
1398 .add(condCodeOp());
1399 TransferImpOps(MI, MIB, MIB);
1400 MI.eraseFromParent();
1401 return true;
1402 }
1403 case ARM::tTPsoft:
1404 case ARM::TPsoft: {
1405 const bool Thumb = Opcode == ARM::tTPsoft;
1406
1407 MachineInstrBuilder MIB;
1408 if (STI->genLongCalls()) {
1409 MachineFunction *MF = MBB.getParent();
1410 MachineConstantPool *MCP = MF->getConstantPool();
1411 unsigned PCLabelID = AFI->createPICLabelUId();
1412 MachineConstantPoolValue *CPV =
1413 ARMConstantPoolSymbol::Create(MF->getFunction().getContext(),
1414 "__aeabi_read_tp", PCLabelID, 0);
1415 unsigned Reg = MI.getOperand(0).getReg();
1416 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1417 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1418 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1419 if (!Thumb)
1420 MIB.addImm(0);
1421 MIB.add(predOps(ARMCC::AL));
1422
1423 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1424 TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1425 if (Thumb)
1426 MIB.add(predOps(ARMCC::AL));
1427 MIB.addReg(Reg, RegState::Kill);
1428 } else {
1429 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1430 TII->get(Thumb ? ARM::tBL : ARM::BL));
1431 if (Thumb)
1432 MIB.add(predOps(ARMCC::AL));
1433 MIB.addExternalSymbol("__aeabi_read_tp", 0);
1434 }
1435
1436 MIB.cloneMemRefs(MI);
1437 TransferImpOps(MI, MIB, MIB);
1438 MI.eraseFromParent();
1439 return true;
1440 }
1441 case ARM::tLDRpci_pic:
1442 case ARM::t2LDRpci_pic: {
1443 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
1444 ? ARM::tLDRpci : ARM::t2LDRpci;
1445 unsigned DstReg = MI.getOperand(0).getReg();
1446 bool DstIsDead = MI.getOperand(0).isDead();
1447 MachineInstrBuilder MIB1 =
1448 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
1449 .add(MI.getOperand(1))
1450 .add(predOps(ARMCC::AL));
1451 MIB1.cloneMemRefs(MI);
1452 MachineInstrBuilder MIB2 =
1453 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
1454 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1455 .addReg(DstReg)
1456 .add(MI.getOperand(2));
1457 TransferImpOps(MI, MIB1, MIB2);
1458 MI.eraseFromParent();
1459 return true;
1460 }
1461
1462 case ARM::LDRLIT_ga_abs:
1463 case ARM::LDRLIT_ga_pcrel:
1464 case ARM::LDRLIT_ga_pcrel_ldr:
1465 case ARM::tLDRLIT_ga_abs:
1466 case ARM::tLDRLIT_ga_pcrel: {
1467 unsigned DstReg = MI.getOperand(0).getReg();
1468 bool DstIsDead = MI.getOperand(0).isDead();
1469 const MachineOperand &MO1 = MI.getOperand(1);
1470 auto Flags = MO1.getTargetFlags();
1471 const GlobalValue *GV = MO1.getGlobal();
1472 bool IsARM =
1473 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1474 bool IsPIC =
1475 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1476 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1477 unsigned PICAddOpc =
1478 IsARM
1479 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1480 : ARM::tPICADD;
1481
1482 // We need a new const-pool entry to load from.
1483 MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
1484 unsigned ARMPCLabelIndex = 0;
1485 MachineConstantPoolValue *CPV;
1486
1487 if (IsPIC) {
1488 unsigned PCAdj = IsARM ? 8 : 4;
1489 auto Modifier = (Flags & ARMII::MO_GOT)
1490 ? ARMCP::GOT_PREL
1491 : ARMCP::no_modifier;
1492 ARMPCLabelIndex = AFI->createPICLabelUId();
1493 CPV = ARMConstantPoolConstant::Create(
1494 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier,
1495 /*AddCurrentAddr*/ Modifier == ARMCP::GOT_PREL);
1496 } else
1497 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
1498
1499 MachineInstrBuilder MIB =
1500 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1501 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1502 if (IsARM)
1503 MIB.addImm(0);
1504 MIB.add(predOps(ARMCC::AL));
1505
1506 if (IsPIC) {
1507 MachineInstrBuilder MIB =
1508 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1509 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1510 .addReg(DstReg)
1511 .addImm(ARMPCLabelIndex);
1512
1513 if (IsARM)
1514 MIB.add(predOps(ARMCC::AL));
1515 }
1516
1517 MI.eraseFromParent();
1518 return true;
1519 }
1520 case ARM::MOV_ga_pcrel:
1521 case ARM::MOV_ga_pcrel_ldr:
1522 case ARM::t2MOV_ga_pcrel: {
1523 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
1524 unsigned LabelId = AFI->createPICLabelUId();
1525 unsigned DstReg = MI.getOperand(0).getReg();
1526 bool DstIsDead = MI.getOperand(0).isDead();
1527 const MachineOperand &MO1 = MI.getOperand(1);
1528 const GlobalValue *GV = MO1.getGlobal();
1529 unsigned TF = MO1.getTargetFlags();
1530 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1531 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1532 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1533 unsigned LO16TF = TF | ARMII::MO_LO16;
1534 unsigned HI16TF = TF | ARMII::MO_HI16;
1535 unsigned PICAddOpc = isARM
1536 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1537 : ARM::tPICADD;
1538 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1539 TII->get(LO16Opc), DstReg)
1540 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
1541 .addImm(LabelId);
1542
1543 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
1544 .addReg(DstReg)
1545 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
1546 .addImm(LabelId);
1547
1548 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1549 TII->get(PICAddOpc))
1550 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1551 .addReg(DstReg).addImm(LabelId);
1552 if (isARM) {
1553 MIB3.add(predOps(ARMCC::AL));
1554 if (Opcode == ARM::MOV_ga_pcrel_ldr)
1555 MIB3.cloneMemRefs(MI);
1556 }
1557 TransferImpOps(MI, MIB1, MIB3);
1558 MI.eraseFromParent();
1559 return true;
1560 }
1561
1562 case ARM::MOVi32imm:
1563 case ARM::MOVCCi32imm:
1564 case ARM::t2MOVi32imm:
1565 case ARM::t2MOVCCi32imm:
1566 ExpandMOV32BitImm(MBB, MBBI);
1567 return true;
1568
1569 case ARM::SUBS_PC_LR: {
1570 MachineInstrBuilder MIB =
1571 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1572 .addReg(ARM::LR)
1573 .add(MI.getOperand(0))
1574 .add(MI.getOperand(1))
1575 .add(MI.getOperand(2))
1576 .addReg(ARM::CPSR, RegState::Undef);
1577 TransferImpOps(MI, MIB, MIB);
1578 MI.eraseFromParent();
1579 return true;
1580 }
1581 case ARM::VLDMQIA: {
1582 unsigned NewOpc = ARM::VLDMDIA;
1583 MachineInstrBuilder MIB =
1584 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1585 unsigned OpIdx = 0;
1586
1587 // Grab the Q register destination.
1588 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1589 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1590
1591 // Copy the source register.
1592 MIB.add(MI.getOperand(OpIdx++));
1593
1594 // Copy the predicate operands.
1595 MIB.add(MI.getOperand(OpIdx++));
1596 MIB.add(MI.getOperand(OpIdx++));
1597
1598 // Add the destination operands (D subregs).
1599 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1600 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1601 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1602 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1603
1604 // Add an implicit def for the super-register.
1605 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1606 TransferImpOps(MI, MIB, MIB);
1607 MIB.cloneMemRefs(MI);
1608 MI.eraseFromParent();
1609 return true;
1610 }
1611
1612 case ARM::VSTMQIA: {
1613 unsigned NewOpc = ARM::VSTMDIA;
1614 MachineInstrBuilder MIB =
1615 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1616 unsigned OpIdx = 0;
1617
1618 // Grab the Q register source.
1619 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1620 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1621
1622 // Copy the destination register.
1623 MachineOperand Dst(MI.getOperand(OpIdx++));
1624 MIB.add(Dst);
1625
1626 // Copy the predicate operands.
1627 MIB.add(MI.getOperand(OpIdx++));
1628 MIB.add(MI.getOperand(OpIdx++));
1629
1630 // Add the source operands (D subregs).
1631 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1632 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1633 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1634 .addReg(D1, SrcIsKill ? RegState::Kill : 0);
1635
1636 if (SrcIsKill) // Add an implicit kill for the Q register.
1637 MIB->addRegisterKilled(SrcReg, TRI, true);
1638
1639 TransferImpOps(MI, MIB, MIB);
1640 MIB.cloneMemRefs(MI);
1641 MI.eraseFromParent();
1642 return true;
1643 }
1644
1645 case ARM::VLD2q8Pseudo:
1646 case ARM::VLD2q16Pseudo:
1647 case ARM::VLD2q32Pseudo:
1648 case ARM::VLD2q8PseudoWB_fixed:
1649 case ARM::VLD2q16PseudoWB_fixed:
1650 case ARM::VLD2q32PseudoWB_fixed:
1651 case ARM::VLD2q8PseudoWB_register:
1652 case ARM::VLD2q16PseudoWB_register:
1653 case ARM::VLD2q32PseudoWB_register:
1654 case ARM::VLD3d8Pseudo:
1655 case ARM::VLD3d16Pseudo:
1656 case ARM::VLD3d32Pseudo:
1657 case ARM::VLD1d8TPseudo:
1658 case ARM::VLD1d16TPseudo:
1659 case ARM::VLD1d32TPseudo:
1660 case ARM::VLD1d64TPseudo:
1661 case ARM::VLD1d64TPseudoWB_fixed:
1662 case ARM::VLD1d64TPseudoWB_register:
1663 case ARM::VLD3d8Pseudo_UPD:
1664 case ARM::VLD3d16Pseudo_UPD:
1665 case ARM::VLD3d32Pseudo_UPD:
1666 case ARM::VLD3q8Pseudo_UPD:
1667 case ARM::VLD3q16Pseudo_UPD:
1668 case ARM::VLD3q32Pseudo_UPD:
1669 case ARM::VLD3q8oddPseudo:
1670 case ARM::VLD3q16oddPseudo:
1671 case ARM::VLD3q32oddPseudo:
1672 case ARM::VLD3q8oddPseudo_UPD:
1673 case ARM::VLD3q16oddPseudo_UPD:
1674 case ARM::VLD3q32oddPseudo_UPD:
1675 case ARM::VLD4d8Pseudo:
1676 case ARM::VLD4d16Pseudo:
1677 case ARM::VLD4d32Pseudo:
1678 case ARM::VLD1d8QPseudo:
1679 case ARM::VLD1d16QPseudo:
1680 case ARM::VLD1d32QPseudo:
1681 case ARM::VLD1d64QPseudo:
1682 case ARM::VLD1d64QPseudoWB_fixed:
1683 case ARM::VLD1d64QPseudoWB_register:
1684 case ARM::VLD1q8HighQPseudo:
1685 case ARM::VLD1q8LowQPseudo_UPD:
1686 case ARM::VLD1q8HighTPseudo:
1687 case ARM::VLD1q8LowTPseudo_UPD:
1688 case ARM::VLD1q16HighQPseudo:
1689 case ARM::VLD1q16LowQPseudo_UPD:
1690 case ARM::VLD1q16HighTPseudo:
1691 case ARM::VLD1q16LowTPseudo_UPD:
1692 case ARM::VLD1q32HighQPseudo:
1693 case ARM::VLD1q32LowQPseudo_UPD:
1694 case ARM::VLD1q32HighTPseudo:
1695 case ARM::VLD1q32LowTPseudo_UPD:
1696 case ARM::VLD1q64HighQPseudo:
1697 case ARM::VLD1q64LowQPseudo_UPD:
1698 case ARM::VLD1q64HighTPseudo:
1699 case ARM::VLD1q64LowTPseudo_UPD:
1700 case ARM::VLD4d8Pseudo_UPD:
1701 case ARM::VLD4d16Pseudo_UPD:
1702 case ARM::VLD4d32Pseudo_UPD:
1703 case ARM::VLD4q8Pseudo_UPD:
1704 case ARM::VLD4q16Pseudo_UPD:
1705 case ARM::VLD4q32Pseudo_UPD:
1706 case ARM::VLD4q8oddPseudo:
1707 case ARM::VLD4q16oddPseudo:
1708 case ARM::VLD4q32oddPseudo:
1709 case ARM::VLD4q8oddPseudo_UPD:
1710 case ARM::VLD4q16oddPseudo_UPD:
1711 case ARM::VLD4q32oddPseudo_UPD:
1712 case ARM::VLD3DUPd8Pseudo:
1713 case ARM::VLD3DUPd16Pseudo:
1714 case ARM::VLD3DUPd32Pseudo:
1715 case ARM::VLD3DUPd8Pseudo_UPD:
1716 case ARM::VLD3DUPd16Pseudo_UPD:
1717 case ARM::VLD3DUPd32Pseudo_UPD:
1718 case ARM::VLD4DUPd8Pseudo:
1719 case ARM::VLD4DUPd16Pseudo:
1720 case ARM::VLD4DUPd32Pseudo:
1721 case ARM::VLD4DUPd8Pseudo_UPD:
1722 case ARM::VLD4DUPd16Pseudo_UPD:
1723 case ARM::VLD4DUPd32Pseudo_UPD:
1724 case ARM::VLD2DUPq8EvenPseudo:
1725 case ARM::VLD2DUPq8OddPseudo:
1726 case ARM::VLD2DUPq16EvenPseudo:
1727 case ARM::VLD2DUPq16OddPseudo:
1728 case ARM::VLD2DUPq32EvenPseudo:
1729 case ARM::VLD2DUPq32OddPseudo:
1730 case ARM::VLD3DUPq8EvenPseudo:
1731 case ARM::VLD3DUPq8OddPseudo:
1732 case ARM::VLD3DUPq16EvenPseudo:
1733 case ARM::VLD3DUPq16OddPseudo:
1734 case ARM::VLD3DUPq32EvenPseudo:
1735 case ARM::VLD3DUPq32OddPseudo:
1736 case ARM::VLD4DUPq8EvenPseudo:
1737 case ARM::VLD4DUPq8OddPseudo:
1738 case ARM::VLD4DUPq16EvenPseudo:
1739 case ARM::VLD4DUPq16OddPseudo:
1740 case ARM::VLD4DUPq32EvenPseudo:
1741 case ARM::VLD4DUPq32OddPseudo:
1742 ExpandVLD(MBBI);
1743 return true;
1744
1745 case ARM::VST2q8Pseudo:
1746 case ARM::VST2q16Pseudo:
1747 case ARM::VST2q32Pseudo:
1748 case ARM::VST2q8PseudoWB_fixed:
1749 case ARM::VST2q16PseudoWB_fixed:
1750 case ARM::VST2q32PseudoWB_fixed:
1751 case ARM::VST2q8PseudoWB_register:
1752 case ARM::VST2q16PseudoWB_register:
1753 case ARM::VST2q32PseudoWB_register:
1754 case ARM::VST3d8Pseudo:
1755 case ARM::VST3d16Pseudo:
1756 case ARM::VST3d32Pseudo:
1757 case ARM::VST1d8TPseudo:
1758 case ARM::VST1d16TPseudo:
1759 case ARM::VST1d32TPseudo:
1760 case ARM::VST1d64TPseudo:
1761 case ARM::VST3d8Pseudo_UPD:
1762 case ARM::VST3d16Pseudo_UPD:
1763 case ARM::VST3d32Pseudo_UPD:
1764 case ARM::VST1d64TPseudoWB_fixed:
1765 case ARM::VST1d64TPseudoWB_register:
1766 case ARM::VST3q8Pseudo_UPD:
1767 case ARM::VST3q16Pseudo_UPD:
1768 case ARM::VST3q32Pseudo_UPD:
1769 case ARM::VST3q8oddPseudo:
1770 case ARM::VST3q16oddPseudo:
1771 case ARM::VST3q32oddPseudo:
1772 case ARM::VST3q8oddPseudo_UPD:
1773 case ARM::VST3q16oddPseudo_UPD:
1774 case ARM::VST3q32oddPseudo_UPD:
1775 case ARM::VST4d8Pseudo:
1776 case ARM::VST4d16Pseudo:
1777 case ARM::VST4d32Pseudo:
1778 case ARM::VST1d8QPseudo:
1779 case ARM::VST1d16QPseudo:
1780 case ARM::VST1d32QPseudo:
1781 case ARM::VST1d64QPseudo:
1782 case ARM::VST4d8Pseudo_UPD:
1783 case ARM::VST4d16Pseudo_UPD:
1784 case ARM::VST4d32Pseudo_UPD:
1785 case ARM::VST1d64QPseudoWB_fixed:
1786 case ARM::VST1d64QPseudoWB_register:
1787 case ARM::VST1q8HighQPseudo:
1788 case ARM::VST1q8LowQPseudo_UPD:
1789 case ARM::VST1q8HighTPseudo:
1790 case ARM::VST1q8LowTPseudo_UPD:
1791 case ARM::VST1q16HighQPseudo:
1792 case ARM::VST1q16LowQPseudo_UPD:
1793 case ARM::VST1q16HighTPseudo:
1794 case ARM::VST1q16LowTPseudo_UPD:
1795 case ARM::VST1q32HighQPseudo:
1796 case ARM::VST1q32LowQPseudo_UPD:
1797 case ARM::VST1q32HighTPseudo:
1798 case ARM::VST1q32LowTPseudo_UPD:
1799 case ARM::VST1q64HighQPseudo:
1800 case ARM::VST1q64LowQPseudo_UPD:
1801 case ARM::VST1q64HighTPseudo:
1802 case ARM::VST1q64LowTPseudo_UPD:
1803 case ARM::VST4q8Pseudo_UPD:
1804 case ARM::VST4q16Pseudo_UPD:
1805 case ARM::VST4q32Pseudo_UPD:
1806 case ARM::VST4q8oddPseudo:
1807 case ARM::VST4q16oddPseudo:
1808 case ARM::VST4q32oddPseudo:
1809 case ARM::VST4q8oddPseudo_UPD:
1810 case ARM::VST4q16oddPseudo_UPD:
1811 case ARM::VST4q32oddPseudo_UPD:
1812 ExpandVST(MBBI);
1813 return true;
1814
1815 case ARM::VLD1LNq8Pseudo:
1816 case ARM::VLD1LNq16Pseudo:
1817 case ARM::VLD1LNq32Pseudo:
1818 case ARM::VLD1LNq8Pseudo_UPD:
1819 case ARM::VLD1LNq16Pseudo_UPD:
1820 case ARM::VLD1LNq32Pseudo_UPD:
1821 case ARM::VLD2LNd8Pseudo:
1822 case ARM::VLD2LNd16Pseudo:
1823 case ARM::VLD2LNd32Pseudo:
1824 case ARM::VLD2LNq16Pseudo:
1825 case ARM::VLD2LNq32Pseudo:
1826 case ARM::VLD2LNd8Pseudo_UPD:
1827 case ARM::VLD2LNd16Pseudo_UPD:
1828 case ARM::VLD2LNd32Pseudo_UPD:
1829 case ARM::VLD2LNq16Pseudo_UPD:
1830 case ARM::VLD2LNq32Pseudo_UPD:
1831 case ARM::VLD3LNd8Pseudo:
1832 case ARM::VLD3LNd16Pseudo:
1833 case ARM::VLD3LNd32Pseudo:
1834 case ARM::VLD3LNq16Pseudo:
1835 case ARM::VLD3LNq32Pseudo:
1836 case ARM::VLD3LNd8Pseudo_UPD:
1837 case ARM::VLD3LNd16Pseudo_UPD:
1838 case ARM::VLD3LNd32Pseudo_UPD:
1839 case ARM::VLD3LNq16Pseudo_UPD:
1840 case ARM::VLD3LNq32Pseudo_UPD:
1841 case ARM::VLD4LNd8Pseudo:
1842 case ARM::VLD4LNd16Pseudo:
1843 case ARM::VLD4LNd32Pseudo:
1844 case ARM::VLD4LNq16Pseudo:
1845 case ARM::VLD4LNq32Pseudo:
1846 case ARM::VLD4LNd8Pseudo_UPD:
1847 case ARM::VLD4LNd16Pseudo_UPD:
1848 case ARM::VLD4LNd32Pseudo_UPD:
1849 case ARM::VLD4LNq16Pseudo_UPD:
1850 case ARM::VLD4LNq32Pseudo_UPD:
1851 case ARM::VST1LNq8Pseudo:
1852 case ARM::VST1LNq16Pseudo:
1853 case ARM::VST1LNq32Pseudo:
1854 case ARM::VST1LNq8Pseudo_UPD:
1855 case ARM::VST1LNq16Pseudo_UPD:
1856 case ARM::VST1LNq32Pseudo_UPD:
1857 case ARM::VST2LNd8Pseudo:
1858 case ARM::VST2LNd16Pseudo:
1859 case ARM::VST2LNd32Pseudo:
1860 case ARM::VST2LNq16Pseudo:
1861 case ARM::VST2LNq32Pseudo:
1862 case ARM::VST2LNd8Pseudo_UPD:
1863 case ARM::VST2LNd16Pseudo_UPD:
1864 case ARM::VST2LNd32Pseudo_UPD:
1865 case ARM::VST2LNq16Pseudo_UPD:
1866 case ARM::VST2LNq32Pseudo_UPD:
1867 case ARM::VST3LNd8Pseudo:
1868 case ARM::VST3LNd16Pseudo:
1869 case ARM::VST3LNd32Pseudo:
1870 case ARM::VST3LNq16Pseudo:
1871 case ARM::VST3LNq32Pseudo:
1872 case ARM::VST3LNd8Pseudo_UPD:
1873 case ARM::VST3LNd16Pseudo_UPD:
1874 case ARM::VST3LNd32Pseudo_UPD:
1875 case ARM::VST3LNq16Pseudo_UPD:
1876 case ARM::VST3LNq32Pseudo_UPD:
1877 case ARM::VST4LNd8Pseudo:
1878 case ARM::VST4LNd16Pseudo:
1879 case ARM::VST4LNd32Pseudo:
1880 case ARM::VST4LNq16Pseudo:
1881 case ARM::VST4LNq32Pseudo:
1882 case ARM::VST4LNd8Pseudo_UPD:
1883 case ARM::VST4LNd16Pseudo_UPD:
1884 case ARM::VST4LNd32Pseudo_UPD:
1885 case ARM::VST4LNq16Pseudo_UPD:
1886 case ARM::VST4LNq32Pseudo_UPD:
1887 ExpandLaneOp(MBBI);
1888 return true;
1889
1890 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1891 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1892 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1893 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1894
1895 case ARM::CMP_SWAP_8:
1896 if (STI->isThumb())
1897 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
1898 ARM::tUXTB, NextMBBI);
1899 else
1900 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB,
1901 ARM::UXTB, NextMBBI);
1902 case ARM::CMP_SWAP_16:
1903 if (STI->isThumb())
1904 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH,
1905 ARM::tUXTH, NextMBBI);
1906 else
1907 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH,
1908 ARM::UXTH, NextMBBI);
1909 case ARM::CMP_SWAP_32:
1910 if (STI->isThumb())
1911 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
1912 NextMBBI);
1913 else
1914 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
1915
1916 case ARM::CMP_SWAP_64:
1917 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
1918 }
1919 }
1920
1921 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1922 bool Modified = false;
1923
1924 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1925 while (MBBI != E) {
1926 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1927 Modified |= ExpandMI(MBB, MBBI, NMBBI);
1928 MBBI = NMBBI;
1929 }
1930
1931 return Modified;
1932 }
1933
1934 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1935 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1936 TII = STI->getInstrInfo();
1937 TRI = STI->getRegisterInfo();
1938 AFI = MF.getInfo<ARMFunctionInfo>();
1939
1940 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"
1941 << "********** Function: " << MF.getName() << '\n');
1942
1943 bool Modified = false;
1944 for (MachineBasicBlock &MBB : MF)
1945 Modified |= ExpandMBB(MBB);
1946 if (VerifyARMPseudo)
1947 MF.verify(this, "After expanding ARM pseudo instructions.");
1948
1949 LLVM_DEBUG(dbgs() << "***************************************************\n");
1950 return Modified;
1951 }
1952
1953 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1954 /// expansion pass.
1955 FunctionPass *llvm::createARMExpandPseudoPass() {
1956 return new ARMExpandPseudo();
1957 }
The low level virtual machine