lib/Target/ARM/ARMSubtarget.h

   1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the ARM specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
  14 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
  15
  16 #include "ARMBaseInstrInfo.h"
  17 #include "ARMBaseRegisterInfo.h"
  18 #include "ARMConstantPoolValue.h"
  19 #include "ARMFrameLowering.h"
  20 #include "ARMISelLowering.h"
  21 #include "ARMSelectionDAGInfo.h"
  22 #include "llvm/ADT/Triple.h"
  23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  24 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  25 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  26 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  27 #include "llvm/CodeGen/MachineFunction.h"
  28 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  29 #include "llvm/MC/MCInstrItineraries.h"
  30 #include "llvm/MC/MCSchedule.h"
  31 #include "llvm/Target/TargetOptions.h"
  32 #include <memory>
  33 #include <string>
  34
  35 #define GET_SUBTARGETINFO_HEADER
  36 #include "ARMGenSubtargetInfo.inc"
  37
  38 namespace llvm {
  39
  40 class ARMBaseTargetMachine;
  41 class GlobalValue;
  42 class StringRef;
  43
  44 class ARMSubtarget : public ARMGenSubtargetInfo {
  45 protected:
  46   enum ARMProcFamilyEnum {
  47     Others,
  48
  49     CortexA12,
  50     CortexA15,
  51     CortexA17,
  52     CortexA32,
  53     CortexA35,
  54     CortexA5,
  55     CortexA53,
  56     CortexA55,
  57     CortexA57,
  58     CortexA7,
  59     CortexA72,
  60     CortexA73,
  61     CortexA75,
  62     CortexA76,
  63     CortexA8,
  64     CortexA9,
  65     CortexM3,
  66     CortexR4,
  67     CortexR4F,
  68     CortexR5,
  69     CortexR52,
  70     CortexR7,
  71     Exynos,
  72     Krait,
  73     Kryo,
  74     NeoverseN1,
  75     Swift
  76   };
  77   enum ARMProcClassEnum {
  78     None,
  79
  80     AClass,
  81     MClass,
  82     RClass
  83   };
  84   enum ARMArchEnum {
  85     ARMv2,
  86     ARMv2a,
  87     ARMv3,
  88     ARMv3m,
  89     ARMv4,
  90     ARMv4t,
  91     ARMv5,
  92     ARMv5t,
  93     ARMv5te,
  94     ARMv5tej,
  95     ARMv6,
  96     ARMv6k,
  97     ARMv6kz,
  98     ARMv6m,
  99     ARMv6sm,
 100     ARMv6t2,
 101     ARMv7a,
 102     ARMv7em,
 103     ARMv7m,
 104     ARMv7r,
 105     ARMv7ve,
 106     ARMv81a,
 107     ARMv82a,
 108     ARMv83a,
 109     ARMv84a,
 110     ARMv85a,
 111     ARMv8a,
 112     ARMv8mBaseline,
 113     ARMv8mMainline,
 114     ARMv8r,
 115     ARMv81mMainline,
 116   };
 117
 118 public:
 119   /// What kind of timing do load multiple/store multiple instructions have.
 120   enum ARMLdStMultipleTiming {
 121     /// Can load/store 2 registers/cycle.
 122     DoubleIssue,
 123     /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
 124     /// is not 64-bit aligned.
 125     DoubleIssueCheckUnalignedAccess,
 126     /// Can load/store 1 register/cycle.
 127     SingleIssue,
 128     /// Can load/store 1 register/cycle, but needs an extra cycle for address
 129     /// computation and potentially also for register writeback.
 130     SingleIssuePlusExtras,
 131   };
 132
 133 protected:
 134   /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
 135   ARMProcFamilyEnum ARMProcFamily = Others;
 136
 137   /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
 138   ARMProcClassEnum ARMProcClass = None;
 139
 140   /// ARMArch - ARM architecture
 141   ARMArchEnum ARMArch = ARMv4t;
 142
 143   /// HasV4TOps, HasV5TOps, HasV5TEOps,
 144   /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
 145   /// Specify whether target support specific ARM ISA variants.
 146   bool HasV4TOps = false;
 147   bool HasV5TOps = false;
 148   bool HasV5TEOps = false;
 149   bool HasV6Ops = false;
 150   bool HasV6MOps = false;
 151   bool HasV6KOps = false;
 152   bool HasV6T2Ops = false;
 153   bool HasV7Ops = false;
 154   bool HasV8Ops = false;
 155   bool HasV8_1aOps = false;
 156   bool HasV8_2aOps = false;
 157   bool HasV8_3aOps = false;
 158   bool HasV8_4aOps = false;
 159   bool HasV8_5aOps = false;
 160   bool HasV8MBaselineOps = false;
 161   bool HasV8MMainlineOps = false;
 162   bool HasV8_1MMainlineOps = false;
 163   bool HasMVEIntegerOps = false;
 164   bool HasMVEFloatOps = false;
 165
 166   /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
 167   /// floating point ISAs are supported.
 168   bool HasVFPv2 = false;
 169   bool HasVFPv3 = false;
 170   bool HasVFPv4 = false;
 171   bool HasFPARMv8 = false;
 172   bool HasNEON = false;
 173   bool HasFPRegs = false;
 174   bool HasFPRegs16 = false;
 175   bool HasFPRegs64 = false;
 176
 177   /// Versions of the VFP flags restricted to single precision, or to
 178   /// 16 d-registers, or both.
 179   bool HasVFPv2SP = false;
 180   bool HasVFPv3SP = false;
 181   bool HasVFPv4SP = false;
 182   bool HasFPARMv8SP = false;
 183   bool HasVFPv2D16 = false;
 184   bool HasVFPv3D16 = false;
 185   bool HasVFPv4D16 = false;
 186   bool HasFPARMv8D16 = false;
 187   bool HasVFPv2D16SP = false;
 188   bool HasVFPv3D16SP = false;
 189   bool HasVFPv4D16SP = false;
 190   bool HasFPARMv8D16SP = false;
 191
 192   /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
 193   bool HasDotProd = false;
 194
 195   /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
 196   /// specified. Use the method useNEONForSinglePrecisionFP() to
 197   /// determine if NEON should actually be used.
 198   bool UseNEONForSinglePrecisionFP = false;
 199
 200   /// UseMulOps - True if non-microcoded fused integer multiply-add and
 201   /// multiply-subtract instructions should be used.
 202   bool UseMulOps = false;
 203
 204   /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
 205   /// whether the FP VML[AS] instructions are slow (if so, don't use them).
 206   bool SlowFPVMLx = false;
 207
 208   /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
 209   /// forwarding to allow mul + mla being issued back to back.
 210   bool HasVMLxForwarding = false;
 211
 212   /// SlowFPBrcc - True if floating point compare + branch is slow.
 213   bool SlowFPBrcc = false;
 214
 215   /// InThumbMode - True if compiling for Thumb, false for ARM.
 216   bool InThumbMode = false;
 217
 218   /// UseSoftFloat - True if we're using software floating point features.
 219   bool UseSoftFloat = false;
 220
 221   /// UseMISched - True if MachineScheduler should be used for this subtarget.
 222   bool UseMISched = false;
 223
 224   /// DisablePostRAScheduler - False if scheduling should happen again after
 225   /// register allocation.
 226   bool DisablePostRAScheduler = false;
 227
 228   /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
 229   bool UseAA = false;
 230
 231   /// HasThumb2 - True if Thumb2 instructions are supported.
 232   bool HasThumb2 = false;
 233
 234   /// NoARM - True if subtarget does not support ARM mode execution.
 235   bool NoARM = false;
 236
 237   /// ReserveR9 - True if R9 is not available as a general purpose register.
 238   bool ReserveR9 = false;
 239
 240   /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
 241   /// 32-bit imms (including global addresses).
 242   bool NoMovt = false;
 243
 244   /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
 245   /// must be able to synthesize call stubs for interworking between ARM and
 246   /// Thumb.
 247   bool SupportsTailCall = false;
 248
 249   /// HasFP16 - True if subtarget supports half-precision FP conversions
 250   bool HasFP16 = false;
 251
 252   /// HasFullFP16 - True if subtarget supports half-precision FP operations
 253   bool HasFullFP16 = false;
 254
 255   /// HasFP16FML - True if subtarget supports half-precision FP fml operations
 256   bool HasFP16FML = false;
 257
 258   /// HasD32 - True if subtarget has the full 32 double precision
 259   /// FP registers for VFPv3.
 260   bool HasD32 = false;
 261
 262   /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
 263   bool HasHardwareDivideInThumb = false;
 264
 265   /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
 266   bool HasHardwareDivideInARM = false;
 267
 268   /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
 269   /// instructions.
 270   bool HasDataBarrier = false;
 271
 272   /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
 273   /// instruction.
 274   bool HasFullDataBarrier = false;
 275
 276   /// HasV7Clrex - True if the subtarget supports CLREX instructions
 277   bool HasV7Clrex = false;
 278
 279   /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
 280   /// instructions
 281   bool HasAcquireRelease = false;
 282
 283   /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
 284   /// over 16-bit ones.
 285   bool Pref32BitThumb = false;
 286
 287   /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
 288   /// that partially update CPSR and add false dependency on the previous
 289   /// CPSR setting instruction.
 290   bool AvoidCPSRPartialUpdate = false;
 291
 292   /// CheapPredicableCPSRDef - If true, disable +1 predication cost
 293   /// for instructions updating CPSR. Enabled for Cortex-A57.
 294   bool CheapPredicableCPSRDef = false;
 295
 296   /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
 297   /// movs with shifter operand (i.e. asr, lsl, lsr).
 298   bool AvoidMOVsShifterOperand = false;
 299
 300   /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
 301   /// avoid issue "normal" call instructions to callees which do not return.
 302   bool HasRetAddrStack = false;
 303
 304   /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
 305   /// a branch predictor or not changes the expected cost of taking a branch
 306   /// which affects the choice of whether to use predicated instructions.
 307   bool HasBranchPredictor = true;
 308
 309   /// HasMPExtension - True if the subtarget supports Multiprocessing
 310   /// extension (ARMv7 only).
 311   bool HasMPExtension = false;
 312
 313   /// HasVirtualization - True if the subtarget supports the Virtualization
 314   /// extension.
 315   bool HasVirtualization = false;
 316
 317   /// HasFP64 - If true, the floating point unit supports double
 318   /// precision.
 319   bool HasFP64 = false;
 320
 321   /// If true, the processor supports the Performance Monitor Extensions. These
 322   /// include a generic cycle-counter as well as more fine-grained (often
 323   /// implementation-specific) events.
 324   bool HasPerfMon = false;
 325
 326   /// HasTrustZone - if true, processor supports TrustZone security extensions
 327   bool HasTrustZone = false;
 328
 329   /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
 330   bool Has8MSecExt = false;
 331
 332   /// HasSHA2 - if true, processor supports SHA1 and SHA256
 333   bool HasSHA2 = false;
 334
 335   /// HasAES - if true, processor supports AES
 336   bool HasAES = false;
 337
 338   /// HasCrypto - if true, processor supports Cryptography extensions
 339   bool HasCrypto = false;
 340
 341   /// HasCRC - if true, processor supports CRC instructions
 342   bool HasCRC = false;
 343
 344   /// HasRAS - if true, the processor supports RAS extensions
 345   bool HasRAS = false;
 346
 347   /// HasLOB - if true, the processor supports the Low Overhead Branch extension
 348   bool HasLOB = false;
 349
 350   /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
 351   /// particularly effective at zeroing a VFP register.
 352   bool HasZeroCycleZeroing = false;
 353
 354   /// HasFPAO - if true, processor  does positive address offset computation faster
 355   bool HasFPAO = false;
 356
 357   /// HasFuseAES - if true, processor executes back to back AES instruction
 358   /// pairs faster.
 359   bool HasFuseAES = false;
 360
 361   /// HasFuseLiterals - if true, processor executes back to back
 362   /// bottom and top halves of literal generation faster.
 363   bool HasFuseLiterals = false;
 364
 365   /// If true, if conversion may decide to leave some instructions unpredicated.
 366   bool IsProfitableToUnpredicate = false;
 367
 368   /// If true, VMOV will be favored over VGETLNi32.
 369   bool HasSlowVGETLNi32 = false;
 370
 371   /// If true, VMOV will be favored over VDUP.
 372   bool HasSlowVDUP32 = false;
 373
 374   /// If true, VMOVSR will be favored over VMOVDRR.
 375   bool PreferVMOVSR = false;
 376
 377   /// If true, ISHST barriers will be used for Release semantics.
 378   bool PreferISHST = false;
 379
 380   /// If true, a VLDM/VSTM starting with an odd register number is considered to
 381   /// take more microops than single VLDRS/VSTRS.
 382   bool SlowOddRegister = false;
 383
 384   /// If true, loading into a D subregister will be penalized.
 385   bool SlowLoadDSubregister = false;
 386
 387   /// If true, use a wider stride when allocating VFP registers.
 388   bool UseWideStrideVFP = false;
 389
 390   /// If true, the AGU and NEON/FPU units are multiplexed.
 391   bool HasMuxedUnits = false;
 392
 393   /// If true, VMOVS will never be widened to VMOVD.
 394   bool DontWidenVMOVS = false;
 395
 396   /// If true, splat a register between VFP and NEON instructions.
 397   bool SplatVFPToNeon = false;
 398
 399   /// If true, run the MLx expansion pass.
 400   bool ExpandMLx = false;
 401
 402   /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
 403   bool HasVMLxHazards = false;
 404
 405   // If true, read thread pointer from coprocessor register.
 406   bool ReadTPHard = false;
 407
 408   /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
 409   bool UseNEONForFPMovs = false;
 410
 411   /// If true, VLDn instructions take an extra cycle for unaligned accesses.
 412   bool CheckVLDnAlign = false;
 413
 414   /// If true, VFP instructions are not pipelined.
 415   bool NonpipelinedVFP = false;
 416
 417   /// StrictAlign - If true, the subtarget disallows unaligned memory
 418   /// accesses for some types.  For details, see
 419   /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
 420   bool StrictAlign = false;
 421
 422   /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
 423   ///  blocks to conform to ARMv8 rule.
 424   bool RestrictIT = false;
 425
 426   /// HasDSP - If true, the subtarget supports the DSP (saturating arith
 427   /// and such) instructions.
 428   bool HasDSP = false;
 429
 430   /// NaCl TRAP instruction is generated instead of the regular TRAP.
 431   bool UseNaClTrap = false;
 432
 433   /// Generate calls via indirect call instructions.
 434   bool GenLongCalls = false;
 435
 436   /// Generate code that does not contain data access to code sections.
 437   bool GenExecuteOnly = false;
 438
 439   /// Target machine allowed unsafe FP math (such as use of NEON fp)
 440   bool UnsafeFPMath = false;
 441
 442   /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
 443   bool UseSjLjEH = false;
 444
 445   /// Has speculation barrier
 446   bool HasSB = false;
 447
 448   /// Implicitly convert an instruction to a different one if its immediates
 449   /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
 450   bool NegativeImmediates = true;
 451
 452   /// stackAlignment - The minimum alignment known to hold of the stack frame on
 453   /// entry to the function and which must be maintained by every function.
 454   unsigned stackAlignment = 4;
 455
 456   /// CPUString - String name of used CPU.
 457   std::string CPUString;
 458
 459   unsigned MaxInterleaveFactor = 1;
 460
 461   /// Clearance before partial register updates (in number of instructions)
 462   unsigned PartialUpdateClearance = 0;
 463
 464   /// What kind of timing do load multiple/store multiple have (double issue,
 465   /// single issue etc).
 466   ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
 467
 468   /// The adjustment that we need to apply to get the operand latency from the
 469   /// operand cycle returned by the itinerary data for pre-ISel operands.
 470   int PreISelOperandLatencyAdjustment = 2;
 471
 472   /// What alignment is preferred for loop bodies, in log2(bytes).
 473   unsigned PrefLoopAlignment = 0;
 474
 475   /// OptMinSize - True if we're optimising for minimum code size, equal to
 476   /// the function attribute.
 477   bool OptMinSize = false;
 478
 479   /// IsLittle - The target is Little Endian
 480   bool IsLittle;
 481
 482   /// TargetTriple - What processor and OS we're targeting.
 483   Triple TargetTriple;
 484
 485   /// SchedModel - Processor specific instruction costs.
 486   MCSchedModel SchedModel;
 487
 488   /// Selected instruction itineraries (one entry per itinerary class.)
 489   InstrItineraryData InstrItins;
 490
 491   /// Options passed via command line that could influence the target
 492   const TargetOptions &Options;
 493
 494   const ARMBaseTargetMachine &TM;
 495
 496 public:
 497   /// This constructor initializes the data members to match that
 498   /// of the specified triple.
 499   ///
 500   ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
 501                const ARMBaseTargetMachine &TM, bool IsLittle,
 502                bool MinSize = false);
 503
 504   /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
 505   /// that still makes it profitable to inline the call.
 506   unsigned getMaxInlineSizeThreshold() const {
 507     return 64;
 508   }
 509
 510   /// ParseSubtargetFeatures - Parses features string setting specified
 511   /// subtarget options.  Definition of function is auto generated by tblgen.
 512   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 513
 514   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
 515   /// so that we can use initializer lists for subtarget initialization.
 516   ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 517
 518   const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
 519     return &TSInfo;
 520   }
 521
 522   const ARMBaseInstrInfo *getInstrInfo() const override {
 523     return InstrInfo.get();
 524   }
 525
 526   const ARMTargetLowering *getTargetLowering() const override {
 527     return &TLInfo;
 528   }
 529
 530   const ARMFrameLowering *getFrameLowering() const override {
 531     return FrameLowering.get();
 532   }
 533
 534   const ARMBaseRegisterInfo *getRegisterInfo() const override {
 535     return &InstrInfo->getRegisterInfo();
 536   }
 537
 538   const CallLowering *getCallLowering() const override;
 539   const InstructionSelector *getInstructionSelector() const override;
 540   const LegalizerInfo *getLegalizerInfo() const override;
 541   const RegisterBankInfo *getRegBankInfo() const override;
 542
 543 private:
 544   ARMSelectionDAGInfo TSInfo;
 545   // Either Thumb1FrameLowering or ARMFrameLowering.
 546   std::unique_ptr<ARMFrameLowering> FrameLowering;
 547   // Either Thumb1InstrInfo or Thumb2InstrInfo.
 548   std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
 549   ARMTargetLowering   TLInfo;
 550
 551   /// GlobalISel related APIs.
 552   std::unique_ptr<CallLowering> CallLoweringInfo;
 553   std::unique_ptr<InstructionSelector> InstSelector;
 554   std::unique_ptr<LegalizerInfo> Legalizer;
 555   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 556
 557   void initializeEnvironment();
 558   void initSubtargetFeatures(StringRef CPU, StringRef FS);
 559   ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
 560
 561 public:
 562   void computeIssueWidth();
 563
 564   bool hasV4TOps()  const { return HasV4TOps;  }
 565   bool hasV5TOps()  const { return HasV5TOps;  }
 566   bool hasV5TEOps() const { return HasV5TEOps; }
 567   bool hasV6Ops()   const { return HasV6Ops;   }
 568   bool hasV6MOps()  const { return HasV6MOps;  }
 569   bool hasV6KOps()  const { return HasV6KOps; }
 570   bool hasV6T2Ops() const { return HasV6T2Ops; }
 571   bool hasV7Ops()   const { return HasV7Ops;  }
 572   bool hasV8Ops()   const { return HasV8Ops;  }
 573   bool hasV8_1aOps() const { return HasV8_1aOps; }
 574   bool hasV8_2aOps() const { return HasV8_2aOps; }
 575   bool hasV8_3aOps() const { return HasV8_3aOps; }
 576   bool hasV8_4aOps() const { return HasV8_4aOps; }
 577   bool hasV8_5aOps() const { return HasV8_5aOps; }
 578   bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
 579   bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
 580   bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; }
 581   bool hasMVEIntegerOps() const { return HasMVEIntegerOps; }
 582   bool hasMVEFloatOps() const { return HasMVEFloatOps; }
 583   bool hasFPRegs() const { return HasFPRegs; }
 584   bool hasFPRegs16() const { return HasFPRegs16; }
 585   bool hasFPRegs64() const { return HasFPRegs64; }
 586
 587   /// @{
 588   /// These functions are obsolete, please consider adding subtarget features
 589   /// or properties instead of calling them.
 590   bool isCortexA5() const { return ARMProcFamily == CortexA5; }
 591   bool isCortexA7() const { return ARMProcFamily == CortexA7; }
 592   bool isCortexA8() const { return ARMProcFamily == CortexA8; }
 593   bool isCortexA9() const { return ARMProcFamily == CortexA9; }
 594   bool isCortexA15() const { return ARMProcFamily == CortexA15; }
 595   bool isSwift()    const { return ARMProcFamily == Swift; }
 596   bool isCortexM3() const { return ARMProcFamily == CortexM3; }
 597   bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
 598   bool isCortexR5() const { return ARMProcFamily == CortexR5; }
 599   bool isKrait() const { return ARMProcFamily == Krait; }
 600   /// @}
 601
 602   bool hasARMOps() const { return !NoARM; }
 603
 604   bool hasVFP2Base() const { return HasVFPv2D16SP; }
 605   bool hasVFP3Base() const { return HasVFPv3D16SP; }
 606   bool hasVFP4Base() const { return HasVFPv4D16SP; }
 607   bool hasFPARMv8Base() const { return HasFPARMv8D16SP; }
 608   bool hasNEON() const { return HasNEON;  }
 609   bool hasSHA2() const { return HasSHA2; }
 610   bool hasAES() const { return HasAES; }
 611   bool hasCrypto() const { return HasCrypto; }
 612   bool hasDotProd() const { return HasDotProd; }
 613   bool hasCRC() const { return HasCRC; }
 614   bool hasRAS() const { return HasRAS; }
 615   bool hasLOB() const { return HasLOB; }
 616   bool hasVirtualization() const { return HasVirtualization; }
 617
 618   bool useNEONForSinglePrecisionFP() const {
 619     return hasNEON() && UseNEONForSinglePrecisionFP;
 620   }
 621
 622   bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
 623   bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
 624   bool hasDataBarrier() const { return HasDataBarrier; }
 625   bool hasFullDataBarrier() const { return HasFullDataBarrier; }
 626   bool hasV7Clrex() const { return HasV7Clrex; }
 627   bool hasAcquireRelease() const { return HasAcquireRelease; }
 628
 629   bool hasAnyDataBarrier() const {
 630     return HasDataBarrier || (hasV6Ops() && !isThumb());
 631   }
 632
 633   bool useMulOps() const { return UseMulOps; }
 634   bool useFPVMLx() const { return !SlowFPVMLx; }
 635   bool hasVMLxForwarding() const { return HasVMLxForwarding; }
 636   bool isFPBrccSlow() const { return SlowFPBrcc; }
 637   bool hasFP64() const { return HasFP64; }
 638   bool hasPerfMon() const { return HasPerfMon; }
 639   bool hasTrustZone() const { return HasTrustZone; }
 640   bool has8MSecExt() const { return Has8MSecExt; }
 641   bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
 642   bool hasFPAO() const { return HasFPAO; }
 643   bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }
 644   bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
 645   bool hasSlowVDUP32() const { return HasSlowVDUP32; }
 646   bool preferVMOVSR() const { return PreferVMOVSR; }
 647   bool preferISHSTBarriers() const { return PreferISHST; }
 648   bool expandMLx() const { return ExpandMLx; }
 649   bool hasVMLxHazards() const { return HasVMLxHazards; }
 650   bool hasSlowOddRegister() const { return SlowOddRegister; }
 651   bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
 652   bool useWideStrideVFP() const { return UseWideStrideVFP; }
 653   bool hasMuxedUnits() const { return HasMuxedUnits; }
 654   bool dontWidenVMOVS() const { return DontWidenVMOVS; }
 655   bool useSplatVFPToNeon() const { return SplatVFPToNeon; }
 656   bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
 657   bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
 658   bool nonpipelinedVFP() const { return NonpipelinedVFP; }
 659   bool prefers32BitThumb() const { return Pref32BitThumb; }
 660   bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
 661   bool cheapPredicableCPSRDef() const { return CheapPredicableCPSRDef; }
 662   bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
 663   bool hasRetAddrStack() const { return HasRetAddrStack; }
 664   bool hasBranchPredictor() const { return HasBranchPredictor; }
 665   bool hasMPExtension() const { return HasMPExtension; }
 666   bool hasDSP() const { return HasDSP; }
 667   bool useNaClTrap() const { return UseNaClTrap; }
 668   bool useSjLjEH() const { return UseSjLjEH; }
 669   bool hasSB() const { return HasSB; }
 670   bool genLongCalls() const { return GenLongCalls; }
 671   bool genExecuteOnly() const { return GenExecuteOnly; }
 672
 673   bool hasFP16() const { return HasFP16; }
 674   bool hasD32() const { return HasD32; }
 675   bool hasFullFP16() const { return HasFullFP16; }
 676   bool hasFP16FML() const { return HasFP16FML; }
 677
 678   bool hasFuseAES() const { return HasFuseAES; }
 679   bool hasFuseLiterals() const { return HasFuseLiterals; }
 680   /// Return true if the CPU supports any kind of instruction fusion.
 681   bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
 682
 683   const Triple &getTargetTriple() const { return TargetTriple; }
 684
 685   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
 686   bool isTargetIOS() const { return TargetTriple.isiOS(); }
 687   bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
 688   bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
 689   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 690   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
 691   bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
 692   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
 693
 694   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
 695   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 696   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 697
 698   // ARM EABI is the bare-metal EABI described in ARM ABI documents and
 699   // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
 700   // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
 701   // even for GNUEABI, so we can make a distinction here and still conform to
 702   // the EABI on GNU (and Android) mode. This requires change in Clang, too.
 703   // FIXME: The Darwin exception is temporary, while we move users to
 704   // "*-*-*-macho" triples as quickly as possible.
 705   bool isTargetAEABI() const {
 706     return (TargetTriple.getEnvironment() == Triple::EABI ||
 707             TargetTriple.getEnvironment() == Triple::EABIHF) &&
 708            !isTargetDarwin() && !isTargetWindows();
 709   }
 710   bool isTargetGNUAEABI() const {
 711     return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
 712             TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
 713            !isTargetDarwin() && !isTargetWindows();
 714   }
 715   bool isTargetMuslAEABI() const {
 716     return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
 717             TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
 718            !isTargetDarwin() && !isTargetWindows();
 719   }
 720
 721   // ARM Targets that support EHABI exception handling standard
 722   // Darwin uses SjLj. Other targets might need more checks.
 723   bool isTargetEHABICompatible() const {
 724     return (TargetTriple.getEnvironment() == Triple::EABI ||
 725             TargetTriple.getEnvironment() == Triple::GNUEABI ||
 726             TargetTriple.getEnvironment() == Triple::MuslEABI ||
 727             TargetTriple.getEnvironment() == Triple::EABIHF ||
 728             TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
 729             TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
 730             isTargetAndroid()) &&
 731            !isTargetDarwin() && !isTargetWindows();
 732   }
 733
 734   bool isTargetHardFloat() const;
 735
 736   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
 737
 738   bool isXRaySupported() const override;
 739
 740   bool isAPCS_ABI() const;
 741   bool isAAPCS_ABI() const;
 742   bool isAAPCS16_ABI() const;
 743
 744   bool isROPI() const;
 745   bool isRWPI() const;
 746
 747   bool useMachineScheduler() const { return UseMISched; }
 748   bool disablePostRAScheduler() const { return DisablePostRAScheduler; }
 749   bool useSoftFloat() const { return UseSoftFloat; }
 750   bool isThumb() const { return InThumbMode; }
 751   bool hasMinSize() const { return OptMinSize; }
 752   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
 753   bool isThumb2() const { return InThumbMode && HasThumb2; }
 754   bool hasThumb2() const { return HasThumb2; }
 755   bool isMClass() const { return ARMProcClass == MClass; }
 756   bool isRClass() const { return ARMProcClass == RClass; }
 757   bool isAClass() const { return ARMProcClass == AClass; }
 758   bool isReadTPHard() const { return ReadTPHard; }
 759
 760   bool isR9Reserved() const {
 761     return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
 762   }
 763
 764   bool useR7AsFramePointer() const {
 765     return isTargetDarwin() || (!isTargetWindows() && isThumb());
 766   }
 767
 768   /// Returns true if the frame setup is split into two separate pushes (first
 769   /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
 770   /// to lr. This is always required on Thumb1-only targets, as the push and
 771   /// pop instructions can't access the high registers.
 772   bool splitFramePushPop(const MachineFunction &MF) const {
 773     return (useR7AsFramePointer() &&
 774             MF.getTarget().Options.DisableFramePointerElim(MF)) ||
 775            isThumb1Only();
 776   }
 777
 778   bool useStride4VFPs() const;
 779
 780   bool useMovt() const;
 781
 782   bool supportsTailCall() const { return SupportsTailCall; }
 783
 784   bool allowsUnalignedMem() const { return !StrictAlign; }
 785
 786   bool restrictIT() const { return RestrictIT; }
 787
 788   const std::string & getCPUString() const { return CPUString; }
 789
 790   bool isLittle() const { return IsLittle; }
 791
 792   unsigned getMispredictionPenalty() const;
 793
 794   /// Returns true if machine scheduler should be enabled.
 795   bool enableMachineScheduler() const override;
 796
 797   /// True for some subtargets at > -O0.
 798   bool enablePostRAScheduler() const override;
 799
 800   /// Enable use of alias analysis during code generation (during MI
 801   /// scheduling, DAGCombine, etc.).
 802   bool useAA() const override { return UseAA; }
 803
 804   // enableAtomicExpand- True if we need to expand our atomics.
 805   bool enableAtomicExpand() const override;
 806
 807   /// getInstrItins - Return the instruction itineraries based on subtarget
 808   /// selection.
 809   const InstrItineraryData *getInstrItineraryData() const override {
 810     return &InstrItins;
 811   }
 812
 813   /// getStackAlignment - Returns the minimum alignment known to hold of the
 814   /// stack frame on entry to the function and which must be maintained by every
 815   /// function for this subtarget.
 816   unsigned getStackAlignment() const { return stackAlignment; }
 817
 818   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
 819
 820   unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
 821
 822   ARMLdStMultipleTiming getLdStMultipleTiming() const {
 823     return LdStMultipleTiming;
 824   }
 825
 826   int getPreISelOperandLatencyAdjustment() const {
 827     return PreISelOperandLatencyAdjustment;
 828   }
 829
 830   /// True if the GV will be accessed via an indirect symbol.
 831   bool isGVIndirectSymbol(const GlobalValue *GV) const;
 832
 833   /// Returns the constant pool modifier needed to access the GV.
 834   bool isGVInGOT(const GlobalValue *GV) const;
 835
 836   /// True if fast-isel is used.
 837   bool useFastISel() const;
 838
 839   /// Returns the correct return opcode for the current feature set.
 840   /// Use BX if available to allow mixing thumb/arm code, but fall back
 841   /// to plain mov pc,lr on ARMv4.
 842   unsigned getReturnOpcode() const {
 843     if (isThumb())
 844       return ARM::tBX_RET;
 845     if (hasV4TOps())
 846       return ARM::BX_RET;
 847     return ARM::MOVPCLR;
 848   }
 849
 850   /// Allow movt+movw for PIC global address calculation.
 851   /// ELF does not have GOT relocations for movt+movw.
 852   /// ROPI does not use GOT.
 853   bool allowPositionIndependentMovt() const {
 854     return isROPI() || !isTargetELF();
 855   }
 856
 857   unsigned getPrefLoopAlignment() const {
 858     return PrefLoopAlignment;
 859   }
 860
 861   bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
 862                                    unsigned PhysReg) const override;
 863   unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
 864 };
 865
 866 } // end namespace llvm
 867
 868 #endif  // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H