| blob | 20c5efcf7f36f33a93516f14288cebfbc59fe938 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
4 ; Odd+Even divisors
5 define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
6 ; CHECK-LABEL: test_srem_odd_even:
7 ; CHECK: // %bb.0:
8 ; CHECK-NEXT: adrp x8, .LCPI0_0
9 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
10 ; CHECK-NEXT: adrp x8, .LCPI0_1
11 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_1]
12 ; CHECK-NEXT: adrp x8, .LCPI0_2
13 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
14 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
15 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
16 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI0_2]
17 ; CHECK-NEXT: adrp x8, .LCPI0_3
18 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
19 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_3]
20 ; CHECK-NEXT: neg v3.4s, v3.4s
21 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
22 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
23 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
24 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
25 ; CHECK-NEXT: movi v1.4s, #1
26 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
27 ; CHECK-NEXT: ret
28 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100>
29 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
30 %ret = zext <4 x i1> %cmp to <4 x i32>
31 ret <4 x i32> %ret
32 }
34 ;==============================================================================;
36 ; One all-ones divisor in odd divisor
37 define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
38 ; CHECK-LABEL: test_srem_odd_allones_eq:
39 ; CHECK: // %bb.0:
40 ; CHECK-NEXT: adrp x8, .LCPI1_0
41 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
42 ; CHECK-NEXT: adrp x8, .LCPI1_1
43 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI1_1]
44 ; CHECK-NEXT: adrp x8, .LCPI1_2
45 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI1_2]
46 ; CHECK-NEXT: adrp x8, .LCPI1_3
47 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
48 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
49 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
50 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI1_3]
51 ; CHECK-NEXT: adrp x8, .LCPI1_4
52 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
53 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI1_4]
54 ; CHECK-NEXT: neg v3.4s, v3.4s
55 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
56 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
57 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
58 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
59 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
60 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
61 ; CHECK-NEXT: movi v1.4s, #1
62 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
63 ; CHECK-NEXT: ret
64 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
65 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
66 %ret = zext <4 x i1> %cmp to <4 x i32>
67 ret <4 x i32> %ret
68 }
69 define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
70 ; CHECK-LABEL: test_srem_odd_allones_ne:
71 ; CHECK: // %bb.0:
72 ; CHECK-NEXT: adrp x8, .LCPI2_0
73 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
74 ; CHECK-NEXT: adrp x8, .LCPI2_1
75 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI2_1]
76 ; CHECK-NEXT: adrp x8, .LCPI2_2
77 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI2_2]
78 ; CHECK-NEXT: adrp x8, .LCPI2_3
79 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
80 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
81 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
82 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI2_3]
83 ; CHECK-NEXT: adrp x8, .LCPI2_4
84 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
85 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI2_4]
86 ; CHECK-NEXT: neg v3.4s, v3.4s
87 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
88 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
89 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
90 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
91 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
92 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
93 ; CHECK-NEXT: mvn v0.16b, v0.16b
94 ; CHECK-NEXT: movi v1.4s, #1
95 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
96 ; CHECK-NEXT: ret
97 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
98 %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
99 %ret = zext <4 x i1> %cmp to <4 x i32>
100 ret <4 x i32> %ret
101 }
103 ; One all-ones divisor in even divisor
104 define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
105 ; CHECK-LABEL: test_srem_even_allones_eq:
106 ; CHECK: // %bb.0:
107 ; CHECK-NEXT: adrp x8, .LCPI3_0
108 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
109 ; CHECK-NEXT: adrp x8, .LCPI3_1
110 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
111 ; CHECK-NEXT: adrp x8, .LCPI3_2
112 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI3_2]
113 ; CHECK-NEXT: adrp x8, .LCPI3_3
114 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
115 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
116 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
117 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI3_3]
118 ; CHECK-NEXT: adrp x8, .LCPI3_4
119 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
120 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_4]
121 ; CHECK-NEXT: neg v3.4s, v3.4s
122 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
123 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
124 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
125 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
126 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
127 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
128 ; CHECK-NEXT: movi v1.4s, #1
129 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
130 ; CHECK-NEXT: ret
131 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
132 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
133 %ret = zext <4 x i1> %cmp to <4 x i32>
134 ret <4 x i32> %ret
135 }
136 define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
137 ; CHECK-LABEL: test_srem_even_allones_ne:
138 ; CHECK: // %bb.0:
139 ; CHECK-NEXT: adrp x8, .LCPI4_0
140 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]
141 ; CHECK-NEXT: adrp x8, .LCPI4_1
142 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_1]
143 ; CHECK-NEXT: adrp x8, .LCPI4_2
144 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI4_2]
145 ; CHECK-NEXT: adrp x8, .LCPI4_3
146 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
147 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
148 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
149 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI4_3]
150 ; CHECK-NEXT: adrp x8, .LCPI4_4
151 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
152 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_4]
153 ; CHECK-NEXT: neg v3.4s, v3.4s
154 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
155 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
156 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
157 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
158 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
159 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
160 ; CHECK-NEXT: mvn v0.16b, v0.16b
161 ; CHECK-NEXT: movi v1.4s, #1
162 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
163 ; CHECK-NEXT: ret
164 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
165 %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
166 %ret = zext <4 x i1> %cmp to <4 x i32>
167 ret <4 x i32> %ret
168 }
170 ; One all-ones divisor in odd+even divisor
171 define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind {
172 ; CHECK-LABEL: test_srem_odd_even_allones_eq:
173 ; CHECK: // %bb.0:
174 ; CHECK-NEXT: adrp x8, .LCPI5_0
175 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]
176 ; CHECK-NEXT: adrp x8, .LCPI5_1
177 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_1]
178 ; CHECK-NEXT: adrp x8, .LCPI5_2
179 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI5_2]
180 ; CHECK-NEXT: adrp x8, .LCPI5_3
181 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
182 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
183 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
184 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI5_3]
185 ; CHECK-NEXT: adrp x8, .LCPI5_4
186 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
187 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_4]
188 ; CHECK-NEXT: neg v3.4s, v3.4s
189 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
190 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
191 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
192 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
193 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
194 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
195 ; CHECK-NEXT: movi v1.4s, #1
196 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
197 ; CHECK-NEXT: ret
198 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
199 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
200 %ret = zext <4 x i1> %cmp to <4 x i32>
201 ret <4 x i32> %ret
202 }
203 define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
204 ; CHECK-LABEL: test_srem_odd_even_allones_ne:
205 ; CHECK: // %bb.0:
206 ; CHECK-NEXT: adrp x8, .LCPI6_0
207 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]
208 ; CHECK-NEXT: adrp x8, .LCPI6_1
209 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI6_1]
210 ; CHECK-NEXT: adrp x8, .LCPI6_2
211 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI6_2]
212 ; CHECK-NEXT: adrp x8, .LCPI6_3
213 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
214 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
215 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
216 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI6_3]
217 ; CHECK-NEXT: adrp x8, .LCPI6_4
218 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
219 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI6_4]
220 ; CHECK-NEXT: neg v3.4s, v3.4s
221 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
222 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
223 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
224 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
225 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
226 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
227 ; CHECK-NEXT: mvn v0.16b, v0.16b
228 ; CHECK-NEXT: movi v1.4s, #1
229 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
230 ; CHECK-NEXT: ret
231 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
232 %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
233 %ret = zext <4 x i1> %cmp to <4 x i32>
234 ret <4 x i32> %ret
235 }
237 ;------------------------------------------------------------------------------;
239 ; One power-of-two divisor in odd divisor
240 define <4 x i32> @test_srem_odd_poweroftwo(<4 x i32> %X) nounwind {
241 ; CHECK-LABEL: test_srem_odd_poweroftwo:
242 ; CHECK: // %bb.0:
243 ; CHECK-NEXT: adrp x8, .LCPI7_0
244 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_0]
245 ; CHECK-NEXT: adrp x8, .LCPI7_1
246 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_1]
247 ; CHECK-NEXT: adrp x8, .LCPI7_2
248 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
249 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
250 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
251 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI7_2]
252 ; CHECK-NEXT: adrp x8, .LCPI7_3
253 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
254 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_3]
255 ; CHECK-NEXT: neg v3.4s, v3.4s
256 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
257 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
258 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
259 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
260 ; CHECK-NEXT: movi v1.4s, #1
261 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
262 ; CHECK-NEXT: ret
263 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5>
264 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
265 %ret = zext <4 x i1> %cmp to <4 x i32>
266 ret <4 x i32> %ret
267 }
269 ; One power-of-two divisor in even divisor
270 define <4 x i32> @test_srem_even_poweroftwo(<4 x i32> %X) nounwind {
271 ; CHECK-LABEL: test_srem_even_poweroftwo:
272 ; CHECK: // %bb.0:
273 ; CHECK-NEXT: adrp x8, .LCPI8_0
274 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0]
275 ; CHECK-NEXT: adrp x8, .LCPI8_1
276 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_1]
277 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
278 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
279 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
280 ; CHECK-NEXT: add v1.4s, v1.4s, v0.4s
281 ; CHECK-NEXT: sshr v3.4s, v1.4s, #3
282 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
283 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
284 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
285 ; CHECK-NEXT: movi v1.4s, #1
286 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
287 ; CHECK-NEXT: ret
288 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14>
289 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
290 %ret = zext <4 x i1> %cmp to <4 x i32>
291 ret <4 x i32> %ret
292 }
294 ; One power-of-two divisor in odd+even divisor
295 define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
296 ; CHECK-LABEL: test_srem_odd_even_poweroftwo:
297 ; CHECK: // %bb.0:
298 ; CHECK-NEXT: adrp x8, .LCPI9_0
299 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0]
300 ; CHECK-NEXT: adrp x8, .LCPI9_1
301 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI9_1]
302 ; CHECK-NEXT: adrp x8, .LCPI9_2
303 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
304 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
305 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
306 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI9_2]
307 ; CHECK-NEXT: adrp x8, .LCPI9_3
308 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
309 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI9_3]
310 ; CHECK-NEXT: neg v3.4s, v3.4s
311 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
312 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
313 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
314 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
315 ; CHECK-NEXT: movi v1.4s, #1
316 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
317 ; CHECK-NEXT: ret
318 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100>
319 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
320 %ret = zext <4 x i1> %cmp to <4 x i32>
321 ret <4 x i32> %ret
322 }
324 ;------------------------------------------------------------------------------;
326 ; One one divisor in odd divisor
327 define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
328 ; CHECK-LABEL: test_srem_odd_one:
329 ; CHECK: // %bb.0:
330 ; CHECK-NEXT: adrp x8, .LCPI10_0
331 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI10_0]
332 ; CHECK-NEXT: adrp x8, .LCPI10_1
333 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI10_1]
334 ; CHECK-NEXT: adrp x8, .LCPI10_2
335 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI10_2]
336 ; CHECK-NEXT: adrp x8, .LCPI10_3
337 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
338 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
339 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
340 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI10_3]
341 ; CHECK-NEXT: adrp x8, .LCPI10_4
342 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
343 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI10_4]
344 ; CHECK-NEXT: neg v3.4s, v3.4s
345 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
346 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
347 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
348 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
349 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
350 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
351 ; CHECK-NEXT: movi v1.4s, #1
352 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
353 ; CHECK-NEXT: ret
354 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 1, i32 5>
355 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
356 %ret = zext <4 x i1> %cmp to <4 x i32>
357 ret <4 x i32> %ret
358 }
360 ; One one divisor in even divisor
361 define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
362 ; CHECK-LABEL: test_srem_even_one:
363 ; CHECK: // %bb.0:
364 ; CHECK-NEXT: adrp x8, .LCPI11_0
365 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI11_0]
366 ; CHECK-NEXT: adrp x8, .LCPI11_1
367 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI11_1]
368 ; CHECK-NEXT: adrp x8, .LCPI11_2
369 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI11_2]
370 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
371 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
372 ; CHECK-NEXT: adrp x8, .LCPI11_3
373 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
374 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI11_3]
375 ; CHECK-NEXT: neg v2.4s, v2.4s
376 ; CHECK-NEXT: add v1.4s, v1.4s, v0.4s
377 ; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s
378 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
379 ; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
380 ; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
381 ; CHECK-NEXT: mls v0.4s, v1.4s, v4.4s
382 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
383 ; CHECK-NEXT: movi v1.4s, #1
384 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
385 ; CHECK-NEXT: ret
386 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
387 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
388 %ret = zext <4 x i1> %cmp to <4 x i32>
389 ret <4 x i32> %ret
390 }
392 ; One one divisor in odd+even divisor
393 define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {
394 ; CHECK-LABEL: test_srem_odd_even_one:
395 ; CHECK: // %bb.0:
396 ; CHECK-NEXT: adrp x8, .LCPI12_0
397 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0]
398 ; CHECK-NEXT: adrp x8, .LCPI12_1
399 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI12_1]
400 ; CHECK-NEXT: adrp x8, .LCPI12_2
401 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI12_2]
402 ; CHECK-NEXT: adrp x8, .LCPI12_3
403 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
404 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
405 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
406 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI12_3]
407 ; CHECK-NEXT: adrp x8, .LCPI12_4
408 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
409 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI12_4]
410 ; CHECK-NEXT: neg v3.4s, v3.4s
411 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
412 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
413 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
414 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
415 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
416 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
417 ; CHECK-NEXT: movi v1.4s, #1
418 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
419 ; CHECK-NEXT: ret
420 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100>
421 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
422 %ret = zext <4 x i1> %cmp to <4 x i32>
423 ret <4 x i32> %ret
424 }
426 ;------------------------------------------------------------------------------;
428 ; One INT_MIN divisor in odd divisor
429 define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind {
430 ; CHECK-LABEL: test_srem_odd_INT_MIN:
431 ; CHECK: // %bb.0:
432 ; CHECK-NEXT: adrp x8, .LCPI13_0
433 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_0]
434 ; CHECK-NEXT: adrp x8, .LCPI13_1
435 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_1]
436 ; CHECK-NEXT: adrp x8, .LCPI13_2
437 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
438 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
439 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
440 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI13_2]
441 ; CHECK-NEXT: adrp x8, .LCPI13_3
442 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
443 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_3]
444 ; CHECK-NEXT: neg v3.4s, v3.4s
445 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
446 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
447 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
448 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
449 ; CHECK-NEXT: movi v1.4s, #1
450 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
451 ; CHECK-NEXT: ret
452 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5>
453 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
454 %ret = zext <4 x i1> %cmp to <4 x i32>
455 ret <4 x i32> %ret
456 }
458 ; One INT_MIN divisor in even divisor
459 define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
460 ; CHECK-LABEL: test_srem_even_INT_MIN:
461 ; CHECK: // %bb.0:
462 ; CHECK-NEXT: adrp x8, .LCPI14_0
463 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
464 ; CHECK-NEXT: adrp x8, .LCPI14_1
465 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_1]
466 ; CHECK-NEXT: adrp x8, .LCPI14_2
467 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
468 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
469 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
470 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI14_2]
471 ; CHECK-NEXT: adrp x8, .LCPI14_3
472 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
473 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_3]
474 ; CHECK-NEXT: neg v3.4s, v3.4s
475 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
476 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
477 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
478 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
479 ; CHECK-NEXT: movi v1.4s, #1
480 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
481 ; CHECK-NEXT: ret
482 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14>
483 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
484 %ret = zext <4 x i1> %cmp to <4 x i32>
485 ret <4 x i32> %ret
486 }
488 ; One INT_MIN divisor in odd+even divisor
489 define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
490 ; CHECK-LABEL: test_srem_odd_even_INT_MIN:
491 ; CHECK: // %bb.0:
492 ; CHECK-NEXT: adrp x8, .LCPI15_0
493 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
494 ; CHECK-NEXT: adrp x8, .LCPI15_1
495 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_1]
496 ; CHECK-NEXT: adrp x8, .LCPI15_2
497 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
498 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
499 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
500 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI15_2]
501 ; CHECK-NEXT: adrp x8, .LCPI15_3
502 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
503 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_3]
504 ; CHECK-NEXT: neg v3.4s, v3.4s
505 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
506 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
507 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
508 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
509 ; CHECK-NEXT: movi v1.4s, #1
510 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
511 ; CHECK-NEXT: ret
512 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100>
513 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
514 %ret = zext <4 x i1> %cmp to <4 x i32>
515 ret <4 x i32> %ret
516 }
518 ;==============================================================================;
520 ; One all-ones divisor and power-of-two divisor divisor in odd divisor
521 define <4 x i32> @test_srem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
522 ; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo:
523 ; CHECK: // %bb.0:
524 ; CHECK-NEXT: adrp x8, .LCPI16_0
525 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
526 ; CHECK-NEXT: adrp x8, .LCPI16_1
527 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI16_1]
528 ; CHECK-NEXT: adrp x8, .LCPI16_2
529 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI16_2]
530 ; CHECK-NEXT: adrp x8, .LCPI16_3
531 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
532 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
533 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
534 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI16_3]
535 ; CHECK-NEXT: adrp x8, .LCPI16_4
536 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
537 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI16_4]
538 ; CHECK-NEXT: neg v3.4s, v3.4s
539 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
540 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
541 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
542 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
543 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
544 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
545 ; CHECK-NEXT: movi v1.4s, #1
546 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
547 ; CHECK-NEXT: ret
548 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5>
549 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
550 %ret = zext <4 x i1> %cmp to <4 x i32>
551 ret <4 x i32> %ret
552 }
554 ; One all-ones divisor and power-of-two divisor divisor in even divisor
555 define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
556 ; CHECK-LABEL: test_srem_even_allones_and_poweroftwo:
557 ; CHECK: // %bb.0:
558 ; CHECK-NEXT: adrp x8, .LCPI17_0
559 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
560 ; CHECK-NEXT: adrp x8, .LCPI17_1
561 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI17_1]
562 ; CHECK-NEXT: adrp x8, .LCPI17_2
563 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI17_2]
564 ; CHECK-NEXT: adrp x8, .LCPI17_3
565 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
566 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
567 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
568 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI17_3]
569 ; CHECK-NEXT: adrp x8, .LCPI17_4
570 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
571 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI17_4]
572 ; CHECK-NEXT: neg v3.4s, v3.4s
573 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
574 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
575 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
576 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
577 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
578 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
579 ; CHECK-NEXT: movi v1.4s, #1
580 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
581 ; CHECK-NEXT: ret
582 %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14>
583 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
584 %ret = zext <4 x i1> %cmp to <4 x i32>
585 ret <4 x i32> %ret
586 }
588 ; One all-ones divisor and power-of-two divisor divisor in odd+even divisor
589 define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
590 ; CHECK-LABEL: test_srem_odd_even_allones_and_poweroftwo:
591 ; CHECK: // %bb.0:
592 ; CHECK-NEXT: adrp x8, .LCPI18_0
593 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI18_0]
594 ; CHECK-NEXT: adrp x8, .LCPI18_1
595 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI18_1]
596 ; CHECK-NEXT: adrp x8, .LCPI18_2
597 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI18_2]
598 ; CHECK-NEXT: adrp x8, .LCPI18_3
599 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
600 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
601 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
602 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI18_3]
603 ; CHECK-NEXT: adrp x8, .LCPI18_4
604 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
605 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI18_4]
606 ; CHECK-NEXT: neg v3.4s, v3.4s
607 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
608 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
609 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
610 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
611 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
612 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
613 ; CHECK-NEXT: movi v1.4s, #1
614 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
615 ; CHECK-NEXT: ret
616 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100>
617 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
618 %ret = zext <4 x i1> %cmp to <4 x i32>
619 ret <4 x i32> %ret
620 }
622 ;------------------------------------------------------------------------------;
624 ; One all-ones divisor and one one divisor in odd divisor
625 define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
626 ; CHECK-LABEL: test_srem_odd_allones_and_one:
627 ; CHECK: // %bb.0:
628 ; CHECK-NEXT: adrp x8, .LCPI19_0
629 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]
630 ; CHECK-NEXT: adrp x8, .LCPI19_1
631 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI19_1]
632 ; CHECK-NEXT: adrp x8, .LCPI19_2
633 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI19_2]
634 ; CHECK-NEXT: adrp x8, .LCPI19_3
635 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
636 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
637 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
638 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI19_3]
639 ; CHECK-NEXT: adrp x8, .LCPI19_4
640 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
641 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI19_4]
642 ; CHECK-NEXT: neg v3.4s, v3.4s
643 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
644 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
645 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
646 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
647 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
648 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
649 ; CHECK-NEXT: movi v1.4s, #1
650 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
651 ; CHECK-NEXT: ret
652 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 5>
653 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
654 %ret = zext <4 x i1> %cmp to <4 x i32>
655 ret <4 x i32> %ret
656 }
658 ; One all-ones divisor and one one divisor in even divisor
659 define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
660 ; CHECK-LABEL: test_srem_even_allones_and_one:
661 ; CHECK: // %bb.0:
662 ; CHECK-NEXT: adrp x8, .LCPI20_0
663 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_0]
664 ; CHECK-NEXT: adrp x8, .LCPI20_1
665 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI20_1]
666 ; CHECK-NEXT: adrp x8, .LCPI20_2
667 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI20_2]
668 ; CHECK-NEXT: adrp x8, .LCPI20_3
669 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
670 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
671 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
672 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI20_3]
673 ; CHECK-NEXT: adrp x8, .LCPI20_4
674 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
675 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI20_4]
676 ; CHECK-NEXT: neg v3.4s, v3.4s
677 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
678 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
679 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
680 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
681 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
682 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
683 ; CHECK-NEXT: movi v1.4s, #1
684 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
685 ; CHECK-NEXT: ret
686 %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>
687 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
688 %ret = zext <4 x i1> %cmp to <4 x i32>
689 ret <4 x i32> %ret
690 }
692 ; One all-ones divisor and one one divisor in odd+even divisor
693 define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
694 ; CHECK-LABEL: test_srem_odd_even_allones_and_one:
695 ; CHECK: // %bb.0:
696 ; CHECK-NEXT: adrp x8, .LCPI21_0
697 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI21_0]
698 ; CHECK-NEXT: adrp x8, .LCPI21_1
699 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI21_1]
700 ; CHECK-NEXT: adrp x8, .LCPI21_2
701 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI21_2]
702 ; CHECK-NEXT: adrp x8, .LCPI21_3
703 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
704 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
705 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
706 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI21_3]
707 ; CHECK-NEXT: adrp x8, .LCPI21_4
708 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
709 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI21_4]
710 ; CHECK-NEXT: neg v3.4s, v3.4s
711 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
712 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
713 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
714 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
715 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
716 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
717 ; CHECK-NEXT: movi v1.4s, #1
718 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
719 ; CHECK-NEXT: ret
720 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100>
721 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
722 %ret = zext <4 x i1> %cmp to <4 x i32>
723 ret <4 x i32> %ret
724 }
726 ;------------------------------------------------------------------------------;
728 ; One power-of-two divisor divisor and one divisor in odd divisor
729 define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
730 ; CHECK-LABEL: test_srem_odd_poweroftwo_and_one:
731 ; CHECK: // %bb.0:
732 ; CHECK-NEXT: adrp x8, .LCPI22_0
733 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_0]
734 ; CHECK-NEXT: adrp x8, .LCPI22_1
735 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI22_1]
736 ; CHECK-NEXT: adrp x8, .LCPI22_2
737 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI22_2]
738 ; CHECK-NEXT: adrp x8, .LCPI22_3
739 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
740 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
741 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
742 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI22_3]
743 ; CHECK-NEXT: adrp x8, .LCPI22_4
744 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
745 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI22_4]
746 ; CHECK-NEXT: neg v3.4s, v3.4s
747 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
748 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
749 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
750 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
751 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
752 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
753 ; CHECK-NEXT: movi v1.4s, #1
754 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
755 ; CHECK-NEXT: ret
756 %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5>
757 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
758 %ret = zext <4 x i1> %cmp to <4 x i32>
759 ret <4 x i32> %ret
760 }
762 ; One power-of-two divisor divisor and one divisor in even divisor
763 define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
764 ; CHECK-LABEL: test_srem_even_poweroftwo_and_one:
765 ; CHECK: // %bb.0:
766 ; CHECK-NEXT: adrp x8, .LCPI23_0
767 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_0]
768 ; CHECK-NEXT: adrp x8, .LCPI23_1
769 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI23_1]
770 ; CHECK-NEXT: adrp x8, .LCPI23_2
771 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI23_2]
772 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
773 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
774 ; CHECK-NEXT: adrp x8, .LCPI23_3
775 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
776 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI23_3]
777 ; CHECK-NEXT: neg v2.4s, v2.4s
778 ; CHECK-NEXT: add v1.4s, v1.4s, v0.4s
779 ; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s
780 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
781 ; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
782 ; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
783 ; CHECK-NEXT: mls v0.4s, v1.4s, v4.4s
784 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
785 ; CHECK-NEXT: movi v1.4s, #1
786 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
787 ; CHECK-NEXT: ret
788 %srem = srem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14>
789 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
790 %ret = zext <4 x i1> %cmp to <4 x i32>
791 ret <4 x i32> %ret
792 }
794 ; One power-of-two divisor divisor and one divisor in odd+even divisor
795 define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
796 ; CHECK-LABEL: test_srem_odd_even_poweroftwo_and_one:
797 ; CHECK: // %bb.0:
798 ; CHECK-NEXT: adrp x8, .LCPI24_0
799 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_0]
800 ; CHECK-NEXT: adrp x8, .LCPI24_1
801 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI24_1]
802 ; CHECK-NEXT: adrp x8, .LCPI24_2
803 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI24_2]
804 ; CHECK-NEXT: adrp x8, .LCPI24_3
805 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
806 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
807 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
808 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI24_3]
809 ; CHECK-NEXT: adrp x8, .LCPI24_4
810 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
811 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI24_4]
812 ; CHECK-NEXT: neg v3.4s, v3.4s
813 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
814 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
815 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
816 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
817 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
818 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
819 ; CHECK-NEXT: movi v1.4s, #1
820 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
821 ; CHECK-NEXT: ret
822 %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100>
823 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
824 %ret = zext <4 x i1> %cmp to <4 x i32>
825 ret <4 x i32> %ret
826 }
828 ;------------------------------------------------------------------------------;
830 define <4 x i32> @test_srem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
831 ; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo_and_one:
832 ; CHECK: // %bb.0:
833 ; CHECK-NEXT: adrp x8, .LCPI25_0
834 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI25_0]
835 ; CHECK-NEXT: adrp x8, .LCPI25_1
836 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI25_1]
837 ; CHECK-NEXT: adrp x8, .LCPI25_2
838 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
839 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
840 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
841 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI25_2]
842 ; CHECK-NEXT: adrp x8, .LCPI25_3
843 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
844 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI25_3]
845 ; CHECK-NEXT: neg v4.4s, v4.4s
846 ; CHECK-NEXT: movi v3.2d, #0x000000ffffffff
847 ; CHECK-NEXT: sshl v4.4s, v1.4s, v4.4s
848 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
849 ; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
850 ; CHECK-NEXT: add v1.4s, v4.4s, v1.4s
851 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
852 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
853 ; CHECK-NEXT: movi v1.4s, #1
854 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
855 ; CHECK-NEXT: ret
856 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1>
857 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
858 %ret = zext <4 x i1> %cmp to <4 x i32>
859 ret <4 x i32> %ret
860 }
862 define <4 x i32> @test_srem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
863 ; CHECK-LABEL: test_srem_even_allones_and_poweroftwo_and_one:
864 ; CHECK: // %bb.0:
865 ; CHECK-NEXT: adrp x8, .LCPI26_0
866 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_0]
867 ; CHECK-NEXT: adrp x8, .LCPI26_1
868 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI26_1]
869 ; CHECK-NEXT: adrp x8, .LCPI26_2
870 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
871 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
872 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
873 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI26_2]
874 ; CHECK-NEXT: adrp x8, .LCPI26_3
875 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
876 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI26_3]
877 ; CHECK-NEXT: neg v4.4s, v4.4s
878 ; CHECK-NEXT: movi v3.2d, #0x000000ffffffff
879 ; CHECK-NEXT: sshl v4.4s, v1.4s, v4.4s
880 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
881 ; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
882 ; CHECK-NEXT: add v1.4s, v4.4s, v1.4s
883 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
884 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
885 ; CHECK-NEXT: movi v1.4s, #1
886 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
887 ; CHECK-NEXT: ret
888 %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1>
889 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
890 %ret = zext <4 x i1> %cmp to <4 x i32>
891 ret <4 x i32> %ret
892 }