lib/CodeGen/AsmPrinter/DwarfExpression.cpp

   1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains support for writing dwarf debug info into asm files.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "DwarfExpression.h"
  14 #include "DwarfCompileUnit.h"
  15 #include "llvm/ADT/APInt.h"
  16 #include "llvm/ADT/SmallBitVector.h"
  17 #include "llvm/BinaryFormat/Dwarf.h"
  18 #include "llvm/CodeGen/Register.h"
  19 #include "llvm/CodeGen/TargetRegisterInfo.h"
  20 #include "llvm/IR/DebugInfoMetadata.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include <algorithm>
  23 #include <cassert>
  24 #include <cstdint>
  25
  26 using namespace llvm;
  27
  28 void DwarfExpression::emitConstu(uint64_t Value) {
  29   if (Value < 32)
  30     emitOp(dwarf::DW_OP_lit0 + Value);
  31   else if (Value == std::numeric_limits<uint64_t>::max()) {
  32     // Only do this for 64-bit values as the DWARF expression stack uses
  33     // target-address-size values.
  34     emitOp(dwarf::DW_OP_lit0);
  35     emitOp(dwarf::DW_OP_not);
  36   } else {
  37     emitOp(dwarf::DW_OP_constu);
  38     emitUnsigned(Value);
  39   }
  40 }
  41
  42 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
  43  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
  44  assert((isUnknownLocation() || isRegisterLocation()) &&
  45         "location description already locked down");
  46  LocationKind = Register;
  47  if (DwarfReg < 32) {
  48    emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
  49   } else {
  50     emitOp(dwarf::DW_OP_regx, Comment);
  51     emitUnsigned(DwarfReg);
  52   }
  53 }
  54
  55 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
  56   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
  57   assert(!isRegisterLocation() && "location description already locked down");
  58   if (DwarfReg < 32) {
  59     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
  60   } else {
  61     emitOp(dwarf::DW_OP_bregx);
  62     emitUnsigned(DwarfReg);
  63   }
  64   emitSigned(Offset);
  65 }
  66
  67 void DwarfExpression::addFBReg(int Offset) {
  68   emitOp(dwarf::DW_OP_fbreg);
  69   emitSigned(Offset);
  70 }
  71
  72 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
  73   if (!SizeInBits)
  74     return;
  75
  76   const unsigned SizeOfByte = 8;
  77   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
  78     emitOp(dwarf::DW_OP_bit_piece);
  79     emitUnsigned(SizeInBits);
  80     emitUnsigned(OffsetInBits);
  81   } else {
  82     emitOp(dwarf::DW_OP_piece);
  83     unsigned ByteSize = SizeInBits / SizeOfByte;
  84     emitUnsigned(ByteSize);
  85   }
  86   this->OffsetInBits += SizeInBits;
  87 }
  88
  89 void DwarfExpression::addShr(unsigned ShiftBy) {
  90   emitConstu(ShiftBy);
  91   emitOp(dwarf::DW_OP_shr);
  92 }
  93
  94 void DwarfExpression::addAnd(unsigned Mask) {
  95   emitConstu(Mask);
  96   emitOp(dwarf::DW_OP_and);
  97 }
  98
  99 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
 100                                     unsigned MachineReg, unsigned MaxSize) {
 101   if (!llvm::Register::isPhysicalRegister(MachineReg)) {
 102     if (isFrameRegister(TRI, MachineReg)) {
 103       DwarfRegs.push_back({-1, 0, nullptr});
 104       return true;
 105     }
 106     return false;
 107   }
 108
 109   int Reg = TRI.getDwarfRegNum(MachineReg, false);
 110
 111   // If this is a valid register number, emit it.
 112   if (Reg >= 0) {
 113     DwarfRegs.push_back({Reg, 0, nullptr});
 114     return true;
 115   }
 116
 117   // Walk up the super-register chain until we find a valid number.
 118   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
 119   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
 120     Reg = TRI.getDwarfRegNum(*SR, false);
 121     if (Reg >= 0) {
 122       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
 123       unsigned Size = TRI.getSubRegIdxSize(Idx);
 124       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
 125       DwarfRegs.push_back({Reg, 0, "super-register"});
 126       // Use a DW_OP_bit_piece to describe the sub-register.
 127       setSubRegisterPiece(Size, RegOffset);
 128       return true;
 129     }
 130   }
 131
 132   // Otherwise, attempt to find a covering set of sub-register numbers.
 133   // For example, Q0 on ARM is a composition of D0+D1.
 134   unsigned CurPos = 0;
 135   // The size of the register in bits.
 136   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
 137   unsigned RegSize = TRI.getRegSizeInBits(*RC);
 138   // Keep track of the bits in the register we already emitted, so we
 139   // can avoid emitting redundant aliasing subregs. Because this is
 140   // just doing a greedy scan of all subregisters, it is possible that
 141   // this doesn't find a combination of subregisters that fully cover
 142   // the register (even though one may exist).
 143   SmallBitVector Coverage(RegSize, false);
 144   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
 145     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
 146     unsigned Size = TRI.getSubRegIdxSize(Idx);
 147     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
 148     Reg = TRI.getDwarfRegNum(*SR, false);
 149     if (Reg < 0)
 150       continue;
 151
 152     // Intersection between the bits we already emitted and the bits
 153     // covered by this subregister.
 154     SmallBitVector CurSubReg(RegSize, false);
 155     CurSubReg.set(Offset, Offset + Size);
 156
 157     // If this sub-register has a DWARF number and we haven't covered
 158     // its range, emit a DWARF piece for it.
 159     if (CurSubReg.test(Coverage)) {
 160       // Emit a piece for any gap in the coverage.
 161       if (Offset > CurPos)
 162         DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
 163       DwarfRegs.push_back(
 164           {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
 165       if (Offset >= MaxSize)
 166         break;
 167
 168       // Mark it as emitted.
 169       Coverage.set(Offset, Offset + Size);
 170       CurPos = Offset + Size;
 171     }
 172   }
 173   // Failed to find any DWARF encoding.
 174   if (CurPos == 0)
 175     return false;
 176   // Found a partial or complete DWARF encoding.
 177   if (CurPos < RegSize)
 178     DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
 179   return true;
 180 }
 181
 182 void DwarfExpression::addStackValue() {
 183   if (DwarfVersion >= 4)
 184     emitOp(dwarf::DW_OP_stack_value);
 185 }
 186
 187 void DwarfExpression::addSignedConstant(int64_t Value) {
 188   assert(isImplicitLocation() || isUnknownLocation());
 189   LocationKind = Implicit;
 190   emitOp(dwarf::DW_OP_consts);
 191   emitSigned(Value);
 192 }
 193
 194 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
 195   assert(isImplicitLocation() || isUnknownLocation());
 196   LocationKind = Implicit;
 197   emitConstu(Value);
 198 }
 199
 200 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
 201   assert(isImplicitLocation() || isUnknownLocation());
 202   LocationKind = Implicit;
 203
 204   unsigned Size = Value.getBitWidth();
 205   const uint64_t *Data = Value.getRawData();
 206
 207   // Chop it up into 64-bit pieces, because that's the maximum that
 208   // addUnsignedConstant takes.
 209   unsigned Offset = 0;
 210   while (Offset < Size) {
 211     addUnsignedConstant(*Data++);
 212     if (Offset == 0 && Size <= 64)
 213       break;
 214     addStackValue();
 215     addOpPiece(std::min(Size - Offset, 64u), Offset);
 216     Offset += 64;
 217   }
 218 }
 219
 220 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
 221                                               DIExpressionCursor &ExprCursor,
 222                                               unsigned MachineReg,
 223                                               unsigned FragmentOffsetInBits) {
 224   auto Fragment = ExprCursor.getFragmentInfo();
 225   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
 226     LocationKind = Unknown;
 227     return false;
 228   }
 229
 230   bool HasComplexExpression = false;
 231   auto Op = ExprCursor.peek();
 232   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
 233     HasComplexExpression = true;
 234
 235   // If the register can only be described by a complex expression (i.e.,
 236   // multiple subregisters) it doesn't safely compose with another complex
 237   // expression. For example, it is not possible to apply a DW_OP_deref
 238   // operation to multiple DW_OP_pieces.
 239   if (HasComplexExpression && DwarfRegs.size() > 1) {
 240     DwarfRegs.clear();
 241     LocationKind = Unknown;
 242     return false;
 243   }
 244
 245   // Handle simple register locations. If we are supposed to emit
 246   // a call site parameter expression and if that expression is just a register
 247   // location, emit it with addBReg and offset 0, because we should emit a DWARF
 248   // expression representing a value, rather than a location.
 249   if (!isMemoryLocation() && !HasComplexExpression && (!isParameterValue() ||
 250                                                        isEntryValue())) {
 251     for (auto &Reg : DwarfRegs) {
 252       if (Reg.DwarfRegNo >= 0)
 253         addReg(Reg.DwarfRegNo, Reg.Comment);
 254       addOpPiece(Reg.Size);
 255     }
 256
 257     if (isEntryValue() && !isParameterValue() && DwarfVersion >= 4)
 258       emitOp(dwarf::DW_OP_stack_value);
 259
 260     DwarfRegs.clear();
 261     return true;
 262   }
 263
 264   // Don't emit locations that cannot be expressed without DW_OP_stack_value.
 265   if (DwarfVersion < 4)
 266     if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
 267           return Op.getOp() == dwarf::DW_OP_stack_value;
 268         })) {
 269       DwarfRegs.clear();
 270       LocationKind = Unknown;
 271       return false;
 272     }
 273
 274   assert(DwarfRegs.size() == 1);
 275   auto Reg = DwarfRegs[0];
 276   bool FBReg = isFrameRegister(TRI, MachineReg);
 277   int SignedOffset = 0;
 278   assert(Reg.Size == 0 && "subregister has same size as superregister");
 279
 280   // Pattern-match combinations for which more efficient representations exist.
 281   // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
 282   if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
 283     SignedOffset = Op->getArg(0);
 284     ExprCursor.take();
 285   }
 286
 287   // [Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset]
 288   // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
 289   // If Reg is a subregister we need to mask it out before subtracting.
 290   if (Op && Op->getOp() == dwarf::DW_OP_constu) {
 291     auto N = ExprCursor.peekNext();
 292     if (N && (N->getOp() == dwarf::DW_OP_plus ||
 293              (N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
 294       int Offset = Op->getArg(0);
 295       SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset;
 296       ExprCursor.consume(2);
 297     }
 298   }
 299
 300   if (FBReg)
 301     addFBReg(SignedOffset);
 302   else
 303     addBReg(Reg.DwarfRegNo, SignedOffset);
 304   DwarfRegs.clear();
 305   return true;
 306 }
 307
 308 void DwarfExpression::addEntryValueExpression(DIExpressionCursor &ExprCursor) {
 309   auto Op = ExprCursor.take();
 310   assert(Op && Op->getOp() == dwarf::DW_OP_entry_value);
 311   assert(!isMemoryLocation() &&
 312          "We don't support entry values of memory locations yet");
 313
 314   emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value));
 315   emitUnsigned(Op->getArg(0));
 316 }
 317
 318 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
 319 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
 320   while (ExprCursor) {
 321     auto Op = ExprCursor.take();
 322     switch (Op->getOp()) {
 323     case dwarf::DW_OP_deref:
 324     case dwarf::DW_OP_LLVM_fragment:
 325       break;
 326     default:
 327       return false;
 328     }
 329   }
 330   return true;
 331 }
 332
 333 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
 334                                     unsigned FragmentOffsetInBits) {
 335   // If we need to mask out a subregister, do it now, unless the next
 336   // operation would emit an OpPiece anyway.
 337   auto N = ExprCursor.peek();
 338   if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
 339     maskSubRegister();
 340
 341   Optional<DIExpression::ExprOperand> PrevConvertOp = None;
 342
 343   while (ExprCursor) {
 344     auto Op = ExprCursor.take();
 345     uint64_t OpNum = Op->getOp();
 346
 347     if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
 348       emitOp(OpNum);
 349       continue;
 350     } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
 351       addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
 352       continue;
 353     }
 354
 355     switch (OpNum) {
 356     case dwarf::DW_OP_LLVM_fragment: {
 357       unsigned SizeInBits = Op->getArg(1);
 358       unsigned FragmentOffset = Op->getArg(0);
 359       // The fragment offset must have already been adjusted by emitting an
 360       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
 361       // location.
 362       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
 363
 364       // If addMachineReg already emitted DW_OP_piece operations to represent
 365       // a super-register by splicing together sub-registers, subtract the size
 366       // of the pieces that was already emitted.
 367       SizeInBits -= OffsetInBits - FragmentOffset;
 368
 369       // If addMachineReg requested a DW_OP_bit_piece to stencil out a
 370       // sub-register that is smaller than the current fragment's size, use it.
 371       if (SubRegisterSizeInBits)
 372         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
 373
 374       // Emit a DW_OP_stack_value for implicit location descriptions.
 375       if (isImplicitLocation())
 376         addStackValue();
 377
 378       // Emit the DW_OP_piece.
 379       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
 380       setSubRegisterPiece(0, 0);
 381       // Reset the location description kind.
 382       LocationKind = Unknown;
 383       return;
 384     }
 385     case dwarf::DW_OP_plus_uconst:
 386       assert(!isRegisterLocation());
 387       emitOp(dwarf::DW_OP_plus_uconst);
 388       emitUnsigned(Op->getArg(0));
 389       break;
 390     case dwarf::DW_OP_plus:
 391     case dwarf::DW_OP_minus:
 392     case dwarf::DW_OP_mul:
 393     case dwarf::DW_OP_div:
 394     case dwarf::DW_OP_mod:
 395     case dwarf::DW_OP_or:
 396     case dwarf::DW_OP_and:
 397     case dwarf::DW_OP_xor:
 398     case dwarf::DW_OP_shl:
 399     case dwarf::DW_OP_shr:
 400     case dwarf::DW_OP_shra:
 401     case dwarf::DW_OP_lit0:
 402     case dwarf::DW_OP_not:
 403     case dwarf::DW_OP_dup:
 404       emitOp(OpNum);
 405       break;
 406     case dwarf::DW_OP_deref:
 407       assert(!isRegisterLocation());
 408       if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
 409         // Turning this into a memory location description makes the deref
 410         // implicit.
 411         LocationKind = Memory;
 412       else
 413         emitOp(dwarf::DW_OP_deref);
 414       break;
 415     case dwarf::DW_OP_constu:
 416       assert(!isRegisterLocation());
 417       emitConstu(Op->getArg(0));
 418       break;
 419     case dwarf::DW_OP_LLVM_convert: {
 420       unsigned BitSize = Op->getArg(0);
 421       dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
 422       if (DwarfVersion >= 5) {
 423         emitOp(dwarf::DW_OP_convert);
 424         // Reuse the base_type if we already have one in this CU otherwise we
 425         // create a new one.
 426         unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
 427         for (; I != E; ++I)
 428           if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
 429               CU.ExprRefedBaseTypes[I].Encoding == Encoding)
 430             break;
 431
 432         if (I == E)
 433           CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
 434
 435         // If targeting a location-list; simply emit the index into the raw
 436         // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
 437         // fitted with means to extract it later.
 438         // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
 439         // (containing the index and a resolve mechanism during emit) into the
 440         // DIE value list.
 441         emitBaseTypeRef(I);
 442       } else {
 443         if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
 444           if (Encoding == dwarf::DW_ATE_signed)
 445             emitLegacySExt(PrevConvertOp->getArg(0));
 446           else if (Encoding == dwarf::DW_ATE_unsigned)
 447             emitLegacyZExt(PrevConvertOp->getArg(0));
 448           PrevConvertOp = None;
 449         } else {
 450           PrevConvertOp = Op;
 451         }
 452       }
 453       break;
 454     }
 455     case dwarf::DW_OP_stack_value:
 456       LocationKind = Implicit;
 457       break;
 458     case dwarf::DW_OP_swap:
 459       assert(!isRegisterLocation());
 460       emitOp(dwarf::DW_OP_swap);
 461       break;
 462     case dwarf::DW_OP_xderef:
 463       assert(!isRegisterLocation());
 464       emitOp(dwarf::DW_OP_xderef);
 465       break;
 466     case dwarf::DW_OP_deref_size:
 467       emitOp(dwarf::DW_OP_deref_size);
 468       emitData1(Op->getArg(0));
 469       break;
 470     case dwarf::DW_OP_LLVM_tag_offset:
 471       TagOffset = Op->getArg(0);
 472       break;
 473     case dwarf::DW_OP_regx:
 474       emitOp(dwarf::DW_OP_regx);
 475       emitUnsigned(Op->getArg(0));
 476       break;
 477     case dwarf::DW_OP_bregx:
 478       emitOp(dwarf::DW_OP_bregx);
 479       emitUnsigned(Op->getArg(0));
 480       emitSigned(Op->getArg(1));
 481       break;
 482     default:
 483       llvm_unreachable("unhandled opcode found in expression");
 484     }
 485   }
 486
 487   if (isImplicitLocation() && !isParameterValue())
 488     // Turn this into an implicit location description.
 489     addStackValue();
 490 }
 491
 492 /// add masking operations to stencil out a subregister.
 493 void DwarfExpression::maskSubRegister() {
 494   assert(SubRegisterSizeInBits && "no subregister was registered");
 495   if (SubRegisterOffsetInBits > 0)
 496     addShr(SubRegisterOffsetInBits);
 497   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
 498   addAnd(Mask);
 499 }
 500
 501 void DwarfExpression::finalize() {
 502   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
 503   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
 504   if (SubRegisterSizeInBits == 0)
 505     return;
 506   // Don't emit a DW_OP_piece for a subregister at offset 0.
 507   if (SubRegisterOffsetInBits == 0)
 508     return;
 509   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
 510 }
 511
 512 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
 513   if (!Expr || !Expr->isFragment())
 514     return;
 515
 516   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
 517   assert(FragmentOffset >= OffsetInBits &&
 518          "overlapping or duplicate fragments");
 519   if (FragmentOffset > OffsetInBits)
 520     addOpPiece(FragmentOffset - OffsetInBits);
 521   OffsetInBits = FragmentOffset;
 522 }
 523
 524 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
 525   // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
 526   emitOp(dwarf::DW_OP_dup);
 527   emitOp(dwarf::DW_OP_constu);
 528   emitUnsigned(FromBits - 1);
 529   emitOp(dwarf::DW_OP_shr);
 530   emitOp(dwarf::DW_OP_lit0);
 531   emitOp(dwarf::DW_OP_not);
 532   emitOp(dwarf::DW_OP_mul);
 533   emitOp(dwarf::DW_OP_constu);
 534   emitUnsigned(FromBits);
 535   emitOp(dwarf::DW_OP_shl);
 536   emitOp(dwarf::DW_OP_or);
 537 }
 538
 539 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
 540   // (X & (1 << FromBits - 1))
 541   emitOp(dwarf::DW_OP_constu);
 542   emitUnsigned((1ULL << FromBits) - 1);
 543   emitOp(dwarf::DW_OP_and);
 544 }