test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs  -o - %s | FileCheck -check-prefix=GCN  %s
   3
   4 ---
   5 name: test_build_vector_v_v2s32_v_s32_v_s32
   6 legalized:       true
   7 regBankSelected: true
   8 tracksRegLiveness: true
   9
  10 body: |
  11   bb.0:
  12     liveins: $vgpr0, $vgpr1
  13
  14     ; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_v_s32
  15     ; GCN: liveins: $vgpr0, $vgpr1
  16     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  17     ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  18     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  19     ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  20     %0:vgpr(s32) = COPY $vgpr0
  21     %1:vgpr(s32) = COPY $vgpr1
  22     %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
  23     S_ENDPGM 0, implicit %2
  24 ...
  25
  26 ---
  27 name: test_build_vector_v_v2s32_s_s32_v_s32
  28 legalized:       true
  29 regBankSelected: true
  30 tracksRegLiveness: true
  31
  32 body: |
  33   bb.0:
  34     liveins: $sgpr0, $vgpr0
  35
  36     ; GCN-LABEL: name: test_build_vector_v_v2s32_s_s32_v_s32
  37     ; GCN: liveins: $sgpr0, $vgpr0
  38     ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
  39     ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  40     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  41     ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  42     %0:sgpr(s32) = COPY $sgpr0
  43     %1:vgpr(s32) = COPY $vgpr0
  44     %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
  45     S_ENDPGM 0, implicit %2
  46 ...
  47
  48 ---
  49 name: test_build_vector_v_v2s32_v_s32_s_s32
  50 legalized:       true
  51 regBankSelected: true
  52 tracksRegLiveness: true
  53
  54 body: |
  55   bb.0:
  56     liveins: $sgpr0, $vgpr0
  57
  58     ; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_s_s32
  59     ; GCN: liveins: $sgpr0, $vgpr0
  60     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  61     ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
  62     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  63     ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  64     %0:vgpr(s32) = COPY $vgpr0
  65     %1:sgpr(s32) = COPY $sgpr0
  66     %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
  67     S_ENDPGM 0, implicit %2
  68 ...
  69
  70 ---
  71 name: test_build_vector_s_v2s32_s_s32_s_s32
  72 legalized:       true
  73 regBankSelected: true
  74 tracksRegLiveness: true
  75
  76 body: |
  77   bb.0:
  78     liveins: $sgpr0, $sgpr1
  79
  80     ; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_s_s32
  81     ; GCN: liveins: $sgpr0, $sgpr1
  82     ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
  83     ; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
  84     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  85     ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  86     %0:sgpr(s32) = COPY $sgpr0
  87     %1:sgpr(s32) = COPY $sgpr1
  88     %2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
  89     S_ENDPGM 0, implicit %2
  90 ...
  91
  92 ---
  93 name: test_build_vector_s_v2s32_undef_s_s32_s_s32
  94 legalized:       true
  95 regBankSelected: true
  96 tracksRegLiveness: true
  97
  98 body: |
  99   bb.0:
 100     liveins: $sgpr0
 101
 102     ; GCN-LABEL: name: test_build_vector_s_v2s32_undef_s_s32_s_s32
 103     ; GCN: liveins: $sgpr0
 104     ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
 105     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE undef %2:sreg_32_xm0, %subreg.sub0, [[COPY]], %subreg.sub1
 106     ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 107     %1:sgpr(s32) = COPY $sgpr0
 108     %2:sgpr(<2 x s32>) = G_BUILD_VECTOR undef %0:sgpr(s32), %1
 109     S_ENDPGM 0, implicit %2
 110 ...
 111
 112 ---
 113 name: test_build_vector_s_v2s32_s_s32_undef_s_s32
 114 legalized:       true
 115 regBankSelected: true
 116 tracksRegLiveness: true
 117
 118 body: |
 119   bb.0:
 120     liveins: $sgpr0
 121
 122     ; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_undef_s_s32
 123     ; GCN: liveins: $sgpr0
 124     ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
 125     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32_xm0, %subreg.sub1
 126     ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 127     %0:sgpr(s32) = COPY $sgpr0
 128     %2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, undef %1:sgpr(s32),
 129     S_ENDPGM 0, implicit %2
 130 ...
 131
 132 ---
 133 name: test_build_vector_s_v2s64_s_s64_s_s64
 134 legalized:       true
 135 regBankSelected: true
 136 tracksRegLiveness: true
 137
 138 body: |
 139   bb.0:
 140     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 141
 142     ; GCN-LABEL: name: test_build_vector_s_v2s64_s_s64_s_s64
 143     ; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 144     ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 145     ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
 146     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
 147     ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
 148     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 149     %1:sgpr(s64) = COPY $sgpr2_sgpr3
 150     %4:sgpr(<2 x s64>) = G_BUILD_VECTOR %0, %1
 151     $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4
 152 ...