test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
   3 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE32 %s
   4
   5 ---
   6
   7 name:            or_s1_vcc_vcc_vcc
   8 legalized:       true
   9 regBankSelected: true
  10 tracksRegLiveness: true
  11
  12 body: |
  13   bb.0:
  14     liveins: $vgpr0, $vgpr1
  15     ; WAVE64-LABEL: name: or_s1_vcc_vcc_vcc
  16     ; WAVE64: liveins: $vgpr0, $vgpr1
  17     ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  18     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  19     ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  20     ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
  21     ; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
  22     ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
  23     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
  24     ; WAVE32-LABEL: name: or_s1_vcc_vcc_vcc
  25     ; WAVE32: liveins: $vgpr0, $vgpr1
  26     ; WAVE32: $vcc_hi = IMPLICIT_DEF
  27     ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  28     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  29     ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  30     ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
  31     ; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
  32     ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
  33     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
  34     %0:vgpr(s32) = COPY $vgpr0
  35     %1:vgpr(s32) = COPY $vgpr1
  36     %2:vgpr(s32) = G_CONSTANT i32 0
  37     %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
  38     %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
  39     %5:vcc(s1) = G_OR %3, %4
  40     S_ENDPGM 0, implicit %5
  41 ...
  42
  43 ---
  44
  45 name:            or_s1_sgpr_sgpr_sgpr
  46 legalized:       true
  47 regBankSelected: true
  48 tracksRegLiveness: true
  49
  50 body: |
  51   bb.0:
  52     liveins: $sgpr0, $sgpr1
  53     ; WAVE64-LABEL: name: or_s1_sgpr_sgpr_sgpr
  54     ; WAVE64: liveins: $sgpr0, $sgpr1
  55     ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
  56     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
  57     ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
  58     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
  59     ; WAVE32-LABEL: name: or_s1_sgpr_sgpr_sgpr
  60     ; WAVE32: liveins: $sgpr0, $sgpr1
  61     ; WAVE32: $vcc_hi = IMPLICIT_DEF
  62     ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
  63     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
  64     ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
  65     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
  66     %0:sgpr(s32) = COPY $sgpr0
  67     %1:sgpr(s32) = COPY $sgpr1
  68     %2:sgpr(s1) = G_TRUNC %0
  69     %3:sgpr(s1) = G_TRUNC %1
  70     %4:sgpr(s1) = G_OR %2, %3
  71     S_ENDPGM 0, implicit %4
  72 ...
  73
  74 ---
  75
  76 name:            or_s1_scc_sgpr_sgpr
  77 legalized:       true
  78 regBankSelected: true
  79 tracksRegLiveness: true
  80
  81 body: |
  82   bb.0:
  83     liveins: $sgpr0, $sgpr1
  84     ; WAVE64-LABEL: name: or_s1_scc_sgpr_sgpr
  85     ; WAVE64: liveins: $sgpr0, $sgpr1
  86     ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
  87     ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
  88     ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
  89     ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
  90     ; WAVE64: [[OR:%[0-9]+]]:scc(s1) = G_OR [[TRUNC]], [[TRUNC1]]
  91     ; WAVE64: S_ENDPGM 0, implicit [[OR]](s1)
  92     ; WAVE32-LABEL: name: or_s1_scc_sgpr_sgpr
  93     ; WAVE32: liveins: $sgpr0, $sgpr1
  94     ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
  95     ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
  96     ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
  97     ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
  98     ; WAVE32: [[OR:%[0-9]+]]:scc(s1) = G_OR [[TRUNC]], [[TRUNC1]]
  99     ; WAVE32: S_ENDPGM 0, implicit [[OR]](s1)
 100     %0:sgpr(s32) = COPY $sgpr0
 101     %1:sgpr(s32) = COPY $sgpr1
 102     %2:sgpr(s1) = G_TRUNC %0
 103     %3:sgpr(s1) = G_TRUNC %1
 104     %4:scc(s1) = G_OR %2, %3
 105     S_ENDPGM 0, implicit %4
 106 ...
 107
 108 ---
 109
 110 name:            or_s16_sgpr_sgpr_sgpr
 111 legalized:       true
 112 regBankSelected: true
 113 tracksRegLiveness: true
 114
 115 body: |
 116   bb.0:
 117     liveins: $sgpr0, $sgpr1
 118     ; WAVE64-LABEL: name: or_s16_sgpr_sgpr_sgpr
 119     ; WAVE64: liveins: $sgpr0, $sgpr1
 120     ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
 121     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
 122     ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
 123     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
 124     ; WAVE32-LABEL: name: or_s16_sgpr_sgpr_sgpr
 125     ; WAVE32: liveins: $sgpr0, $sgpr1
 126     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 127     ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
 128     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
 129     ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
 130     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
 131     %0:sgpr(s32) = COPY $sgpr0
 132     %1:sgpr(s32) = COPY $sgpr1
 133     %2:sgpr(s16) = G_TRUNC %0
 134     %3:sgpr(s16) = G_TRUNC %1
 135     %4:sgpr(s16) = G_OR %2, %3
 136     S_ENDPGM 0, implicit %4
 137 ...
 138
 139 ---
 140
 141 name:            or_s16_vgpr_vgpr_vgpr
 142 legalized:       true
 143 regBankSelected: true
 144 tracksRegLiveness: true
 145
 146 body: |
 147   bb.0:
 148     liveins: $vgpr0, $vgpr1
 149     ; WAVE64-LABEL: name: or_s16_vgpr_vgpr_vgpr
 150     ; WAVE64: liveins: $vgpr0, $vgpr1
 151     ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
 152     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
 153     ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
 154     ; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
 155     ; WAVE64: [[OR:%[0-9]+]]:vgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
 156     ; WAVE64: S_ENDPGM 0, implicit [[OR]](s16)
 157     ; WAVE32-LABEL: name: or_s16_vgpr_vgpr_vgpr
 158     ; WAVE32: liveins: $vgpr0, $vgpr1
 159     ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
 160     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
 161     ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
 162     ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
 163     ; WAVE32: [[OR:%[0-9]+]]:vgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
 164     ; WAVE32: S_ENDPGM 0, implicit [[OR]](s16)
 165     %0:vgpr(s32) = COPY $vgpr0
 166     %1:vgpr(s32) = COPY $vgpr1
 167     %2:vgpr(s16) = G_TRUNC %0
 168     %3:vgpr(s16) = G_TRUNC %1
 169     %4:vgpr(s16) = G_OR %2, %3
 170     S_ENDPGM 0, implicit %4
 171 ...
 172
 173 ---
 174
 175 name:            or_s32_sgpr_sgpr_sgpr
 176 legalized:       true
 177 regBankSelected: true
 178 tracksRegLiveness: true
 179
 180 body: |
 181   bb.0:
 182     liveins: $sgpr0, $sgpr1
 183     ; WAVE64-LABEL: name: or_s32_sgpr_sgpr_sgpr
 184     ; WAVE64: liveins: $sgpr0, $sgpr1
 185     ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
 186     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
 187     ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
 188     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
 189     ; WAVE32-LABEL: name: or_s32_sgpr_sgpr_sgpr
 190     ; WAVE32: liveins: $sgpr0, $sgpr1
 191     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 192     ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
 193     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
 194     ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
 195     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
 196     %0:sgpr(s32) = COPY $sgpr0
 197     %1:sgpr(s32) = COPY $sgpr1
 198     %2:sgpr(s32) = G_OR %0, %1
 199     S_ENDPGM 0, implicit %2
 200 ...
 201
 202 ---
 203
 204 name:            or_s64_sgpr_sgpr_sgpr
 205 legalized:       true
 206 regBankSelected: true
 207 tracksRegLiveness: true
 208
 209 body: |
 210   bb.0:
 211     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 212     ; WAVE64-LABEL: name: or_s64_sgpr_sgpr_sgpr
 213     ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 214     ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 215     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
 216     ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
 217     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
 218     ; WAVE32-LABEL: name: or_s64_sgpr_sgpr_sgpr
 219     ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 220     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 221     ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 222     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
 223     ; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
 224     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
 225     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 226     %1:sgpr(s64) = COPY $sgpr2_sgpr3
 227     %2:sgpr(s64) = G_OR %0, %1
 228     S_ENDPGM 0, implicit %2
 229 ...
 230
 231 ---
 232
 233 name:            or_v2s16_sgpr_sgpr_sgpr
 234 legalized:       true
 235 regBankSelected: true
 236 tracksRegLiveness: true
 237
 238 body: |
 239   bb.0:
 240     liveins: $sgpr0, $sgpr1
 241     ; WAVE64-LABEL: name: or_v2s16_sgpr_sgpr_sgpr
 242     ; WAVE64: liveins: $sgpr0, $sgpr1
 243     ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
 244     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
 245     ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
 246     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
 247     ; WAVE32-LABEL: name: or_v2s16_sgpr_sgpr_sgpr
 248     ; WAVE32: liveins: $sgpr0, $sgpr1
 249     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 250     ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
 251     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
 252     ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
 253     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
 254     %0:sgpr(<2 x s16>) = COPY $sgpr0
 255     %1:sgpr(<2 x s16>) = COPY $sgpr1
 256     %2:sgpr(<2 x s16>) = G_OR %0, %1
 257     S_ENDPGM 0, implicit %2
 258 ...
 259
 260 ---
 261
 262 name:            or_v2s32_sgpr_sgpr_sgpr
 263 legalized:       true
 264 regBankSelected: true
 265 tracksRegLiveness: true
 266
 267 body: |
 268   bb.0:
 269     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 270     ; WAVE64-LABEL: name: or_v2s32_sgpr_sgpr_sgpr
 271     ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 272     ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 273     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
 274     ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
 275     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
 276     ; WAVE32-LABEL: name: or_v2s32_sgpr_sgpr_sgpr
 277     ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 278     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 279     ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 280     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
 281     ; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
 282     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
 283     %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
 284     %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
 285     %2:sgpr(<2 x s32>) = G_OR %0, %1
 286     S_ENDPGM 0, implicit %2
 287 ...
 288
 289 ---
 290
 291 name:            or_v4s16_sgpr_sgpr_sgpr
 292 legalized:       true
 293 regBankSelected: true
 294 tracksRegLiveness: true
 295
 296 body: |
 297   bb.0:
 298     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 299     ; WAVE64-LABEL: name: or_v4s16_sgpr_sgpr_sgpr
 300     ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 301     ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 302     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
 303     ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
 304     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
 305     ; WAVE32-LABEL: name: or_v4s16_sgpr_sgpr_sgpr
 306     ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 307     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 308     ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
 309     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
 310     ; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
 311     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
 312     %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
 313     %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
 314     %2:sgpr(<4 x s16>) = G_OR %0, %1
 315     S_ENDPGM 0, implicit %2
 316 ...
 317
 318 ---
 319
 320 name:            or_s32_vgpr_vgpr_vgpr
 321 legalized:       true
 322 regBankSelected: true
 323 tracksRegLiveness: true
 324
 325 body: |
 326   bb.0:
 327     liveins: $vgpr0, $vgpr1
 328     ; WAVE64-LABEL: name: or_s32_vgpr_vgpr_vgpr
 329     ; WAVE64: liveins: $vgpr0, $vgpr1
 330     ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 331     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 332     ; WAVE64: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[COPY]], [[COPY1]], implicit $exec
 333     ; WAVE64: S_ENDPGM 0, implicit [[V_OR_B32_e32_]]
 334     ; WAVE32-LABEL: name: or_s32_vgpr_vgpr_vgpr
 335     ; WAVE32: liveins: $vgpr0, $vgpr1
 336     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 337     ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 338     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 339     ; WAVE32: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[COPY]], [[COPY1]], implicit $exec
 340     ; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e32_]]
 341     %0:vgpr(s32) = COPY $vgpr0
 342     %1:vgpr(s32) = COPY $vgpr1
 343     %2:vgpr(s32) = G_OR %0, %1
 344     S_ENDPGM 0, implicit %2
 345 ...
 346
 347 ---
 348
 349 name:            or_v2s16_vgpr_vgpr_vgpr
 350 legalized:       true
 351 regBankSelected: true
 352 tracksRegLiveness: true
 353
 354 body: |
 355   bb.0:
 356     liveins: $vgpr0, $vgpr1
 357     ; WAVE64-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
 358     ; WAVE64: liveins: $vgpr0, $vgpr1
 359     ; WAVE64: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
 360     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
 361     ; WAVE64: [[OR:%[0-9]+]]:vgpr(<2 x s16>) = G_OR [[COPY]], [[COPY1]]
 362     ; WAVE64: S_ENDPGM 0, implicit [[OR]](<2 x s16>)
 363     ; WAVE32-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
 364     ; WAVE32: liveins: $vgpr0, $vgpr1
 365     ; WAVE32: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
 366     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
 367     ; WAVE32: [[OR:%[0-9]+]]:vgpr(<2 x s16>) = G_OR [[COPY]], [[COPY1]]
 368     ; WAVE32: S_ENDPGM 0, implicit [[OR]](<2 x s16>)
 369     %0:vgpr(<2 x s16>) = COPY $vgpr0
 370     %1:vgpr(<2 x s16>) = COPY $vgpr1
 371     %2:vgpr(<2 x s16>) = G_OR %0, %1
 372     S_ENDPGM 0, implicit %2
 373 ...
 374
 375
 376 # This should fail to select
 377 ---
 378
 379 name:            or_s64_vgpr_vgpr_vgpr
 380 legalized:       true
 381 regBankSelected: true
 382 tracksRegLiveness: true
 383
 384 body: |
 385   bb.0:
 386     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 387     ; WAVE64-LABEL: name: or_s64_vgpr_vgpr_vgpr
 388     ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 389     ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
 390     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
 391     ; WAVE64: [[OR:%[0-9]+]]:vgpr(s64) = G_OR [[COPY]], [[COPY1]]
 392     ; WAVE64: S_ENDPGM 0, implicit [[OR]](s64)
 393     ; WAVE32-LABEL: name: or_s64_vgpr_vgpr_vgpr
 394     ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 395     ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
 396     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
 397     ; WAVE32: [[OR:%[0-9]+]]:vgpr(s64) = G_OR [[COPY]], [[COPY1]]
 398     ; WAVE32: S_ENDPGM 0, implicit [[OR]](s64)
 399     %0:vgpr(s64) = COPY $vgpr0_vgpr1
 400     %1:vgpr(s64) = COPY $vgpr2_vgpr3
 401     %2:vgpr(s64) = G_OR %0, %1
 402     S_ENDPGM 0, implicit %2
 403 ...
 404
 405 ---
 406
 407 name:            or_s1_vcc_undef_vcc_undef_vcc
 408 legalized:       true
 409 regBankSelected: true
 410 tracksRegLiveness: true
 411
 412 body: |
 413   bb.0:
 414     ; WAVE64-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
 415     ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 undef %1:sreg_64, undef %2:sreg_64
 416     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
 417     ; WAVE32-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
 418     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 419     ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
 420     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
 421     %2:vcc(s1) = G_OR undef %0:vcc(s1), undef %1:vcc(s1)
 422     S_ENDPGM 0, implicit %2
 423 ...
 424
 425 ---
 426
 427 name:            or_s1_sgpr_undef_sgpr_undef_sgpr
 428 legalized:       true
 429 regBankSelected: true
 430 tracksRegLiveness: true
 431
 432 body: |
 433   bb.0:
 434     ; WAVE64-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr
 435     ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
 436     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
 437     ; WAVE32-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr
 438     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 439     ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
 440     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
 441     %2:sgpr(s1) = G_OR undef %0:sgpr(s1), undef %1:sgpr(s1)
 442     S_ENDPGM 0, implicit %2
 443 ...
 444
 445 ---
 446
 447 name:            or_s1_vgpr_undef_vgpr_undef_vgpr
 448 legalized:       true
 449 regBankSelected: true
 450 tracksRegLiveness: true
 451
 452 body: |
 453   bb.0:
 454     ; WAVE64-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr
 455     ; WAVE64: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr
 456     ; WAVE64: S_ENDPGM 0, implicit [[OR]](s1)
 457     ; WAVE32-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr
 458     ; WAVE32: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr
 459     ; WAVE32: S_ENDPGM 0, implicit [[OR]](s1)
 460     %2:vgpr(s1) = G_OR undef %0:vgpr(s1), undef %1:vgpr(s1)
 461     S_ENDPGM 0, implicit %2
 462 ...
 463
 464 ---
 465
 466 name:            or_s1_vcc_copy_to_vcc
 467 legalized:       true
 468 regBankSelected: true
 469 tracksRegLiveness: true
 470
 471 body: |
 472   bb.0:
 473     liveins: $vgpr0, $vgpr1
 474     ; WAVE64-LABEL: name: or_s1_vcc_copy_to_vcc
 475     ; WAVE64: liveins: $vgpr0, $vgpr1
 476     ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 477     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 478     ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
 479     ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
 480     ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
 481     ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
 482     ; WAVE32-LABEL: name: or_s1_vcc_copy_to_vcc
 483     ; WAVE32: liveins: $vgpr0, $vgpr1
 484     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 485     ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 486     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 487     ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
 488     ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
 489     ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
 490     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
 491     %0:vgpr(s32) = COPY $vgpr0
 492     %1:vgpr(s32) = COPY $vgpr1
 493     %2:vgpr(s1) = G_TRUNC %0
 494     %3:vgpr(s1) = G_TRUNC %1
 495     %4:vcc(s1) = COPY %2
 496     %5:vcc(s1) = COPY %3
 497     %6:vcc(s1) = G_OR %4, %5
 498     S_ENDPGM 0, implicit %6
 499 ...
 500
 501 # The selector for the copy of the or result may constrain the result
 502 # register of the or, losing that it is a VCCRegBank context.
 503
 504 # Works for wave32, should fail for wave64
 505 ---
 506 name:            copy_select_constrain_vcc_result_reg_wave32
 507 legalized:       true
 508 regBankSelected: true
 509 tracksRegLiveness: true
 510 body:             |
 511   bb.0:
 512     liveins: $vgpr0
 513
 514     ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
 515     ; WAVE64: liveins: $vgpr0
 516     ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
 517     ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
 518     ; WAVE64: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
 519     ; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
 520     ; WAVE64: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
 521     ; WAVE64: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
 522     ; WAVE64: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
 523     ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_64_xexec(s1) = S_OR_B32 [[COPY1]](s1), [[COPY2]](s1)
 524     ; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0(s1) = COPY [[S_OR_B32_]](s1)
 525     ; WAVE64: S_ENDPGM 0, implicit [[COPY3]](s1)
 526     ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
 527     ; WAVE32: liveins: $vgpr0
 528     ; WAVE32: $vcc_hi = IMPLICIT_DEF
 529     ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 530     ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
 531     ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
 532     ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
 533     ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
 534     ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
 535     %1:vgpr(s32) = COPY $vgpr0
 536     %0:vgpr(s1) = G_TRUNC %1(s32)
 537     %2:sgpr(s1) = G_CONSTANT i1 true
 538     %6:sgpr(s32) = G_CONSTANT i32 0
 539     %7:sgpr(p1) = G_IMPLICIT_DEF
 540     %9:vcc(s1) = COPY %0(s1)
 541     %10:vcc(s1) = COPY %2(s1)
 542     %8:vcc(s1) = G_OR %9, %10
 543     %3:sreg_32_xm0(s1) = COPY %8(s1)
 544     S_ENDPGM 0, implicit %3
 545
 546 ...
 547
 548 # Works for wave64, should fail for wave32
 549 ---
 550 name:            copy_select_constrain_vcc_result_reg_wave64
 551 legalized:       true
 552 regBankSelected: true
 553 tracksRegLiveness: true
 554 body:             |
 555   bb.0:
 556     liveins: $vgpr0
 557
 558     ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
 559     ; WAVE64: liveins: $vgpr0
 560     ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 561     ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
 562     ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
 563     ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
 564     ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
 565     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B64_]]
 566     ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
 567     ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
 568     ; WAVE32: liveins: $vgpr0
 569     ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
 570     ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
 571     ; WAVE32: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
 572     ; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
 573     ; WAVE32: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
 574     ; WAVE32: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
 575     ; WAVE32: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
 576     ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[COPY1]](s1), [[COPY2]](s1)
 577     ; WAVE32: [[COPY3:%[0-9]+]]:sreg_64_xexec(s1) = COPY [[S_OR_B32_]](s1)
 578     ; WAVE32: S_ENDPGM 0, implicit [[COPY3]](s1)
 579     %1:vgpr(s32) = COPY $vgpr0
 580     %0:vgpr(s1) = G_TRUNC %1(s32)
 581     %2:sgpr(s1) = G_CONSTANT i1 true
 582     %6:sgpr(s32) = G_CONSTANT i32 0
 583     %7:sgpr(p1) = G_IMPLICIT_DEF
 584     %9:vcc(s1) = COPY %0(s1)
 585     %10:vcc(s1) = COPY %2(s1)
 586     %8:vcc(s1) = G_OR %9, %10
 587     %3:sreg_64_xexec(s1) = COPY %8(s1)
 588     S_ENDPGM 0, implicit %3
 589
 590 ...