| blob | 7de4f1796b08a34d1810bbf9b1aeeb6b7387a9a0 |
1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
2 ; RUN: llvm-as -data-layout=A5 < %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs | FileCheck --check-prefix=GCN %s
4 declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
5 declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
6 declare i32 @llvm.amdgcn.workitem.id.x()
7 declare i32 @llvm.amdgcn.workgroup.id.x()
8 declare void @llvm.amdgcn.s.barrier()
10 @test_local.temp = internal addrspace(3) global [1 x i32] undef, align 4
11 @test_global_local.temp = internal addrspace(3) global [1 x i32] undef, align 4
13 ; GCN-LABEL: {{^}}test_local
14 ; GCN: v_mov_b32_e32 v[[VAL:[0-9]+]], 0x777
15 ; GCN: ds_write_b32 v{{[0-9]+}}, v[[VAL]]
16 ; GCN: s_waitcnt lgkmcnt(0){{$}}
17 ; GCN-NEXT: s_barrier
18 ; GCN: flat_store_dword
19 define amdgpu_kernel void @test_local(i32 addrspace(1)*) {
20 %2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
21 store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
22 %3 = call i32 @llvm.amdgcn.workitem.id.x()
23 %4 = zext i32 %3 to i64
24 %5 = icmp eq i64 %4, 0
25 br i1 %5, label %6, label %7
27 ; <label>:6: ; preds = %1
28 store i32 1911, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_local.temp, i64 0, i64 0), align 4
29 br label %7
31 ; <label>:7: ; preds = %6, %1
32 fence syncscope("workgroup") release
33 call void @llvm.amdgcn.s.barrier()
34 fence syncscope("workgroup") acquire
35 %8 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_local.temp, i64 0, i64 0), align 4
36 %9 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
37 %10 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
38 %11 = call i32 @llvm.amdgcn.workitem.id.x()
39 %12 = call i32 @llvm.amdgcn.workgroup.id.x()
40 %13 = getelementptr inbounds i8, i8 addrspace(4)* %10, i64 4
41 %14 = bitcast i8 addrspace(4)* %13 to i16 addrspace(4)*
42 %15 = load i16, i16 addrspace(4)* %14, align 4
43 %16 = zext i16 %15 to i32
44 %17 = mul i32 %12, %16
45 %18 = add i32 %17, %11
46 %19 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
47 %20 = zext i32 %18 to i64
48 %21 = bitcast i8 addrspace(4)* %19 to i64 addrspace(4)*
49 %22 = load i64, i64 addrspace(4)* %21, align 8
50 %23 = add i64 %22, %20
51 %24 = getelementptr inbounds i32, i32 addrspace(1)* %9, i64 %23
52 store i32 %8, i32 addrspace(1)* %24, align 4
53 ret void
54 }
56 ; GCN-LABEL: {{^}}test_global
57 ; GCN: s_movk_i32 [[K:s[0-9]+]], 0x888
58 ; GCN: v_add_u32_e32 v{{[0-9]+}}, vcc, [[K]], v{{[0-9]+}}
59 ; GCN: flat_store_dword
60 ; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
61 ; GCN-NEXT: s_barrier
62 define amdgpu_kernel void @test_global(i32 addrspace(1)*) {
63 %2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
64 %3 = alloca i32, align 4, addrspace(5)
65 store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
66 store i32 0, i32 addrspace(5)* %3, align 4
67 br label %4
69 ; <label>:4: ; preds = %58, %1
70 %5 = load i32, i32 addrspace(5)* %3, align 4
71 %6 = sext i32 %5 to i64
72 %7 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
73 %8 = call i32 @llvm.amdgcn.workitem.id.x()
74 %9 = call i32 @llvm.amdgcn.workgroup.id.x()
75 %10 = getelementptr inbounds i8, i8 addrspace(4)* %7, i64 4
76 %11 = bitcast i8 addrspace(4)* %10 to i16 addrspace(4)*
77 %12 = load i16, i16 addrspace(4)* %11, align 4
78 %13 = zext i16 %12 to i32
79 %14 = mul i32 %9, %13
80 %15 = add i32 %14, %8
81 %16 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
82 %17 = zext i32 %15 to i64
83 %18 = bitcast i8 addrspace(4)* %16 to i64 addrspace(4)*
84 %19 = load i64, i64 addrspace(4)* %18, align 8
85 %20 = add i64 %19, %17
86 %21 = icmp ult i64 %6, %20
87 br i1 %21, label %22, label %61
89 ; <label>:22: ; preds = %4
90 %23 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
91 %24 = call i32 @llvm.amdgcn.workitem.id.x()
92 %25 = call i32 @llvm.amdgcn.workgroup.id.x()
93 %26 = getelementptr inbounds i8, i8 addrspace(4)* %23, i64 4
94 %27 = bitcast i8 addrspace(4)* %26 to i16 addrspace(4)*
95 %28 = load i16, i16 addrspace(4)* %27, align 4
96 %29 = zext i16 %28 to i32
97 %30 = mul i32 %25, %29
98 %31 = add i32 %30, %24
99 %32 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
100 %33 = zext i32 %31 to i64
101 %34 = bitcast i8 addrspace(4)* %32 to i64 addrspace(4)*
102 %35 = load i64, i64 addrspace(4)* %34, align 8
103 %36 = add i64 %35, %33
104 %37 = add i64 %36, 2184
105 %38 = trunc i64 %37 to i32
106 %39 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
107 %40 = load i32, i32 addrspace(5)* %3, align 4
108 %41 = sext i32 %40 to i64
109 %42 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
110 %43 = call i32 @llvm.amdgcn.workitem.id.x()
111 %44 = call i32 @llvm.amdgcn.workgroup.id.x()
112 %45 = getelementptr inbounds i8, i8 addrspace(4)* %42, i64 4
113 %46 = bitcast i8 addrspace(4)* %45 to i16 addrspace(4)*
114 %47 = load i16, i16 addrspace(4)* %46, align 4
115 %48 = zext i16 %47 to i32
116 %49 = mul i32 %44, %48
117 %50 = add i32 %49, %43
118 %51 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
119 %52 = zext i32 %50 to i64
120 %53 = bitcast i8 addrspace(4)* %51 to i64 addrspace(4)*
121 %54 = load i64, i64 addrspace(4)* %53, align 8
122 %55 = add i64 %54, %52
123 %56 = add i64 %41, %55
124 %57 = getelementptr inbounds i32, i32 addrspace(1)* %39, i64 %56
125 store i32 %38, i32 addrspace(1)* %57, align 4
126 fence syncscope("workgroup") release
127 call void @llvm.amdgcn.s.barrier()
128 fence syncscope("workgroup") acquire
129 br label %58
131 ; <label>:58: ; preds = %22
132 %59 = load i32, i32 addrspace(5)* %3, align 4
133 %60 = add nsw i32 %59, 1
134 store i32 %60, i32 addrspace(5)* %3, align 4
135 br label %4
137 ; <label>:61: ; preds = %4
138 ret void
139 }
141 ; GCN-LABEL: {{^}}test_global_local
142 ; GCN: v_mov_b32_e32 v[[VAL:[0-9]+]], 0x999
143 ; GCN: ds_write_b32 v{{[0-9]+}}, v[[VAL]]
144 ; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
145 ; GCN-NEXT: s_barrier
146 ; GCN: flat_store_dword
147 define amdgpu_kernel void @test_global_local(i32 addrspace(1)*) {
148 %2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
149 store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
150 %3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
151 %4 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
152 %5 = call i32 @llvm.amdgcn.workitem.id.x()
153 %6 = call i32 @llvm.amdgcn.workgroup.id.x()
154 %7 = getelementptr inbounds i8, i8 addrspace(4)* %4, i64 4
155 %8 = bitcast i8 addrspace(4)* %7 to i16 addrspace(4)*
156 %9 = load i16, i16 addrspace(4)* %8, align 4
157 %10 = zext i16 %9 to i32
158 %11 = mul i32 %6, %10
159 %12 = add i32 %11, %5
160 %13 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
161 %14 = zext i32 %12 to i64
162 %15 = bitcast i8 addrspace(4)* %13 to i64 addrspace(4)*
163 %16 = load i64, i64 addrspace(4)* %15, align 8
164 %17 = add i64 %16, %14
165 %18 = getelementptr inbounds i32, i32 addrspace(1)* %3, i64 %17
166 store i32 1, i32 addrspace(1)* %18, align 4
167 %19 = call i32 @llvm.amdgcn.workitem.id.x()
168 %20 = zext i32 %19 to i64
169 %21 = icmp eq i64 %20, 0
170 br i1 %21, label %22, label %23
172 ; <label>:22: ; preds = %1
173 store i32 2457, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_global_local.temp, i64 0, i64 0), align 4
174 br label %23
176 ; <label>:23: ; preds = %22, %1
177 fence syncscope("workgroup") release
178 call void @llvm.amdgcn.s.barrier()
179 fence syncscope("workgroup") acquire
180 %24 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_global_local.temp, i64 0, i64 0), align 4
181 %25 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
182 %26 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
183 %27 = call i32 @llvm.amdgcn.workitem.id.x()
184 %28 = call i32 @llvm.amdgcn.workgroup.id.x()
185 %29 = getelementptr inbounds i8, i8 addrspace(4)* %26, i64 4
186 %30 = bitcast i8 addrspace(4)* %29 to i16 addrspace(4)*
187 %31 = load i16, i16 addrspace(4)* %30, align 4
188 %32 = zext i16 %31 to i32
189 %33 = mul i32 %28, %32
190 %34 = add i32 %33, %27
191 %35 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
192 %36 = zext i32 %34 to i64
193 %37 = bitcast i8 addrspace(4)* %35 to i64 addrspace(4)*
194 %38 = load i64, i64 addrspace(4)* %37, align 8
195 %39 = add i64 %38, %36
196 %40 = getelementptr inbounds i32, i32 addrspace(1)* %25, i64 %39
197 store i32 %24, i32 addrspace(1)* %40, align 4
198 ret void
199 }