1 ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2 ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
4 ; SI-LABEL: {{^}}i1_copy_from_loop:
7 ; SI: v_cmp_gt_u32_e64 [[CC_SREG:s\[[0-9]+:[0-9]+\]]], 4,
8 ; SI-DAG: s_andn2_b64 [[CC_ACCUM:s\[[0-9]+:[0-9]+\]]], [[CC_ACCUM]], exec
9 ; SI-DAG: s_and_b64 [[CC_MASK:s\[[0-9]+:[0-9]+\]]], [[CC_SREG]], exec
10 ; SI: s_or_b64 [[CC_ACCUM]], [[CC_ACCUM]], [[CC_MASK]]
13 ; SI: s_or_b64 [[CC_ACCUM]], [[CC_ACCUM]], exec
16 ; SI-DAG: s_andn2_b64 [[LCSSA_ACCUM:s\[[0-9]+:[0-9]+\]]], [[LCSSA_ACCUM]], exec
17 ; SI-DAG: s_and_b64 [[CC_MASK2:s\[[0-9]+:[0-9]+\]]], [[CC_ACCUM]], exec
18 ; SI: s_or_b64 [[LCSSA_ACCUM]], [[LCSSA_ACCUM]], [[CC_MASK2]]
21 ; SI: s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[LCSSA_ACCUM]]
23 define amdgpu_ps void @i1_copy_from_loop(<4 x i32> inreg %rsrc, i32 %tid) {
28 %i = phi i32 [0, %entry], [%i.inc, %end.loop]
29 %cc = icmp ult i32 %i, 4
30 br i1 %cc, label %mid.loop, label %for.end
33 %v = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %tid, i32 %i, i1 false, i1 false)
34 %cc2 = fcmp oge float %v, 0.0
35 br i1 %cc2, label %end.loop, label %for.end
38 %i.inc = add i32 %i, 1
42 br i1 %cc, label %if, label %end
45 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float undef, float undef, float undef, float undef, i1 true, i1 true)
52 declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
53 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
55 attributes #0 = { nounwind readonly }
56 attributes #1 = { nounwind inaccessiblememonly }