1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
4 define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {
5 ; CHECK-LABEL: cmpeqz_v4i1:
6 ; CHECK: @ %bb.0: @ %entry
7 ; CHECK-NEXT: vorr q2, q0, q1
8 ; CHECK-NEXT: vcmp.i32 eq, q2, zr
9 ; CHECK-NEXT: vpsel q0, q0, q1
12 %c1 = icmp eq <4 x i32> %a, zeroinitializer
13 %c2 = icmp eq <4 x i32> %b, zeroinitializer
14 %o = and <4 x i1> %c1, %c2
15 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
19 define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {
20 ; CHECK-LABEL: cmpnez_v4i1:
21 ; CHECK: @ %bb.0: @ %entry
22 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
24 ; CHECK-NEXT: vcmpt.i32 ne, q1, zr
25 ; CHECK-NEXT: vpsel q0, q0, q1
28 %c1 = icmp eq <4 x i32> %a, zeroinitializer
29 %c2 = icmp ne <4 x i32> %b, zeroinitializer
30 %o = and <4 x i1> %c1, %c2
31 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
35 define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {
36 ; CHECK-LABEL: cmpsltz_v4i1:
37 ; CHECK: @ %bb.0: @ %entry
38 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
40 ; CHECK-NEXT: vcmpt.s32 lt, q1, zr
41 ; CHECK-NEXT: vpsel q0, q0, q1
44 %c1 = icmp eq <4 x i32> %a, zeroinitializer
45 %c2 = icmp slt <4 x i32> %b, zeroinitializer
46 %o = and <4 x i1> %c1, %c2
47 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
51 define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
52 ; CHECK-LABEL: cmpsgtz_v4i1:
53 ; CHECK: @ %bb.0: @ %entry
54 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
56 ; CHECK-NEXT: vcmpt.s32 gt, q1, zr
57 ; CHECK-NEXT: vpsel q0, q0, q1
60 %c1 = icmp eq <4 x i32> %a, zeroinitializer
61 %c2 = icmp sgt <4 x i32> %b, zeroinitializer
62 %o = and <4 x i1> %c1, %c2
63 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
67 define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {
68 ; CHECK-LABEL: cmpslez_v4i1:
69 ; CHECK: @ %bb.0: @ %entry
70 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
72 ; CHECK-NEXT: vcmpt.s32 le, q1, zr
73 ; CHECK-NEXT: vpsel q0, q0, q1
76 %c1 = icmp eq <4 x i32> %a, zeroinitializer
77 %c2 = icmp sle <4 x i32> %b, zeroinitializer
78 %o = and <4 x i1> %c1, %c2
79 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
83 define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {
84 ; CHECK-LABEL: cmpsgez_v4i1:
85 ; CHECK: @ %bb.0: @ %entry
86 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
88 ; CHECK-NEXT: vcmpt.s32 ge, q1, zr
89 ; CHECK-NEXT: vpsel q0, q0, q1
92 %c1 = icmp eq <4 x i32> %a, zeroinitializer
93 %c2 = icmp sge <4 x i32> %b, zeroinitializer
94 %o = and <4 x i1> %c1, %c2
95 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
99 define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {
100 ; CHECK-LABEL: cmpultz_v4i1:
101 ; CHECK: @ %bb.0: @ %entry
102 ; CHECK-NEXT: vmov q0, q1
105 %c1 = icmp eq <4 x i32> %a, zeroinitializer
106 %c2 = icmp ult <4 x i32> %b, zeroinitializer
107 %o = and <4 x i1> %c1, %c2
108 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
112 define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
113 ; CHECK-LABEL: cmpugtz_v4i1:
114 ; CHECK: @ %bb.0: @ %entry
115 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
117 ; CHECK-NEXT: vcmpt.i32 ne, q1, zr
118 ; CHECK-NEXT: vpsel q0, q0, q1
121 %c1 = icmp eq <4 x i32> %a, zeroinitializer
122 %c2 = icmp ugt <4 x i32> %b, zeroinitializer
123 %o = and <4 x i1> %c1, %c2
124 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
128 define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
129 ; CHECK-LABEL: cmpulez_v4i1:
130 ; CHECK: @ %bb.0: @ %entry
131 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
133 ; CHECK-NEXT: vcmpt.u32 cs, q1, zr
134 ; CHECK-NEXT: vpsel q0, q0, q1
137 %c1 = icmp eq <4 x i32> %a, zeroinitializer
138 %c2 = icmp ule <4 x i32> %b, zeroinitializer
139 %o = and <4 x i1> %c1, %c2
140 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
144 define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {
145 ; CHECK-LABEL: cmpugez_v4i1:
146 ; CHECK: @ %bb.0: @ %entry
147 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
148 ; CHECK-NEXT: vpsel q0, q0, q1
151 %c1 = icmp eq <4 x i32> %a, zeroinitializer
152 %c2 = icmp uge <4 x i32> %b, zeroinitializer
153 %o = and <4 x i1> %c1, %c2
154 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
160 define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
161 ; CHECK-LABEL: cmpeq_v4i1:
162 ; CHECK: @ %bb.0: @ %entry
163 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
165 ; CHECK-NEXT: vcmpt.i32 eq, q1, q2
166 ; CHECK-NEXT: vpsel q0, q0, q1
169 %c1 = icmp eq <4 x i32> %a, zeroinitializer
170 %c2 = icmp eq <4 x i32> %b, %c
171 %o = and <4 x i1> %c1, %c2
172 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
176 define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
177 ; CHECK-LABEL: cmpne_v4i1:
178 ; CHECK: @ %bb.0: @ %entry
179 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
181 ; CHECK-NEXT: vcmpt.i32 ne, q1, q2
182 ; CHECK-NEXT: vpsel q0, q0, q1
185 %c1 = icmp eq <4 x i32> %a, zeroinitializer
186 %c2 = icmp ne <4 x i32> %b, %c
187 %o = and <4 x i1> %c1, %c2
188 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
192 define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
193 ; CHECK-LABEL: cmpslt_v4i1:
194 ; CHECK: @ %bb.0: @ %entry
195 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
197 ; CHECK-NEXT: vcmpt.s32 gt, q2, q1
198 ; CHECK-NEXT: vpsel q0, q0, q1
201 %c1 = icmp eq <4 x i32> %a, zeroinitializer
202 %c2 = icmp slt <4 x i32> %b, %c
203 %o = and <4 x i1> %c1, %c2
204 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
208 define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
209 ; CHECK-LABEL: cmpsgt_v4i1:
210 ; CHECK: @ %bb.0: @ %entry
211 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
213 ; CHECK-NEXT: vcmpt.s32 gt, q1, q2
214 ; CHECK-NEXT: vpsel q0, q0, q1
217 %c1 = icmp eq <4 x i32> %a, zeroinitializer
218 %c2 = icmp sgt <4 x i32> %b, %c
219 %o = and <4 x i1> %c1, %c2
220 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
224 define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
225 ; CHECK-LABEL: cmpsle_v4i1:
226 ; CHECK: @ %bb.0: @ %entry
227 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
229 ; CHECK-NEXT: vcmpt.s32 ge, q2, q1
230 ; CHECK-NEXT: vpsel q0, q0, q1
233 %c1 = icmp eq <4 x i32> %a, zeroinitializer
234 %c2 = icmp sle <4 x i32> %b, %c
235 %o = and <4 x i1> %c1, %c2
236 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
240 define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
241 ; CHECK-LABEL: cmpsge_v4i1:
242 ; CHECK: @ %bb.0: @ %entry
243 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
245 ; CHECK-NEXT: vcmpt.s32 ge, q1, q2
246 ; CHECK-NEXT: vpsel q0, q0, q1
249 %c1 = icmp eq <4 x i32> %a, zeroinitializer
250 %c2 = icmp sge <4 x i32> %b, %c
251 %o = and <4 x i1> %c1, %c2
252 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
256 define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
257 ; CHECK-LABEL: cmpult_v4i1:
258 ; CHECK: @ %bb.0: @ %entry
259 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
261 ; CHECK-NEXT: vcmpt.u32 hi, q2, q1
262 ; CHECK-NEXT: vpsel q0, q0, q1
265 %c1 = icmp eq <4 x i32> %a, zeroinitializer
266 %c2 = icmp ult <4 x i32> %b, %c
267 %o = and <4 x i1> %c1, %c2
268 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
272 define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
273 ; CHECK-LABEL: cmpugt_v4i1:
274 ; CHECK: @ %bb.0: @ %entry
275 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
277 ; CHECK-NEXT: vcmpt.u32 hi, q1, q2
278 ; CHECK-NEXT: vpsel q0, q0, q1
281 %c1 = icmp eq <4 x i32> %a, zeroinitializer
282 %c2 = icmp ugt <4 x i32> %b, %c
283 %o = and <4 x i1> %c1, %c2
284 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
288 define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
289 ; CHECK-LABEL: cmpule_v4i1:
290 ; CHECK: @ %bb.0: @ %entry
291 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
293 ; CHECK-NEXT: vcmpt.u32 cs, q2, q1
294 ; CHECK-NEXT: vpsel q0, q0, q1
297 %c1 = icmp eq <4 x i32> %a, zeroinitializer
298 %c2 = icmp ule <4 x i32> %b, %c
299 %o = and <4 x i1> %c1, %c2
300 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
304 define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
305 ; CHECK-LABEL: cmpuge_v4i1:
306 ; CHECK: @ %bb.0: @ %entry
307 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
309 ; CHECK-NEXT: vcmpt.u32 cs, q1, q2
310 ; CHECK-NEXT: vpsel q0, q0, q1
313 %c1 = icmp eq <4 x i32> %a, zeroinitializer
314 %c2 = icmp uge <4 x i32> %b, %c
315 %o = and <4 x i1> %c1, %c2
316 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
321 define arm_aapcs_vfpcc <4 x i32> @cmpeqr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
322 ; CHECK-LABEL: cmpeqr_v4i1:
323 ; CHECK: @ %bb.0: @ %entry
324 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
326 ; CHECK-NEXT: vcmpt.i32 eq, q1, r0
327 ; CHECK-NEXT: vpsel q0, q0, q1
330 %c1 = icmp eq <4 x i32> %a, zeroinitializer
331 %i = insertelement <4 x i32> undef, i32 %c, i32 0
332 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
333 %c2 = icmp eq <4 x i32> %b, %sp
334 %o = and <4 x i1> %c1, %c2
335 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
339 define arm_aapcs_vfpcc <4 x i32> @cmpner_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
340 ; CHECK-LABEL: cmpner_v4i1:
341 ; CHECK: @ %bb.0: @ %entry
342 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
344 ; CHECK-NEXT: vcmpt.i32 ne, q1, r0
345 ; CHECK-NEXT: vpsel q0, q0, q1
348 %c1 = icmp eq <4 x i32> %a, zeroinitializer
349 %i = insertelement <4 x i32> undef, i32 %c, i32 0
350 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
351 %c2 = icmp ne <4 x i32> %b, %sp
352 %o = and <4 x i1> %c1, %c2
353 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
357 define arm_aapcs_vfpcc <4 x i32> @cmpsltr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
358 ; CHECK-LABEL: cmpsltr_v4i1:
359 ; CHECK: @ %bb.0: @ %entry
360 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
361 ; CHECK-NEXT: vdup.32 q2, r0
363 ; CHECK-NEXT: vcmpt.s32 gt, q2, q1
364 ; CHECK-NEXT: vpsel q0, q0, q1
367 %c1 = icmp eq <4 x i32> %a, zeroinitializer
368 %i = insertelement <4 x i32> undef, i32 %c, i32 0
369 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
370 %c2 = icmp slt <4 x i32> %b, %sp
371 %o = and <4 x i1> %c1, %c2
372 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
376 define arm_aapcs_vfpcc <4 x i32> @cmpsgtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
377 ; CHECK-LABEL: cmpsgtr_v4i1:
378 ; CHECK: @ %bb.0: @ %entry
379 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
381 ; CHECK-NEXT: vcmpt.s32 gt, q1, r0
382 ; CHECK-NEXT: vpsel q0, q0, q1
385 %c1 = icmp eq <4 x i32> %a, zeroinitializer
386 %i = insertelement <4 x i32> undef, i32 %c, i32 0
387 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
388 %c2 = icmp sgt <4 x i32> %b, %sp
389 %o = and <4 x i1> %c1, %c2
390 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
394 define arm_aapcs_vfpcc <4 x i32> @cmpsler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
395 ; CHECK-LABEL: cmpsler_v4i1:
396 ; CHECK: @ %bb.0: @ %entry
397 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
398 ; CHECK-NEXT: vdup.32 q2, r0
400 ; CHECK-NEXT: vcmpt.s32 ge, q2, q1
401 ; CHECK-NEXT: vpsel q0, q0, q1
404 %c1 = icmp eq <4 x i32> %a, zeroinitializer
405 %i = insertelement <4 x i32> undef, i32 %c, i32 0
406 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
407 %c2 = icmp sle <4 x i32> %b, %sp
408 %o = and <4 x i1> %c1, %c2
409 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
413 define arm_aapcs_vfpcc <4 x i32> @cmpsger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
414 ; CHECK-LABEL: cmpsger_v4i1:
415 ; CHECK: @ %bb.0: @ %entry
416 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
418 ; CHECK-NEXT: vcmpt.s32 ge, q1, r0
419 ; CHECK-NEXT: vpsel q0, q0, q1
422 %c1 = icmp eq <4 x i32> %a, zeroinitializer
423 %i = insertelement <4 x i32> undef, i32 %c, i32 0
424 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
425 %c2 = icmp sge <4 x i32> %b, %sp
426 %o = and <4 x i1> %c1, %c2
427 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
431 define arm_aapcs_vfpcc <4 x i32> @cmpultr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
432 ; CHECK-LABEL: cmpultr_v4i1:
433 ; CHECK: @ %bb.0: @ %entry
434 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
435 ; CHECK-NEXT: vdup.32 q2, r0
437 ; CHECK-NEXT: vcmpt.u32 hi, q2, q1
438 ; CHECK-NEXT: vpsel q0, q0, q1
441 %c1 = icmp eq <4 x i32> %a, zeroinitializer
442 %i = insertelement <4 x i32> undef, i32 %c, i32 0
443 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
444 %c2 = icmp ult <4 x i32> %b, %sp
445 %o = and <4 x i1> %c1, %c2
446 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
450 define arm_aapcs_vfpcc <4 x i32> @cmpugtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
451 ; CHECK-LABEL: cmpugtr_v4i1:
452 ; CHECK: @ %bb.0: @ %entry
453 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
455 ; CHECK-NEXT: vcmpt.u32 hi, q1, r0
456 ; CHECK-NEXT: vpsel q0, q0, q1
459 %c1 = icmp eq <4 x i32> %a, zeroinitializer
460 %i = insertelement <4 x i32> undef, i32 %c, i32 0
461 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
462 %c2 = icmp ugt <4 x i32> %b, %sp
463 %o = and <4 x i1> %c1, %c2
464 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
468 define arm_aapcs_vfpcc <4 x i32> @cmpuler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
469 ; CHECK-LABEL: cmpuler_v4i1:
470 ; CHECK: @ %bb.0: @ %entry
471 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
472 ; CHECK-NEXT: vdup.32 q2, r0
474 ; CHECK-NEXT: vcmpt.u32 cs, q2, q1
475 ; CHECK-NEXT: vpsel q0, q0, q1
478 %c1 = icmp eq <4 x i32> %a, zeroinitializer
479 %i = insertelement <4 x i32> undef, i32 %c, i32 0
480 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
481 %c2 = icmp ule <4 x i32> %b, %sp
482 %o = and <4 x i1> %c1, %c2
483 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
487 define arm_aapcs_vfpcc <4 x i32> @cmpuger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
488 ; CHECK-LABEL: cmpuger_v4i1:
489 ; CHECK: @ %bb.0: @ %entry
490 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
492 ; CHECK-NEXT: vcmpt.u32 cs, q1, r0
493 ; CHECK-NEXT: vpsel q0, q0, q1
496 %c1 = icmp eq <4 x i32> %a, zeroinitializer
497 %i = insertelement <4 x i32> undef, i32 %c, i32 0
498 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
499 %c2 = icmp uge <4 x i32> %b, %sp
500 %o = and <4 x i1> %c1, %c2
501 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
507 define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {
508 ; CHECK-LABEL: cmpeqz_v8i1:
509 ; CHECK: @ %bb.0: @ %entry
510 ; CHECK-NEXT: vorr q2, q0, q1
511 ; CHECK-NEXT: vcmp.i16 eq, q2, zr
512 ; CHECK-NEXT: vpsel q0, q0, q1
515 %c1 = icmp eq <8 x i16> %a, zeroinitializer
516 %c2 = icmp eq <8 x i16> %b, zeroinitializer
517 %o = and <8 x i1> %c1, %c2
518 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
522 define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
523 ; CHECK-LABEL: cmpeq_v8i1:
524 ; CHECK: @ %bb.0: @ %entry
525 ; CHECK-NEXT: vcmp.i16 eq, q0, zr
527 ; CHECK-NEXT: vcmpt.i16 eq, q1, q2
528 ; CHECK-NEXT: vpsel q0, q0, q1
531 %c1 = icmp eq <8 x i16> %a, zeroinitializer
532 %c2 = icmp eq <8 x i16> %b, %c
533 %o = and <8 x i1> %c1, %c2
534 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
538 define arm_aapcs_vfpcc <8 x i16> @cmpeqr_v8i1(<8 x i16> %a, <8 x i16> %b, i16 %c) {
539 ; CHECK-LABEL: cmpeqr_v8i1:
540 ; CHECK: @ %bb.0: @ %entry
541 ; CHECK-NEXT: vcmp.i16 eq, q0, zr
543 ; CHECK-NEXT: vcmpt.i16 eq, q1, r0
544 ; CHECK-NEXT: vpsel q0, q0, q1
547 %c1 = icmp eq <8 x i16> %a, zeroinitializer
548 %i = insertelement <8 x i16> undef, i16 %c, i32 0
549 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
550 %c2 = icmp eq <8 x i16> %b, %sp
551 %o = and <8 x i1> %c1, %c2
552 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
557 define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {
558 ; CHECK-LABEL: cmpeqz_v16i1:
559 ; CHECK: @ %bb.0: @ %entry
560 ; CHECK-NEXT: vorr q2, q0, q1
561 ; CHECK-NEXT: vcmp.i8 eq, q2, zr
562 ; CHECK-NEXT: vpsel q0, q0, q1
565 %c1 = icmp eq <16 x i8> %a, zeroinitializer
566 %c2 = icmp eq <16 x i8> %b, zeroinitializer
567 %o = and <16 x i1> %c1, %c2
568 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
572 define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
573 ; CHECK-LABEL: cmpeq_v16i1:
574 ; CHECK: @ %bb.0: @ %entry
575 ; CHECK-NEXT: vcmp.i8 eq, q0, zr
577 ; CHECK-NEXT: vcmpt.i8 eq, q1, q2
578 ; CHECK-NEXT: vpsel q0, q0, q1
581 %c1 = icmp eq <16 x i8> %a, zeroinitializer
582 %c2 = icmp eq <16 x i8> %b, %c
583 %o = and <16 x i1> %c1, %c2
584 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
588 define arm_aapcs_vfpcc <16 x i8> @cmpeqr_v16i1(<16 x i8> %a, <16 x i8> %b, i8 %c) {
589 ; CHECK-LABEL: cmpeqr_v16i1:
590 ; CHECK: @ %bb.0: @ %entry
591 ; CHECK-NEXT: vcmp.i8 eq, q0, zr
593 ; CHECK-NEXT: vcmpt.i8 eq, q1, r0
594 ; CHECK-NEXT: vpsel q0, q0, q1
597 %c1 = icmp eq <16 x i8> %a, zeroinitializer
598 %i = insertelement <16 x i8> undef, i8 %c, i32 0
599 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
600 %c2 = icmp eq <16 x i8> %b, %sp
601 %o = and <16 x i1> %c1, %c2
602 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
607 define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
608 ; CHECK-LABEL: cmpeqz_v2i1:
609 ; CHECK: @ %bb.0: @ %entry
610 ; CHECK-NEXT: vorr q2, q0, q1
611 ; CHECK-NEXT: vmov r0, s9
612 ; CHECK-NEXT: vmov r1, s8
613 ; CHECK-NEXT: orrs r0, r1
614 ; CHECK-NEXT: vmov r1, s10
615 ; CHECK-NEXT: clz r0, r0
616 ; CHECK-NEXT: lsrs r0, r0, #5
618 ; CHECK-NEXT: movne.w r0, #-1
619 ; CHECK-NEXT: vmov.32 q3[0], r0
620 ; CHECK-NEXT: vmov.32 q3[1], r0
621 ; CHECK-NEXT: vmov r0, s11
622 ; CHECK-NEXT: orrs r0, r1
623 ; CHECK-NEXT: clz r0, r0
624 ; CHECK-NEXT: lsrs r0, r0, #5
626 ; CHECK-NEXT: movne.w r0, #-1
627 ; CHECK-NEXT: vmov.32 q3[2], r0
628 ; CHECK-NEXT: vmov.32 q3[3], r0
629 ; CHECK-NEXT: vbic q1, q1, q3
630 ; CHECK-NEXT: vand q0, q0, q3
631 ; CHECK-NEXT: vorr q0, q0, q1
634 %c1 = icmp eq <2 x i64> %a, zeroinitializer
635 %c2 = icmp eq <2 x i64> %b, zeroinitializer
636 %o = and <2 x i1> %c1, %c2
637 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
641 define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
642 ; CHECK-LABEL: cmpeq_v2i1:
643 ; CHECK: @ %bb.0: @ %entry
644 ; CHECK-NEXT: vmov r0, s9
645 ; CHECK-NEXT: vmov r1, s5
646 ; CHECK-NEXT: vmov r2, s4
647 ; CHECK-NEXT: eors r0, r1
648 ; CHECK-NEXT: vmov r1, s8
649 ; CHECK-NEXT: eors r1, r2
650 ; CHECK-NEXT: vmov r2, s6
651 ; CHECK-NEXT: orrs r0, r1
652 ; CHECK-NEXT: vmov r1, s7
653 ; CHECK-NEXT: clz r0, r0
654 ; CHECK-NEXT: lsrs r0, r0, #5
656 ; CHECK-NEXT: movne.w r0, #-1
657 ; CHECK-NEXT: vmov.32 q3[0], r0
658 ; CHECK-NEXT: vmov.32 q3[1], r0
659 ; CHECK-NEXT: vmov r0, s11
660 ; CHECK-NEXT: eors r0, r1
661 ; CHECK-NEXT: vmov r1, s10
662 ; CHECK-NEXT: eors r1, r2
663 ; CHECK-NEXT: orrs r0, r1
664 ; CHECK-NEXT: vmov r1, s0
665 ; CHECK-NEXT: clz r0, r0
666 ; CHECK-NEXT: lsrs r0, r0, #5
668 ; CHECK-NEXT: movne.w r0, #-1
669 ; CHECK-NEXT: vmov.32 q3[2], r0
670 ; CHECK-NEXT: vmov.32 q3[3], r0
671 ; CHECK-NEXT: vmov r0, s1
672 ; CHECK-NEXT: orrs r0, r1
673 ; CHECK-NEXT: vmov r1, s2
674 ; CHECK-NEXT: clz r0, r0
675 ; CHECK-NEXT: lsrs r0, r0, #5
677 ; CHECK-NEXT: movne.w r0, #-1
678 ; CHECK-NEXT: vmov.32 q2[0], r0
679 ; CHECK-NEXT: vmov.32 q2[1], r0
680 ; CHECK-NEXT: vmov r0, s3
681 ; CHECK-NEXT: orrs r0, r1
682 ; CHECK-NEXT: clz r0, r0
683 ; CHECK-NEXT: lsrs r0, r0, #5
685 ; CHECK-NEXT: movne.w r0, #-1
686 ; CHECK-NEXT: vmov.32 q2[2], r0
687 ; CHECK-NEXT: vmov.32 q2[3], r0
688 ; CHECK-NEXT: vand q2, q2, q3
689 ; CHECK-NEXT: vbic q1, q1, q2
690 ; CHECK-NEXT: vand q0, q0, q2
691 ; CHECK-NEXT: vorr q0, q0, q1
694 %c1 = icmp eq <2 x i64> %a, zeroinitializer
695 %c2 = icmp eq <2 x i64> %b, %c
696 %o = and <2 x i1> %c1, %c2
697 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
701 define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c) {
702 ; CHECK-LABEL: cmpeqr_v2i1:
703 ; CHECK: @ %bb.0: @ %entry
704 ; CHECK-NEXT: vmov r2, s5
705 ; CHECK-NEXT: vmov r3, s4
706 ; CHECK-NEXT: eors r2, r1
707 ; CHECK-NEXT: eors r3, r0
708 ; CHECK-NEXT: orrs r2, r3
709 ; CHECK-NEXT: clz r2, r2
710 ; CHECK-NEXT: lsrs r2, r2, #5
712 ; CHECK-NEXT: movne.w r2, #-1
713 ; CHECK-NEXT: vmov.32 q2[0], r2
714 ; CHECK-NEXT: vmov.32 q2[1], r2
715 ; CHECK-NEXT: vmov r2, s7
716 ; CHECK-NEXT: eors r1, r2
717 ; CHECK-NEXT: vmov r2, s6
718 ; CHECK-NEXT: eors r0, r2
719 ; CHECK-NEXT: orrs r0, r1
720 ; CHECK-NEXT: vmov r1, s0
721 ; CHECK-NEXT: clz r0, r0
722 ; CHECK-NEXT: lsrs r0, r0, #5
724 ; CHECK-NEXT: movne.w r0, #-1
725 ; CHECK-NEXT: vmov.32 q2[2], r0
726 ; CHECK-NEXT: vmov.32 q2[3], r0
727 ; CHECK-NEXT: vmov r0, s1
728 ; CHECK-NEXT: orrs r0, r1
729 ; CHECK-NEXT: vmov r1, s2
730 ; CHECK-NEXT: clz r0, r0
731 ; CHECK-NEXT: lsrs r0, r0, #5
733 ; CHECK-NEXT: movne.w r0, #-1
734 ; CHECK-NEXT: vmov.32 q3[0], r0
735 ; CHECK-NEXT: vmov.32 q3[1], r0
736 ; CHECK-NEXT: vmov r0, s3
737 ; CHECK-NEXT: orrs r0, r1
738 ; CHECK-NEXT: clz r0, r0
739 ; CHECK-NEXT: lsrs r0, r0, #5
741 ; CHECK-NEXT: movne.w r0, #-1
742 ; CHECK-NEXT: vmov.32 q3[2], r0
743 ; CHECK-NEXT: vmov.32 q3[3], r0
744 ; CHECK-NEXT: vand q2, q3, q2
745 ; CHECK-NEXT: vbic q1, q1, q2
746 ; CHECK-NEXT: vand q0, q0, q2
747 ; CHECK-NEXT: vorr q0, q0, q1
750 %c1 = icmp eq <2 x i64> %a, zeroinitializer
751 %i = insertelement <2 x i64> undef, i64 %c, i32 0
752 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
753 %c2 = icmp eq <2 x i64> %b, %sp
754 %o = and <2 x i1> %c1, %c2
755 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b