[llvm-objdump] - Remove one overload of reportError. NFCI.
[llvm-complete.git] / test / MC / AArch64 / SVE2 / sqshl-diagnostics.s
blob1f78eaf08460877f13ad020128b02e64446696e9
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
3 sqshl z0.b, p0/m, z0.b, #-1
4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
5 // CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #-1
6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8 sqshl z0.b, p0/m, z0.b, #8
9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
10 // CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #8
11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
13 sqshl z0.h, p0/m, z0.h, #-1
14 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
15 // CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #-1
16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18 sqshl z0.h, p0/m, z0.h, #16
19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
20 // CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #16
21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23 sqshl z0.s, p0/m, z0.s, #-1
24 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
25 // CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #-1
26 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
28 sqshl z0.s, p0/m, z0.s, #32
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
30 // CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #32
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33 sqshl z0.d, p0/m, z0.d, #-1
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
35 // CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #-1
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38 sqshl z0.d, p0/m, z0.d, #64
39 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
40 // CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #64
41 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
44 // --------------------------------------------------------------------------//
45 // Source and Destination Registers must match
47 sqshl z0.b, p0/m, z1.b, z2.b
48 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
49 // CHECK-NEXT: sqshl z0.b, p0/m, z1.b, z2.b
50 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
52 sqshl z0.b, p0/m, z1.b, #0
53 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
54 // CHECK-NEXT: sqshl z0.b, p0/m, z1.b, #0
55 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
58 // --------------------------------------------------------------------------//
59 // Element sizes must match
61 sqshl z0.b, p0/m, z0.d, z1.d
62 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
63 // CHECK-NEXT: sqshl z0.b, p0/m, z0.d, z1.d
64 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
66 sqshl z0.b, p0/m, z0.b, z1.h
67 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
68 // CHECK-NEXT: sqshl z0.b, p0/m, z0.b, z1.h
69 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
71 sqshl z0.b, p0/m, z0.d, #0
72 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
73 // CHECK-NEXT: sqshl z0.b, p0/m, z0.d, #0
74 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
76 sqshl z0.d, p0/m, z0.b, #0
77 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
78 // CHECK-NEXT: sqshl z0.d, p0/m, z0.b, #0
79 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
82 // --------------------------------------------------------------------------//
83 // Invalid predicate
85 sqshl z0.b, p0/z, z0.b, z1.b
86 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
87 // CHECK-NEXT: sqshl z0.b, p0/z, z0.b, z1.b
88 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
90 sqshl z0.b, p8/m, z0.b, z1.b
91 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
92 // CHECK-NEXT: sqshl z0.b, p8/m, z0.b, z1.b
93 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
95 sqshl z0.b, p8/m, z0.b, #0
96 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
97 // CHECK-NEXT: sqshl z0.b, p8/m, z0.b, #0
98 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: