test/MC/AArch64/SVE2/stnt1d-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
   2
   3
   4 // --------------------------------------------------------------------------//
   5 // Invalid result type.
   6
   7 stnt1d { z0.b }, p0, [z0.s]
   8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   9 // CHECK-NEXT: stnt1d { z0.b }, p0, [z0.s]
  10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  11
  12 stnt1d { z0.h }, p0, [z0.s]
  13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  14 // CHECK-NEXT: stnt1d { z0.h }, p0, [z0.s]
  15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  16
  17 stnt1d { z0.s }, p0, [z0.s]
  18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  19 // CHECK-NEXT: stnt1d { z0.s }, p0, [z0.s]
  20 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  21
  22
  23 // --------------------------------------------------------------------------//
  24 // Invalid base vector.
  25
  26 stnt1d { z0.d }, p0, [z0.b]
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  28 // CHECK-NEXT: stnt1d { z0.d }, p0, [z0.b]
  29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  30
  31
  32 // --------------------------------------------------------------------------//
  33 // Invalid offset type.
  34
  35 stnt1d { z0.d }, p0, [z0.d, z1.d]
  36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  37 // CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, z1.d]
  38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  39
  40
  41 // --------------------------------------------------------------------------//
  42 // restricted predicate has range [0, 7].
  43
  44 stnt1d { z27.d }, p8, [z0.d]
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  46 // CHECK-NEXT: stnt1d { z27.d }, p8, [z0.d]
  47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  48
  49
  50 // --------------------------------------------------------------------------//
  51 // Invalid vector list.
  52
  53 stnt1d { }, p0, [z0.d]
  54 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
  55 // CHECK-NEXT: stnt1d { }, p0, [z0.d]
  56 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  57
  58 stnt1d { z0.d, z1.d }, p0, [z0.d]
  59 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  60 // CHECK-NEXT: stnt1d { z0.d, z1.d }, p0, [z0.d]
  61 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  62
  63 stnt1d { v0.2d }, p0, [z0.d]
  64 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  65 // CHECK-NEXT: stnt1d { v0.2d }, p0, [z0.d]
  66 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  67
  68
  69 // --------------------------------------------------------------------------//
  70 // Negative tests for instructions that are incompatible with movprfx
  71
  72 movprfx z0.d, p0/z, z7.d
  73 stnt1d  { z0.d }, p0, [z0.d, x0]
  74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  75 // CHECK-NEXT: stnt1d  { z0.d }, p0, [z0.d, x0]
  76 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  77
  78 movprfx z0, z7
  79 stnt1d  { z0.d }, p0, [z0.d, x0]
  80 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  81 // CHECK-NEXT: stnt1d  { z0.d }, p0, [z0.d, x0]
  82 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: