test/MC/AArch64/arm32-elf-relocs.s

   1 // RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -o - < %s | \
   2 // RUN:   FileCheck %s
   3 // RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding \
   4 // RUN:    -o - < %s | FileCheck --check-prefix=CHECK-ENCODING %s
   5 // RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -filetype=obj < %s | \
   6 // RUN:   llvm-objdump -triple=arm64-linux-gnu - -r | \
   7 // RUN:   FileCheck %s --check-prefix=CHECK-OBJ-ILP32
   8
   9    add x0, x2, #:lo12:sym
  10 // CHECK: add x0, x2, :lo12:sym
  11 // CHECK-OBJ-ILP32: 0 R_AARCH64_P32_ADD_ABS_LO12_NC sym
  12
  13    add x5, x7, #:dtprel_lo12:sym
  14 // CHECK: add x5, x7, :dtprel_lo12:sym
  15 // CHECK-OBJ-ILP32: 4 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym
  16
  17    add x9, x12, #:dtprel_lo12_nc:sym
  18 // CHECK: add x9, x12, :dtprel_lo12_nc:sym
  19 // CHECK-OBJ-ILP32: 8 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym
  20
  21    add x20, x30, #:tprel_lo12:sym
  22 // CHECK: add x20, x30, :tprel_lo12:sym
  23 // CHECK-OBJ-ILP32: c R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym
  24
  25    add x9, x12, #:tprel_lo12_nc:sym
  26 // CHECK: add x9, x12, :tprel_lo12_nc:sym
  27 // CHECK-OBJ-ILP32: 10 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym
  28
  29    add x5, x0, #:tlsdesc_lo12:sym
  30 // CHECK: add x5, x0, :tlsdesc_lo12:sym
  31 // CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12 sym
  32
  33         add x0, x2, #:lo12:sym+8
  34 // CHECK: add x0, x2, :lo12:sym
  35 // CHECK-OBJ-ILP32: 18 R_AARCH64_P32_ADD_ABS_LO12_NC sym+8
  36
  37    add x5, x7, #:dtprel_lo12:sym+1
  38 // CHECK: add x5, x7, :dtprel_lo12:sym+1
  39 // CHECK-OBJ-ILP32: 1c R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym+1
  40
  41    add x9, x12, #:dtprel_lo12_nc:sym+2
  42 // CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
  43 // CHECK-OBJ-ILP32:20 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym+2
  44
  45    add x20, x30, #:tprel_lo12:sym+12
  46 // CHECK: add x20, x30, :tprel_lo12:sym+12
  47 // CHECK-OBJ-ILP32: 24 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym+12
  48
  49    add x9, x12, #:tprel_lo12_nc:sym+54
  50 // CHECK: add x9, x12, :tprel_lo12_nc:sym+54
  51 // CHECK-OBJ-ILP32: 28 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym+54
  52
  53    add x5, x0, #:tlsdesc_lo12:sym+70
  54 // CHECK: add x5, x0, :tlsdesc_lo12:sym+70
  55 // CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12 sym+70
  56
  57         .hword sym + 4 - .
  58 // CHECK-OBJ-ILP32: 30 R_AARCH64_P32_PREL16 sym+4
  59         .word sym - . + 8
  60 // CHECK-OBJ-ILP32: 32 R_AARCH64_P32_PREL32 sym+8
  61
  62         .hword sym
  63 // CHECK-OBJ-ILP32: 36 R_AARCH64_P32_ABS16 sym
  64         .word sym+1
  65 // CHECK-OBJ-ILP32: 38 R_AARCH64_P32_ABS32 sym+1
  66
  67    adrp x0, sym
  68 // CHECK: adrp x0, sym
  69 // CHECK-OBJ-ILP32: 3c R_AARCH64_P32_ADR_PREL_PG_HI21 sym
  70
  71    adrp x15, :got:sym
  72 // CHECK: adrp x15, :got:sym
  73 // CHECK-OBJ-ILP32: 40 R_AARCH64_P32_ADR_GOT_PAGE sym
  74
  75    adrp x29, :gottprel:sym
  76 // CHECK: adrp x29, :gottprel:sym
  77 // CHECK-OBJ-ILP32: 44 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym
  78
  79    adrp x2, :tlsdesc:sym
  80 // CHECK: adrp x2, :tlsdesc:sym
  81 // CHECK-OBJ-ILP32: 48 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym
  82
  83    // LLVM is not competent enough to do this relocation because the
  84    // page boundary could occur anywhere after linking. A relocation
  85    // is needed.
  86    adrp x3, trickQuestion
  87    .global trickQuestion
  88 trickQuestion:
  89 // CHECK: adrp x3, trickQuestion
  90 // CHECK-OBJ-ILP32: 4c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion
  91
  92    ldrb w2, [x3, :lo12:sym]
  93    ldrsb w5, [x7, #:lo12:sym]
  94    ldrsb x11, [x13, :lo12:sym]
  95    ldr b17, [x19, #:lo12:sym]
  96 // CHECK: ldrb w2, [x3, :lo12:sym]
  97 // CHECK: ldrsb w5, [x7, :lo12:sym]
  98 // CHECK: ldrsb x11, [x13, :lo12:sym]
  99 // CHECK: ldr b17, [x19, :lo12:sym]
 100 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
 101 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
 102 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
 103 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
 104
 105    ldrb w23, [x29, #:dtprel_lo12_nc:sym]
 106    ldrsb w23, [x19, #:dtprel_lo12:sym]
 107    ldrsb x17, [x13, :dtprel_lo12_nc:sym]
 108    ldr b11, [x7, #:dtprel_lo12:sym]
 109 // CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
 110 // CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
 111 // CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
 112 // CHECK: ldr b11, [x7, :dtprel_lo12:sym]
 113 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
 114 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
 115 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
 116 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
 117
 118    ldrb w1, [x2, :tprel_lo12:sym]
 119    ldrsb w3, [x4, #:tprel_lo12_nc:sym]
 120    ldrsb x5, [x6, :tprel_lo12:sym]
 121    ldr b7, [x8, #:tprel_lo12_nc:sym]
 122 // CHECK: ldrb w1, [x2, :tprel_lo12:sym]
 123 // CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
 124 // CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
 125 // CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
 126 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
 127 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
 128 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
 129 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
 130
 131    ldrh w2, [x3, #:lo12:sym]
 132    ldrsh w5, [x7, :lo12:sym]
 133    ldrsh x11, [x13, #:lo12:sym]
 134    ldr h17, [x19, :lo12:sym]
 135 // CHECK: ldrh w2, [x3, :lo12:sym]
 136 // CHECK: ldrsh w5, [x7, :lo12:sym]
 137 // CHECK: ldrsh x11, [x13, :lo12:sym]
 138 // CHECK: ldr h17, [x19, :lo12:sym]
 139 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
 140 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
 141 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
 142 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
 143
 144    ldrh w23, [x29, #:dtprel_lo12_nc:sym]
 145    ldrsh w23, [x19, :dtprel_lo12:sym]
 146    ldrsh x17, [x13, :dtprel_lo12_nc:sym]
 147    ldr h11, [x7, #:dtprel_lo12:sym]
 148 // CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
 149 // CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
 150 // CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
 151 // CHECK: ldr h11, [x7, :dtprel_lo12:sym]
 152 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
 153 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
 154 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
 155 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
 156
 157    ldrh w1, [x2, :tprel_lo12:sym]
 158    ldrsh w3, [x4, #:tprel_lo12_nc:sym]
 159    ldrsh x5, [x6, :tprel_lo12:sym]
 160    ldr h7, [x8, #:tprel_lo12_nc:sym]
 161 // CHECK: ldrh w1, [x2, :tprel_lo12:sym]
 162 // CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
 163 // CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
 164 // CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
 165 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
 166 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
 167 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
 168 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
 169
 170    ldr w1, [x2, #:lo12:sym]
 171    ldrsw x3, [x4, #:lo12:sym]
 172    ldr s4, [x5, :lo12:sym]
 173 // CHECK: ldr w1, [x2, :lo12:sym]
 174 // CHECK: ldrsw x3, [x4, :lo12:sym]
 175 // CHECK: ldr s4, [x5, :lo12:sym]
 176 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
 177 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
 178 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
 179
 180    ldr w1, [x2, :dtprel_lo12:sym]
 181    ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
 182    ldr s4, [x5, #:dtprel_lo12_nc:sym]
 183 // CHECK: ldr w1, [x2, :dtprel_lo12:sym]
 184 // CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
 185 // CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
 186 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym
 187 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
 188 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
 189
 190
 191    ldr w1, [x2, #:tprel_lo12:sym]
 192    ldrsw x3, [x4, :tprel_lo12_nc:sym]
 193    ldr s4, [x5, :tprel_lo12_nc:sym]
 194 // CHECK: ldr w1, [x2, :tprel_lo12:sym]
 195 // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
 196 // CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
 197 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym
 198 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
 199 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
 200
 201    ldr x28, [x27, :lo12:sym]
 202    ldr d26, [x25, :lo12:sym]
 203 // CHECK: ldr x28, [x27, :lo12:sym]
 204 // CHECK: ldr d26, [x25, :lo12:sym]
 205 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym
 206 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym
 207
 208    ldr w24, [x23, :got_lo12:sym]
 209    ldr s22, [x21, :got_lo12:sym]
 210 // CHECK: ldr w24, [x23, :got_lo12:sym]
 211 // CHECK: ldr s22, [x21, :got_lo12:sym]
 212 // CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym
 213 // CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym
 214
 215    ldr x24, [x23, :dtprel_lo12_nc:sym]
 216    ldr d22, [x21, :dtprel_lo12:sym]
 217 // CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
 218 // CHECK: ldr d22, [x21, :dtprel_lo12:sym]
 219 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym
 220 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym
 221
 222    ldr q24, [x23, :dtprel_lo12_nc:sym]
 223    ldr q22, [x21, :dtprel_lo12:sym]
 224 // CHECK: ldr q24, [x23, :dtprel_lo12_nc:sym]
 225 // CHECK: ldr q22, [x21, :dtprel_lo12:sym]
 226 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC sym
 227 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12 sym
 228
 229    ldr x24, [x23, :tprel_lo12:sym]
 230    ldr d22, [x21, :tprel_lo12_nc:sym]
 231 // CHECK: ldr x24, [x23, :tprel_lo12:sym]
 232 // CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
 233 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym
 234 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym
 235
 236    ldr q24, [x23, :tprel_lo12:sym]
 237    ldr q22, [x21, :tprel_lo12_nc:sym]
 238 // CHECK: ldr q24, [x23, :tprel_lo12:sym]
 239 // CHECK: ldr q22, [x21, :tprel_lo12_nc:sym]
 240 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 sym
 241 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC sym
 242
 243    ldr w24, [x23, :gottprel_lo12:sym]
 244    ldr s22, [x21, :gottprel_lo12:sym]
 245
 246    ldr w24, [x23, :tlsdesc_lo12:sym]
 247    ldr s22, [x21, :tlsdesc_lo12:sym]
 248 // CHECK: ldr w24, [x23, :tlsdesc_lo12:sym]
 249 // CHECK: ldr s22, [x21, :tlsdesc_lo12:sym]
 250 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym
 251 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym
 252
 253    ldr q20, [x19, #:lo12:sym]
 254 // CHECK: ldr q20, [x19, :lo12:sym]
 255 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST128_ABS_LO12_NC sym
 256 // check encoding here, since encoding test doesn't belong with TLS encoding
 257 // tests, as it isn't a TLS relocation.
 258 // CHECK-ENCODING: ldr q20, [x19, :lo12:sym] // encoding: [0x74,0bAAAAAA10,0b11AAAAAA,0x3d]
 259 // CHECK-ENCODING-NEXT:  0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale16
 260
 261 // Since relocated instructions print without a '#', that syntax should
 262 // certainly be accepted when assembling.
 263    add x3, x5, :lo12:imm
 264 // CHECK: add x3, x5, :lo12:imm