test/MC/ARM/mve-reductions.s

   1 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s 2>%t \
   2 # RUN:   | FileCheck --check-prefix=CHECK %s
   3 # RUN:     FileCheck --check-prefix=ERROR < %t %s
   4 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding  < %s 2>%t \
   5 # RUN:   | FileCheck --check-prefix=CHECK %s
   6 # RUN:     FileCheck --check-prefix=ERROR < %t %s
   7
   8 # CHECK: vabav.s8  r0, q1, q3 @ encoding: [0x82,0xee,0x07,0x0f]
   9 vabav.s8 r0, q1, q3
  10
  11 # CHECK: vabav.s16  r0, q1, q3 @ encoding: [0x92,0xee,0x07,0x0f]
  12 vabav.s16 r0, q1, q3
  13
  14 # CHECK: vabav.s32  r0, q1, q3 @ encoding: [0xa2,0xee,0x07,0x0f]
  15 vabav.s32 r0, q1, q3
  16
  17 # CHECK: vabav.u8  r0, q1, q3 @ encoding: [0x82,0xfe,0x07,0x0f]
  18 vabav.u8 r0, q1, q3
  19
  20 # CHECK: vabav.u16  r0, q1, q3 @ encoding: [0x92,0xfe,0x07,0x0f]
  21 vabav.u16 r0, q1, q3
  22
  23 # CHECK: vabav.u32  r0, q1, q3 @ encoding: [0xa2,0xfe,0x07,0x0f]
  24 vabav.u32 r0, q1, q3
  25
  26 # CHECK: vaddv.s16 lr, q0  @ encoding: [0xf5,0xee,0x00,0xef]
  27 vaddv.s16 lr, q0
  28
  29 # ERROR: [[@LINE+1]]:11: {{error|note}}: operand must be an even-numbered register
  30 vaddv.s16 r1, q0
  31
  32 # CHECK: vpte.i8 eq, q0, q0
  33 # CHECK: vaddvt.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
  34 # CHECK: vaddve.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
  35 vpte.i8 eq, q0, q0
  36 vaddvt.s16 r0, q6
  37 vaddve.s16 r0, q6
  38
  39 # CHECK: vaddva.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
  40 vaddva.s16 lr, q0
  41
  42 # CHECK: vpte.i8 eq, q0, q0
  43 # CHECK: vaddvat.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
  44 # CHECK: vaddvae.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
  45 vpte.i8 eq, q0, q0
  46 vaddvat.s16 lr, q0
  47 vaddvae.s16 lr, q0
  48
  49 # CHECK: vaddlv.s32 r0, r9, q2  @ encoding: [0xc9,0xee,0x04,0x0f]
  50 vaddlv.s32 r0, r9, q2
  51
  52 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
  53 vaddlv.s32 r0, r2, q2
  54
  55 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register
  56 vaddlv.s32 r1, r3, q2
  57
  58 # CHECK: vaddlv.u32 r0, r1, q1  @ encoding: [0x89,0xfe,0x02,0x0f]
  59 vaddlv.u32 r0, r1, q1
  60
  61 # CHECK: vminv.s8 lr, q0  @ encoding: [0xe2,0xee,0x80,0xef]
  62 vminv.s8 lr, q0
  63
  64 # CHECK: vminv.s16 lr, q0  @ encoding: [0xe6,0xee,0x80,0xef]
  65 vminv.s16 lr, q0
  66
  67 # CHECK: vminv.s32 lr, q2  @ encoding: [0xea,0xee,0x84,0xef]
  68 vminv.s32 lr, q2
  69
  70 # CHECK: vminv.u8 r0, q0  @ encoding: [0xe2,0xfe,0x80,0x0f]
  71 vminv.u8 r0, q0
  72
  73 # CHECK: vminv.u32 r10, q3  @ encoding: [0xea,0xfe,0x86,0xaf]
  74 vminv.u32 r10, q3
  75
  76 # CHECK: vminav.s16 r0, q0  @ encoding: [0xe4,0xee,0x80,0x0f]
  77 vminav.s16 r0, q0
  78
  79 # CHECK: vminav.s8 r0, q1  @ encoding: [0xe0,0xee,0x82,0x0f]
  80 vminav.s8 r0, q1
  81
  82 # CHECK: vminav.s32 lr, q1  @ encoding: [0xe8,0xee,0x82,0xef]
  83 vminav.s32 lr, q1
  84
  85 # CHECK: vmaxv.s8 lr, q4  @ encoding: [0xe2,0xee,0x08,0xef]
  86 vmaxv.s8 lr, q4
  87
  88 # CHECK: vmaxv.s16 lr, q0  @ encoding: [0xe6,0xee,0x00,0xef]
  89 vmaxv.s16 lr, q0
  90
  91 # CHECK: vmaxv.s32 r1, q1  @ encoding: [0xea,0xee,0x02,0x1f]
  92 vmaxv.s32 r1, q1
  93
  94 # CHECK: vmaxv.u8 r0, q4  @ encoding: [0xe2,0xfe,0x08,0x0f]
  95 vmaxv.u8 r0, q4
  96
  97 # CHECK: vmaxv.u16 r0, q1  @ encoding: [0xe6,0xfe,0x02,0x0f]
  98 vmaxv.u16 r0, q1
  99
 100 # CHECK: vmaxv.u32 r1, q0  @ encoding: [0xea,0xfe,0x00,0x1f]
 101 vmaxv.u32 r1, q0
 102
 103 # CHECK: vmaxav.s8 lr, q6  @ encoding: [0xe0,0xee,0x0c,0xef]
 104 vmaxav.s8 lr, q6
 105
 106 # CHECK: vmaxav.s16 r0, q6  @ encoding: [0xe4,0xee,0x0c,0x0f]
 107 vmaxav.s16 r0, q6
 108
 109 # CHECK: vmaxav.s32 r10, q7  @ encoding: [0xe8,0xee,0x0e,0xaf]
 110 vmaxav.s32 r10, q7
 111
 112 # CHECK: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
 113 vmladav.s16 lr, q0, q7
 114
 115 # CHECK: vmlav.s32 lr, q0, q4  @ encoding: [0xf1,0xee,0x08,0xee]
 116 vmladav.s32 lr, q0, q4
 117
 118 # CHECK: vmlav.u16 lr, q0, q7  @ encoding: [0xf0,0xfe,0x0e,0xee]
 119 vmladav.u16 lr, q0, q7
 120
 121 # CHECK: vmlav.u32 lr, q0, q0  @ encoding: [0xf1,0xfe,0x00,0xee]
 122 vmladav.u32 lr, q0, q0
 123
 124 # CHECK: vmlava.s16 lr, q0, q4  @ encoding: [0xf0,0xee,0x28,0xee]
 125 vmladava.s16 lr, q0, q4
 126
 127 # CHECK: vmladavx.s16 r0, q0, q7  @ encoding: [0xf0,0xee,0x0e,0x1e]
 128 vmladavx.s16 r0, q0, q7
 129
 130 # CHECK: vmladavax.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x2e,0xfe]
 131 vmladavax.s16 lr, q0, q7
 132
 133 # CHECK: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
 134 vmladav.s8 lr, q3, q0
 135
 136 # CHECK: vmlav.u8 lr, q1, q7  @ encoding: [0xf2,0xfe,0x0e,0xef]
 137 vmladav.u8 lr, q1, q7
 138
 139 # CHECK: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
 140 vrmlaldavh.s32 lr, r1, q6, q2
 141
 142 # CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
 143 vrmlaldavh.u32 lr, r1, q5, q2
 144
 145 # CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
 146 vrmlaldavh.u32 lr, r1, q5, q2
 147
 148 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register
 149 vrmlaldavh.u32 r1, r3, q5, q2
 150
 151 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
 152 vrmlaldavh.u32 r2, r4, q5, q2
 153
 154 # CHECK: vrmlaldavhax.s32 lr, r1, q3, q0  @ encoding: [0x86,0xee,0x20,0xff]
 155 vrmlaldavhax.s32 lr, r1, q3, q0
 156
 157 # CHECK: vrmlsldavh.s32 lr, r11, q6, q5  @ encoding: [0xdc,0xfe,0x0b,0xee]
 158 vrmlsldavh.s32 lr, r11, q6, q5
 159
 160 # CHECK: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
 161 vmlsdav.s16 lr, q0, q3
 162
 163 # CHECK: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
 164 vrmlalvh.s32 lr, r1, q6, q2
 165
 166 # CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
 167 vrmlalvh.u32 lr, r1, q5, q2
 168
 169 # CHECK: vrmlalvha.s32 lr, r1, q3, q6  @ encoding: [0x86,0xee,0x2c,0xef]
 170 vrmlalvha.s32 lr, r1, q3, q6
 171
 172 # CHECK: vrmlalvha.u32 lr, r1, q7, q1  @ encoding: [0x8e,0xfe,0x22,0xef]
 173 vrmlalvha.u32 lr, r1, q7, q1
 174
 175 # CHECK: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
 176 vmlsdav.s16 lr, q0, q3
 177
 178 # CHECK: vmlsdav.s32 lr, q2, q6  @ encoding: [0xf5,0xee,0x0d,0xee]
 179 vmlsdav.s32 lr, q2, q6
 180
 181 # CHECK: vpte.i8 eq, q0, q0
 182 # CHECK: vmlsdavaxt.s16 lr, q1, q4  @ encoding: [0xf2,0xee,0x29,0xfe]
 183 # CHECK: vmlsdavaxe.s16 lr, q1, q4  @ encoding: [0xf2,0xee,0x29,0xfe]
 184 vpte.i8 eq, q0, q0
 185 vmlsdavaxt.s16 lr, q1, q4
 186 vmlsdavaxe.s16 lr, q1, q4
 187
 188 # CHECK: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
 189 vmlav.s16 lr, q0, q7
 190
 191 # CHECK: vmlalv.s16 lr, r1, q4, q1  @ encoding: [0x88,0xee,0x02,0xee]
 192 vmlaldav.s16 lr, r1, q4, q1
 193
 194 # CHECK: vmlalv.s32 lr, r11, q4, q1  @ encoding: [0xd9,0xee,0x02,0xee]
 195 vmlaldav.s32 lr, r11, q4, q1
 196
 197 # CHECK: vmlalv.s32 r0, r1, q7, q6  @ encoding: [0x8f,0xee,0x0c,0x0e]
 198 vmlalv.s32 r0, r1, q7, q6
 199
 200 # CHECK: vmlalv.u16 lr, r11, q5, q4  @ encoding: [0xda,0xfe,0x08,0xee]
 201 vmlalv.u16 lr, r11, q5, q4