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[llvm-objdump] - Remove one overload of reportError. NFCI.
[llvm-complete.git] / utils / TableGen / CodeGenTarget.cpp
blobe9c075280ec802b2e30b52bde267ec435e060842
1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class wraps target description classes used by the various code
10 // generation TableGen backends. This makes it easier to access the data and
11 // provides a single place that needs to check it for validity. All of these
12 // classes abort on error conditions.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "CodeGenTarget.h"
17 #include "CodeGenDAGPatterns.h"
18 #include "CodeGenIntrinsics.h"
19 #include "CodeGenSchedule.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Timer.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
27 #include <algorithm>
28 using namespace llvm;
29
30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
32
33 static cl::opt<unsigned>
34 AsmParserNum("asmparsernum", cl::init(0),
35 cl::desc("Make -gen-asm-parser emit assembly parser #N"),
36 cl::cat(AsmParserCat));
37
38 static cl::opt<unsigned>
39 AsmWriterNum("asmwriternum", cl::init(0),
40 cl::desc("Make -gen-asm-writer emit assembly writer #N"),
41 cl::cat(AsmWriterCat));
42
43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
44 /// record corresponds to.
45 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
47 }
48
49 StringRef llvm::getName(MVT::SimpleValueType T) {
50 switch (T) {
51 case MVT::Other: return "UNKNOWN";
52 case MVT::iPTR: return "TLI.getPointerTy()";
53 case MVT::iPTRAny: return "TLI.getPointerTy()";
54 default: return getEnumName(T);
55 }
56 }
57
58 StringRef llvm::getEnumName(MVT::SimpleValueType T) {
59 switch (T) {
60 case MVT::Other: return "MVT::Other";
61 case MVT::i1: return "MVT::i1";
62 case MVT::i8: return "MVT::i8";
63 case MVT::i16: return "MVT::i16";
64 case MVT::i32: return "MVT::i32";
65 case MVT::i64: return "MVT::i64";
66 case MVT::i128: return "MVT::i128";
67 case MVT::Any: return "MVT::Any";
68 case MVT::iAny: return "MVT::iAny";
69 case MVT::fAny: return "MVT::fAny";
70 case MVT::vAny: return "MVT::vAny";
71 case MVT::f16: return "MVT::f16";
72 case MVT::f32: return "MVT::f32";
73 case MVT::f64: return "MVT::f64";
74 case MVT::f80: return "MVT::f80";
75 case MVT::f128: return "MVT::f128";
76 case MVT::ppcf128: return "MVT::ppcf128";
77 case MVT::x86mmx: return "MVT::x86mmx";
78 case MVT::Glue: return "MVT::Glue";
79 case MVT::isVoid: return "MVT::isVoid";
80 case MVT::v1i1: return "MVT::v1i1";
81 case MVT::v2i1: return "MVT::v2i1";
82 case MVT::v4i1: return "MVT::v4i1";
83 case MVT::v8i1: return "MVT::v8i1";
84 case MVT::v16i1: return "MVT::v16i1";
85 case MVT::v32i1: return "MVT::v32i1";
86 case MVT::v64i1: return "MVT::v64i1";
87 case MVT::v128i1: return "MVT::v128i1";
88 case MVT::v512i1: return "MVT::v512i1";
89 case MVT::v1024i1: return "MVT::v1024i1";
90 case MVT::v1i8: return "MVT::v1i8";
91 case MVT::v2i8: return "MVT::v2i8";
92 case MVT::v4i8: return "MVT::v4i8";
93 case MVT::v8i8: return "MVT::v8i8";
94 case MVT::v16i8: return "MVT::v16i8";
95 case MVT::v32i8: return "MVT::v32i8";
96 case MVT::v64i8: return "MVT::v64i8";
97 case MVT::v128i8: return "MVT::v128i8";
98 case MVT::v256i8: return "MVT::v256i8";
99 case MVT::v1i16: return "MVT::v1i16";
100 case MVT::v2i16: return "MVT::v2i16";
101 case MVT::v3i16: return "MVT::v3i16";
102 case MVT::v4i16: return "MVT::v4i16";
103 case MVT::v8i16: return "MVT::v8i16";
104 case MVT::v16i16: return "MVT::v16i16";
105 case MVT::v32i16: return "MVT::v32i16";
106 case MVT::v64i16: return "MVT::v64i16";
107 case MVT::v128i16: return "MVT::v128i16";
108 case MVT::v1i32: return "MVT::v1i32";
109 case MVT::v2i32: return "MVT::v2i32";
110 case MVT::v3i32: return "MVT::v3i32";
111 case MVT::v4i32: return "MVT::v4i32";
112 case MVT::v5i32: return "MVT::v5i32";
113 case MVT::v8i32: return "MVT::v8i32";
114 case MVT::v16i32: return "MVT::v16i32";
115 case MVT::v32i32: return "MVT::v32i32";
116 case MVT::v64i32: return "MVT::v64i32";
117 case MVT::v128i32: return "MVT::v128i32";
118 case MVT::v256i32: return "MVT::v256i32";
119 case MVT::v512i32: return "MVT::v512i32";
120 case MVT::v1024i32: return "MVT::v1024i32";
121 case MVT::v2048i32: return "MVT::v2048i32";
122 case MVT::v1i64: return "MVT::v1i64";
123 case MVT::v2i64: return "MVT::v2i64";
124 case MVT::v4i64: return "MVT::v4i64";
125 case MVT::v8i64: return "MVT::v8i64";
126 case MVT::v16i64: return "MVT::v16i64";
127 case MVT::v32i64: return "MVT::v32i64";
128 case MVT::v1i128: return "MVT::v1i128";
129 case MVT::v2f16: return "MVT::v2f16";
130 case MVT::v3f16: return "MVT::v3f16";
131 case MVT::v4f16: return "MVT::v4f16";
132 case MVT::v8f16: return "MVT::v8f16";
133 case MVT::v1f32: return "MVT::v1f32";
134 case MVT::v2f32: return "MVT::v2f32";
135 case MVT::v3f32: return "MVT::v3f32";
136 case MVT::v4f32: return "MVT::v4f32";
137 case MVT::v5f32: return "MVT::v5f32";
138 case MVT::v8f32: return "MVT::v8f32";
139 case MVT::v16f32: return "MVT::v16f32";
140 case MVT::v32f32: return "MVT::v32f32";
141 case MVT::v64f32: return "MVT::v64f32";
142 case MVT::v128f32: return "MVT::v128f32";
143 case MVT::v256f32: return "MVT::v256f32";
144 case MVT::v512f32: return "MVT::v512f32";
145 case MVT::v1024f32: return "MVT::v1024f32";
146 case MVT::v2048f32: return "MVT::v2048f32";
147 case MVT::v1f64: return "MVT::v1f64";
148 case MVT::v2f64: return "MVT::v2f64";
149 case MVT::v4f64: return "MVT::v4f64";
150 case MVT::v8f64: return "MVT::v8f64";
151 case MVT::nxv1i1: return "MVT::nxv1i1";
152 case MVT::nxv2i1: return "MVT::nxv2i1";
153 case MVT::nxv4i1: return "MVT::nxv4i1";
154 case MVT::nxv8i1: return "MVT::nxv8i1";
155 case MVT::nxv16i1: return "MVT::nxv16i1";
156 case MVT::nxv32i1: return "MVT::nxv32i1";
157 case MVT::nxv1i8: return "MVT::nxv1i8";
158 case MVT::nxv2i8: return "MVT::nxv2i8";
159 case MVT::nxv4i8: return "MVT::nxv4i8";
160 case MVT::nxv8i8: return "MVT::nxv8i8";
161 case MVT::nxv16i8: return "MVT::nxv16i8";
162 case MVT::nxv32i8: return "MVT::nxv32i8";
163 case MVT::nxv1i16: return "MVT::nxv1i16";
164 case MVT::nxv2i16: return "MVT::nxv2i16";
165 case MVT::nxv4i16: return "MVT::nxv4i16";
166 case MVT::nxv8i16: return "MVT::nxv8i16";
167 case MVT::nxv16i16: return "MVT::nxv16i16";
168 case MVT::nxv32i16: return "MVT::nxv32i16";
169 case MVT::nxv1i32: return "MVT::nxv1i32";
170 case MVT::nxv2i32: return "MVT::nxv2i32";
171 case MVT::nxv4i32: return "MVT::nxv4i32";
172 case MVT::nxv8i32: return "MVT::nxv8i32";
173 case MVT::nxv16i32: return "MVT::nxv16i32";
174 case MVT::nxv1i64: return "MVT::nxv1i64";
175 case MVT::nxv2i64: return "MVT::nxv2i64";
176 case MVT::nxv4i64: return "MVT::nxv4i64";
177 case MVT::nxv8i64: return "MVT::nxv8i64";
178 case MVT::nxv16i64: return "MVT::nxv16i64";
179 case MVT::nxv2f16: return "MVT::nxv2f16";
180 case MVT::nxv4f16: return "MVT::nxv4f16";
181 case MVT::nxv8f16: return "MVT::nxv8f16";
182 case MVT::nxv1f32: return "MVT::nxv1f32";
183 case MVT::nxv2f32: return "MVT::nxv2f32";
184 case MVT::nxv4f32: return "MVT::nxv4f32";
185 case MVT::nxv8f32: return "MVT::nxv8f32";
186 case MVT::nxv16f32: return "MVT::nxv16f32";
187 case MVT::nxv1f64: return "MVT::nxv1f64";
188 case MVT::nxv2f64: return "MVT::nxv2f64";
189 case MVT::nxv4f64: return "MVT::nxv4f64";
190 case MVT::nxv8f64: return "MVT::nxv8f64";
191 case MVT::token: return "MVT::token";
192 case MVT::Metadata: return "MVT::Metadata";
193 case MVT::iPTR: return "MVT::iPTR";
194 case MVT::iPTRAny: return "MVT::iPTRAny";
195 case MVT::Untyped: return "MVT::Untyped";
196 case MVT::exnref: return "MVT::exnref";
197 default: llvm_unreachable("ILLEGAL VALUE TYPE!");
198 }
199 }
200
201 /// getQualifiedName - Return the name of the specified record, with a
202 /// namespace qualifier if the record contains one.
203 ///
204 std::string llvm::getQualifiedName(const Record *R) {
205 std::string Namespace;
206 if (R->getValue("Namespace"))
207 Namespace = R->getValueAsString("Namespace");
208 if (Namespace.empty()) return R->getName();
209 return Namespace + "::" + R->getName().str();
210 }
211
212
213 /// getTarget - Return the current instance of the Target class.
214 ///
215 CodeGenTarget::CodeGenTarget(RecordKeeper &records)
216 : Records(records), CGH(records) {
217 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
218 if (Targets.size() == 0)
219 PrintFatalError("ERROR: No 'Target' subclasses defined!");
220 if (Targets.size() != 1)
221 PrintFatalError("ERROR: Multiple subclasses of Target defined!");
222 TargetRec = Targets[0];
223 }
224
225 CodeGenTarget::~CodeGenTarget() {
226 }
227
228 const StringRef CodeGenTarget::getName() const {
229 return TargetRec->getName();
230 }
231
232 StringRef CodeGenTarget::getInstNamespace() const {
233 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
234 // Make sure not to pick up "TargetOpcode" by accidentally getting
235 // the namespace off the PHI instruction or something.
236 if (Inst->Namespace != "TargetOpcode")
237 return Inst->Namespace;
238 }
239
240 return "";
241 }
242
243 Record *CodeGenTarget::getInstructionSet() const {
244 return TargetRec->getValueAsDef("InstructionSet");
245 }
246
247 bool CodeGenTarget::getAllowRegisterRenaming() const {
248 return TargetRec->getValueAsInt("AllowRegisterRenaming");
249 }
250
251 /// getAsmParser - Return the AssemblyParser definition for this target.
252 ///
253 Record *CodeGenTarget::getAsmParser() const {
254 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
255 if (AsmParserNum >= LI.size())
256 PrintFatalError("Target does not have an AsmParser #" +
257 Twine(AsmParserNum) + "!");
258 return LI[AsmParserNum];
259 }
260
261 /// getAsmParserVariant - Return the AssmblyParserVariant definition for
262 /// this target.
263 ///
264 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
265 std::vector<Record*> LI =
266 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
267 if (i >= LI.size())
268 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
269 "!");
270 return LI[i];
271 }
272
273 /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
274 /// available for this target.
275 ///
276 unsigned CodeGenTarget::getAsmParserVariantCount() const {
277 std::vector<Record*> LI =
278 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
279 return LI.size();
280 }
281
282 /// getAsmWriter - Return the AssemblyWriter definition for this target.
283 ///
284 Record *CodeGenTarget::getAsmWriter() const {
285 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
286 if (AsmWriterNum >= LI.size())
287 PrintFatalError("Target does not have an AsmWriter #" +
288 Twine(AsmWriterNum) + "!");
289 return LI[AsmWriterNum];
290 }
291
292 CodeGenRegBank &CodeGenTarget::getRegBank() const {
293 if (!RegBank)
294 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes());
295 return *RegBank;
296 }
297
298 Optional<CodeGenRegisterClass *>
299 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
300 CodeGenRegBank &RegBank,
301 const CodeGenSubRegIndex *SubIdx) const {
302 std::vector<CodeGenRegisterClass *> Candidates;
303 auto &RegClasses = RegBank.getRegClasses();
304
305 // Try to find a register class which supports ValueTy, and also contains
306 // SubIdx.
307 for (CodeGenRegisterClass &RC : RegClasses) {
308 // Is there a subclass of this class which contains this subregister index?
309 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx);
310 if (!SubClassWithSubReg)
311 continue;
312
313 // We have a class. Check if it supports this value type.
314 if (llvm::none_of(SubClassWithSubReg->VTs,
315 [&ValueTy](const ValueTypeByHwMode &ClassVT) {
316 return ClassVT == ValueTy;
317 }))
318 continue;
319
320 // We have a register class which supports both the value type and
321 // subregister index. Remember it.
322 Candidates.push_back(SubClassWithSubReg);
323 }
324
325 // If we didn't find anything, we're done.
326 if (Candidates.empty())
327 return None;
328
329 // Find and return the largest of our candidate classes.
330 llvm::sort(Candidates,
331 [&](const CodeGenRegisterClass *A, const CodeGenRegisterClass *B) {
332 return A->getMembers().size() > B->getMembers().size();
333 });
334
335 return Candidates[0];
336 }
337
338 void CodeGenTarget::ReadRegAltNameIndices() const {
339 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
340 llvm::sort(RegAltNameIndices, LessRecord());
341 }
342
343 /// getRegisterByName - If there is a register with the specific AsmName,
344 /// return it.
345 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
346 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
347 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
348 if (I == Regs.end())
349 return nullptr;
350 return I->second;
351 }
352
353 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
354 const {
355 const CodeGenRegister *Reg = getRegBank().getReg(R);
356 std::vector<ValueTypeByHwMode> Result;
357 for (const auto &RC : getRegBank().getRegClasses()) {
358 if (RC.contains(Reg)) {
359 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
360 Result.insert(Result.end(), InVTs.begin(), InVTs.end());
361 }
362 }
363
364 // Remove duplicates.
365 llvm::sort(Result);
366 Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
367 return Result;
368 }
369
370
371 void CodeGenTarget::ReadLegalValueTypes() const {
372 for (const auto &RC : getRegBank().getRegClasses())
373 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
374
375 // Remove duplicates.
376 llvm::sort(LegalValueTypes);
377 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
378 LegalValueTypes.end()),
379 LegalValueTypes.end());
380 }
381
382 CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
383 if (!SchedModels)
384 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this);
385 return *SchedModels;
386 }
387
388 void CodeGenTarget::ReadInstructions() const {
389 NamedRegionTimer T("Read Instructions", "Time spent reading instructions",
390 "CodeGenTarget", "CodeGenTarget", TimeRegions);
391 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
392 if (Insts.size() <= 2)
393 PrintFatalError("No 'Instruction' subclasses defined!");
394
395 // Parse the instructions defined in the .td file.
396 for (unsigned i = 0, e = Insts.size(); i != e; ++i)
397 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]);
398 }
399
400 static const CodeGenInstruction *
401 GetInstByName(const char *Name,
402 const DenseMap<const Record*,
403 std::unique_ptr<CodeGenInstruction>> &Insts,
404 RecordKeeper &Records) {
405 const Record *Rec = Records.getDef(Name);
406
407 const auto I = Insts.find(Rec);
408 if (!Rec || I == Insts.end())
409 PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
410 return I->second.get();
411 }
412
413 static const char *const FixedInstrs[] = {
414 #define HANDLE_TARGET_OPCODE(OPC) #OPC,
415 #include "llvm/Support/TargetOpcodes.def"
416 nullptr};
417
418 unsigned CodeGenTarget::getNumFixedInstructions() {
419 return array_lengthof(FixedInstrs) - 1;
420 }
421
422 /// Return all of the instructions defined by the target, ordered by
423 /// their enum value.
424 void CodeGenTarget::ComputeInstrsByEnum() const {
425 const auto &Insts = getInstructions();
426 for (const char *const *p = FixedInstrs; *p; ++p) {
427 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
428 assert(Instr && "Missing target independent instruction");
429 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
430 InstrsByEnum.push_back(Instr);
431 }
432 unsigned EndOfPredefines = InstrsByEnum.size();
433 assert(EndOfPredefines == getNumFixedInstructions() &&
434 "Missing generic opcode");
435
436 for (const auto &I : Insts) {
437 const CodeGenInstruction *CGI = I.second.get();
438 if (CGI->Namespace != "TargetOpcode") {
439 InstrsByEnum.push_back(CGI);
440 if (CGI->TheDef->getValueAsBit("isPseudo"))
441 ++NumPseudoInstructions;
442 }
443 }
444
445 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
446
447 // All of the instructions are now in random order based on the map iteration.
448 llvm::sort(
449 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
450 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
451 const auto &D1 = *Rec1->TheDef;
452 const auto &D2 = *Rec2->TheDef;
453 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
454 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
455 });
456 }
457
458
459 /// isLittleEndianEncoding - Return whether this target encodes its instruction
460 /// in little-endian format, i.e. bits laid out in the order [0..n]
461 ///
462 bool CodeGenTarget::isLittleEndianEncoding() const {
463 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
464 }
465
466 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
467 /// encodings, reverse the bit order of all instructions.
468 void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
469 if (!isLittleEndianEncoding())
470 return;
471
472 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
473 for (Record *R : Insts) {
474 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
475 R->getValueAsBit("isPseudo"))
476 continue;
477
478 BitsInit *BI = R->getValueAsBitsInit("Inst");
479
480 unsigned numBits = BI->getNumBits();
481
482 SmallVector<Init *, 16> NewBits(numBits);
483
484 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
485 unsigned bitSwapIdx = numBits - bit - 1;
486 Init *OrigBit = BI->getBit(bit);
487 Init *BitSwap = BI->getBit(bitSwapIdx);
488 NewBits[bit] = BitSwap;
489 NewBits[bitSwapIdx] = OrigBit;
490 }
491 if (numBits % 2) {
492 unsigned middle = (numBits + 1) / 2;
493 NewBits[middle] = BI->getBit(middle);
494 }
495
496 BitsInit *NewBI = BitsInit::get(NewBits);
497
498 // Update the bits in reversed order so that emitInstrOpBits will get the
499 // correct endianness.
500 R->getValue("Inst")->setValue(NewBI);
501 }
502 }
503
504 /// guessInstructionProperties - Return true if it's OK to guess instruction
505 /// properties instead of raising an error.
506 ///
507 /// This is configurable as a temporary migration aid. It will eventually be
508 /// permanently false.
509 bool CodeGenTarget::guessInstructionProperties() const {
510 return getInstructionSet()->getValueAsBit("guessInstructionProperties");
511 }
512
513 //===----------------------------------------------------------------------===//
514 // ComplexPattern implementation
515 //
516 ComplexPattern::ComplexPattern(Record *R) {
517 Ty = ::getValueType(R->getValueAsDef("Ty"));
518 NumOperands = R->getValueAsInt("NumOperands");
519 SelectFunc = R->getValueAsString("SelectFunc");
520 RootNodes = R->getValueAsListOfDefs("RootNodes");
521
522 // FIXME: This is a hack to statically increase the priority of patterns which
523 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
524 // possible pattern match we'll need to dynamically calculate the complexity
525 // of all patterns a dag can potentially map to.
526 int64_t RawComplexity = R->getValueAsInt("Complexity");
527 if (RawComplexity == -1)
528 Complexity = NumOperands * 3;
529 else
530 Complexity = RawComplexity;
531
532 // FIXME: Why is this different from parseSDPatternOperatorProperties?
533 // Parse the properties.
534 Properties = 0;
535 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
536 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
537 if (PropList[i]->getName() == "SDNPHasChain") {
538 Properties |= 1 << SDNPHasChain;
539 } else if (PropList[i]->getName() == "SDNPOptInGlue") {
540 Properties |= 1 << SDNPOptInGlue;
541 } else if (PropList[i]->getName() == "SDNPMayStore") {
542 Properties |= 1 << SDNPMayStore;
543 } else if (PropList[i]->getName() == "SDNPMayLoad") {
544 Properties |= 1 << SDNPMayLoad;
545 } else if (PropList[i]->getName() == "SDNPSideEffect") {
546 Properties |= 1 << SDNPSideEffect;
547 } else if (PropList[i]->getName() == "SDNPMemOperand") {
548 Properties |= 1 << SDNPMemOperand;
549 } else if (PropList[i]->getName() == "SDNPVariadic") {
550 Properties |= 1 << SDNPVariadic;
551 } else if (PropList[i]->getName() == "SDNPWantRoot") {
552 Properties |= 1 << SDNPWantRoot;
553 } else if (PropList[i]->getName() == "SDNPWantParent") {
554 Properties |= 1 << SDNPWantParent;
555 } else {
556 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" +
557 PropList[i]->getName() +
558 "' on ComplexPattern '" + R->getName() +
559 "'!");
560 }
561 }
562
563 //===----------------------------------------------------------------------===//
564 // CodeGenIntrinsic Implementation
565 //===----------------------------------------------------------------------===//
566
567 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC,
568 bool TargetOnly) {
569 std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic");
570
571 Intrinsics.reserve(Defs.size());
572
573 for (unsigned I = 0, e = Defs.size(); I != e; ++I) {
574 bool isTarget = Defs[I]->getValueAsBit("isTarget");
575 if (isTarget == TargetOnly)
576 Intrinsics.push_back(CodeGenIntrinsic(Defs[I]));
577 }
578 llvm::sort(Intrinsics,
579 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
580 return std::tie(LHS.TargetPrefix, LHS.Name) <
581 std::tie(RHS.TargetPrefix, RHS.Name);
582 });
583 Targets.push_back({"", 0, 0});
584 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
585 if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
586 Targets.back().Count = I - Targets.back().Offset;
587 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
588 }
589 Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
590 }
591
592 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
593 TheDef = R;
594 std::string DefName = R->getName();
595 ArrayRef<SMLoc> DefLoc = R->getLoc();
596 ModRef = ReadWriteMem;
597 Properties = 0;
598 isOverloaded = false;
599 isCommutative = false;
600 canThrow = false;
601 isNoReturn = false;
602 isWillReturn = false;
603 isCold = false;
604 isNoDuplicate = false;
605 isConvergent = false;
606 isSpeculatable = false;
607 hasSideEffects = false;
608
609 if (DefName.size() <= 4 ||
610 std::string(DefName.begin(), DefName.begin() + 4) != "int_")
611 PrintFatalError(DefLoc,
612 "Intrinsic '" + DefName + "' does not start with 'int_'!");
613
614 EnumName = std::string(DefName.begin()+4, DefName.end());
615
616 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
617 GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
618 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field.
619 MSBuiltinName = R->getValueAsString("MSBuiltinName");
620
621 TargetPrefix = R->getValueAsString("TargetPrefix");
622 Name = R->getValueAsString("LLVMName");
623
624 if (Name == "") {
625 // If an explicit name isn't specified, derive one from the DefName.
626 Name = "llvm.";
627
628 for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
629 Name += (EnumName[i] == '_') ? '.' : EnumName[i];
630 } else {
631 // Verify it starts with "llvm.".
632 if (Name.size() <= 5 ||
633 std::string(Name.begin(), Name.begin() + 5) != "llvm.")
634 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
635 "'s name does not start with 'llvm.'!");
636 }
637
638 // If TargetPrefix is specified, make sure that Name starts with
639 // "llvm.<targetprefix>.".
640 if (!TargetPrefix.empty()) {
641 if (Name.size() < 6+TargetPrefix.size() ||
642 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
643 != (TargetPrefix + "."))
644 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
645 "' does not start with 'llvm." +
646 TargetPrefix + ".'!");
647 }
648
649 ListInit *RetTypes = R->getValueAsListInit("RetTypes");
650 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes");
651
652 // First collate a list of overloaded types.
653 std::vector<MVT::SimpleValueType> OverloadedVTs;
654 for (ListInit *TypeList : {RetTypes, ParamTypes}) {
655 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
656 Record *TyEl = TypeList->getElementAsRecord(i);
657 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
658
659 if (TyEl->isSubClassOf("LLVMMatchType"))
660 continue;
661
662 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT"));
663 if (MVT(VT).isOverloaded()) {
664 OverloadedVTs.push_back(VT);
665 isOverloaded = true;
666 }
667 }
668 }
669
670 // Parse the list of return types.
671 ListInit *TypeList = RetTypes;
672 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
673 Record *TyEl = TypeList->getElementAsRecord(i);
674 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
675 MVT::SimpleValueType VT;
676 if (TyEl->isSubClassOf("LLVMMatchType")) {
677 unsigned MatchTy = TyEl->getValueAsInt("Number");
678 assert(MatchTy < OverloadedVTs.size() &&
679 "Invalid matching number!");
680 VT = OverloadedVTs[MatchTy];
681 // It only makes sense to use the extended and truncated vector element
682 // variants with iAny types; otherwise, if the intrinsic is not
683 // overloaded, all the types can be specified directly.
684 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
685 !TyEl->isSubClassOf("LLVMTruncatedType")) ||
686 VT == MVT::iAny || VT == MVT::vAny) &&
687 "Expected iAny or vAny type");
688 } else {
689 VT = getValueType(TyEl->getValueAsDef("VT"));
690 }
691
692 // Reject invalid types.
693 if (VT == MVT::isVoid)
694 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
695 " has void in result type list!");
696
697 IS.RetVTs.push_back(VT);
698 IS.RetTypeDefs.push_back(TyEl);
699 }
700
701 // Parse the list of parameter types.
702 TypeList = ParamTypes;
703 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
704 Record *TyEl = TypeList->getElementAsRecord(i);
705 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
706 MVT::SimpleValueType VT;
707 if (TyEl->isSubClassOf("LLVMMatchType")) {
708 unsigned MatchTy = TyEl->getValueAsInt("Number");
709 if (MatchTy >= OverloadedVTs.size()) {
710 PrintError(R->getLoc(),
711 "Parameter #" + Twine(i) + " has out of bounds matching "
712 "number " + Twine(MatchTy));
713 PrintFatalError(DefLoc,
714 Twine("ParamTypes is ") + TypeList->getAsString());
715 }
716 VT = OverloadedVTs[MatchTy];
717 // It only makes sense to use the extended and truncated vector element
718 // variants with iAny types; otherwise, if the intrinsic is not
719 // overloaded, all the types can be specified directly.
720 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
721 !TyEl->isSubClassOf("LLVMTruncatedType") &&
722 !TyEl->isSubClassOf("LLVMScalarOrSameVectorWidth")) ||
723 VT == MVT::iAny || VT == MVT::vAny) &&
724 "Expected iAny or vAny type");
725 } else
726 VT = getValueType(TyEl->getValueAsDef("VT"));
727
728 // Reject invalid types.
729 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
730 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
731 " has void in result type list!");
732
733 IS.ParamVTs.push_back(VT);
734 IS.ParamTypeDefs.push_back(TyEl);
735 }
736
737 // Parse the intrinsic properties.
738 ListInit *PropList = R->getValueAsListInit("IntrProperties");
739 for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
740 Record *Property = PropList->getElementAsRecord(i);
741 assert(Property->isSubClassOf("IntrinsicProperty") &&
742 "Expected a property!");
743
744 if (Property->getName() == "IntrNoMem")
745 ModRef = NoMem;
746 else if (Property->getName() == "IntrReadMem")
747 ModRef = ModRefBehavior(ModRef & ~MR_Mod);
748 else if (Property->getName() == "IntrWriteMem")
749 ModRef = ModRefBehavior(ModRef & ~MR_Ref);
750 else if (Property->getName() == "IntrArgMemOnly")
751 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem);
752 else if (Property->getName() == "IntrInaccessibleMemOnly")
753 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem);
754 else if (Property->getName() == "IntrInaccessibleMemOrArgMemOnly")
755 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem |
756 MR_InaccessibleMem);
757 else if (Property->getName() == "Commutative")
758 isCommutative = true;
759 else if (Property->getName() == "Throws")
760 canThrow = true;
761 else if (Property->getName() == "IntrNoDuplicate")
762 isNoDuplicate = true;
763 else if (Property->getName() == "IntrConvergent")
764 isConvergent = true;
765 else if (Property->getName() == "IntrNoReturn")
766 isNoReturn = true;
767 else if (Property->getName() == "IntrWillReturn")
768 isWillReturn = true;
769 else if (Property->getName() == "IntrCold")
770 isCold = true;
771 else if (Property->getName() == "IntrSpeculatable")
772 isSpeculatable = true;
773 else if (Property->getName() == "IntrHasSideEffects")
774 hasSideEffects = true;
775 else if (Property->isSubClassOf("NoCapture")) {
776 unsigned ArgNo = Property->getValueAsInt("ArgNo");
777 ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
778 } else if (Property->isSubClassOf("NoAlias")) {
779 unsigned ArgNo = Property->getValueAsInt("ArgNo");
780 ArgumentAttributes.push_back(std::make_pair(ArgNo, NoAlias));
781 } else if (Property->isSubClassOf("Returned")) {
782 unsigned ArgNo = Property->getValueAsInt("ArgNo");
783 ArgumentAttributes.push_back(std::make_pair(ArgNo, Returned));
784 } else if (Property->isSubClassOf("ReadOnly")) {
785 unsigned ArgNo = Property->getValueAsInt("ArgNo");
786 ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadOnly));
787 } else if (Property->isSubClassOf("WriteOnly")) {
788 unsigned ArgNo = Property->getValueAsInt("ArgNo");
789 ArgumentAttributes.push_back(std::make_pair(ArgNo, WriteOnly));
790 } else if (Property->isSubClassOf("ReadNone")) {
791 unsigned ArgNo = Property->getValueAsInt("ArgNo");
792 ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadNone));
793 } else if (Property->isSubClassOf("ImmArg")) {
794 unsigned ArgNo = Property->getValueAsInt("ArgNo");
795 ArgumentAttributes.push_back(std::make_pair(ArgNo, ImmArg));
796 } else
797 llvm_unreachable("Unknown property!");
798 }
799
800 // Also record the SDPatternOperator Properties.
801 Properties = parseSDPatternOperatorProperties(R);
802
803 // Sort the argument attributes for later benefit.
804 llvm::sort(ArgumentAttributes);
805 }
806
807 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const {
808 if (ParamIdx >= IS.ParamVTs.size())
809 return false;
810 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]);
811 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny;
812 }
The low level virtual machine