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[ARM] Add or update a number of costmodel tests. NFC
[llvm-complete.git] / utils / TableGen / CodeGenTarget.cpp
blobb65e1b6af7919e8355dd5dc4874e2d8500ef7c6f
1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class wraps target description classes used by the various code
10 // generation TableGen backends. This makes it easier to access the data and
11 // provides a single place that needs to check it for validity. All of these
12 // classes abort on error conditions.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "CodeGenTarget.h"
17 #include "CodeGenDAGPatterns.h"
18 #include "CodeGenIntrinsics.h"
19 #include "CodeGenSchedule.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Timer.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
27 #include <algorithm>
28 using namespace llvm;
29
30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
32
33 static cl::opt<unsigned>
34 AsmParserNum("asmparsernum", cl::init(0),
35 cl::desc("Make -gen-asm-parser emit assembly parser #N"),
36 cl::cat(AsmParserCat));
37
38 static cl::opt<unsigned>
39 AsmWriterNum("asmwriternum", cl::init(0),
40 cl::desc("Make -gen-asm-writer emit assembly writer #N"),
41 cl::cat(AsmWriterCat));
42
43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
44 /// record corresponds to.
45 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
47 }
48
49 StringRef llvm::getName(MVT::SimpleValueType T) {
50 switch (T) {
51 case MVT::Other: return "UNKNOWN";
52 case MVT::iPTR: return "TLI.getPointerTy()";
53 case MVT::iPTRAny: return "TLI.getPointerTy()";
54 default: return getEnumName(T);
55 }
56 }
57
58 StringRef llvm::getEnumName(MVT::SimpleValueType T) {
59 switch (T) {
60 case MVT::Other: return "MVT::Other";
61 case MVT::i1: return "MVT::i1";
62 case MVT::i8: return "MVT::i8";
63 case MVT::i16: return "MVT::i16";
64 case MVT::i32: return "MVT::i32";
65 case MVT::i64: return "MVT::i64";
66 case MVT::i128: return "MVT::i128";
67 case MVT::Any: return "MVT::Any";
68 case MVT::iAny: return "MVT::iAny";
69 case MVT::fAny: return "MVT::fAny";
70 case MVT::vAny: return "MVT::vAny";
71 case MVT::f16: return "MVT::f16";
72 case MVT::f32: return "MVT::f32";
73 case MVT::f64: return "MVT::f64";
74 case MVT::f80: return "MVT::f80";
75 case MVT::f128: return "MVT::f128";
76 case MVT::ppcf128: return "MVT::ppcf128";
77 case MVT::x86mmx: return "MVT::x86mmx";
78 case MVT::Glue: return "MVT::Glue";
79 case MVT::isVoid: return "MVT::isVoid";
80 case MVT::v1i1: return "MVT::v1i1";
81 case MVT::v2i1: return "MVT::v2i1";
82 case MVT::v4i1: return "MVT::v4i1";
83 case MVT::v8i1: return "MVT::v8i1";
84 case MVT::v16i1: return "MVT::v16i1";
85 case MVT::v32i1: return "MVT::v32i1";
86 case MVT::v64i1: return "MVT::v64i1";
87 case MVT::v128i1: return "MVT::v128i1";
88 case MVT::v512i1: return "MVT::v512i1";
89 case MVT::v1024i1: return "MVT::v1024i1";
90 case MVT::v1i8: return "MVT::v1i8";
91 case MVT::v2i8: return "MVT::v2i8";
92 case MVT::v4i8: return "MVT::v4i8";
93 case MVT::v8i8: return "MVT::v8i8";
94 case MVT::v16i8: return "MVT::v16i8";
95 case MVT::v32i8: return "MVT::v32i8";
96 case MVT::v64i8: return "MVT::v64i8";
97 case MVT::v128i8: return "MVT::v128i8";
98 case MVT::v256i8: return "MVT::v256i8";
99 case MVT::v1i16: return "MVT::v1i16";
100 case MVT::v2i16: return "MVT::v2i16";
101 case MVT::v4i16: return "MVT::v4i16";
102 case MVT::v8i16: return "MVT::v8i16";
103 case MVT::v16i16: return "MVT::v16i16";
104 case MVT::v32i16: return "MVT::v32i16";
105 case MVT::v64i16: return "MVT::v64i16";
106 case MVT::v128i16: return "MVT::v128i16";
107 case MVT::v1i32: return "MVT::v1i32";
108 case MVT::v2i32: return "MVT::v2i32";
109 case MVT::v3i32: return "MVT::v3i32";
110 case MVT::v4i32: return "MVT::v4i32";
111 case MVT::v5i32: return "MVT::v5i32";
112 case MVT::v8i32: return "MVT::v8i32";
113 case MVT::v16i32: return "MVT::v16i32";
114 case MVT::v32i32: return "MVT::v32i32";
115 case MVT::v64i32: return "MVT::v64i32";
116 case MVT::v128i32: return "MVT::v128i32";
117 case MVT::v256i32: return "MVT::v256i32";
118 case MVT::v512i32: return "MVT::v512i32";
119 case MVT::v1024i32: return "MVT::v1024i32";
120 case MVT::v2048i32: return "MVT::v2048i32";
121 case MVT::v1i64: return "MVT::v1i64";
122 case MVT::v2i64: return "MVT::v2i64";
123 case MVT::v4i64: return "MVT::v4i64";
124 case MVT::v8i64: return "MVT::v8i64";
125 case MVT::v16i64: return "MVT::v16i64";
126 case MVT::v32i64: return "MVT::v32i64";
127 case MVT::v1i128: return "MVT::v1i128";
128 case MVT::v2f16: return "MVT::v2f16";
129 case MVT::v4f16: return "MVT::v4f16";
130 case MVT::v8f16: return "MVT::v8f16";
131 case MVT::v1f32: return "MVT::v1f32";
132 case MVT::v2f32: return "MVT::v2f32";
133 case MVT::v3f32: return "MVT::v3f32";
134 case MVT::v4f32: return "MVT::v4f32";
135 case MVT::v5f32: return "MVT::v5f32";
136 case MVT::v8f32: return "MVT::v8f32";
137 case MVT::v16f32: return "MVT::v16f32";
138 case MVT::v32f32: return "MVT::v32f32";
139 case MVT::v64f32: return "MVT::v64f32";
140 case MVT::v128f32: return "MVT::v128f32";
141 case MVT::v256f32: return "MVT::v256f32";
142 case MVT::v512f32: return "MVT::v512f32";
143 case MVT::v1024f32: return "MVT::v1024f32";
144 case MVT::v2048f32: return "MVT::v2048f32";
145 case MVT::v1f64: return "MVT::v1f64";
146 case MVT::v2f64: return "MVT::v2f64";
147 case MVT::v4f64: return "MVT::v4f64";
148 case MVT::v8f64: return "MVT::v8f64";
149 case MVT::nxv1i1: return "MVT::nxv1i1";
150 case MVT::nxv2i1: return "MVT::nxv2i1";
151 case MVT::nxv4i1: return "MVT::nxv4i1";
152 case MVT::nxv8i1: return "MVT::nxv8i1";
153 case MVT::nxv16i1: return "MVT::nxv16i1";
154 case MVT::nxv32i1: return "MVT::nxv32i1";
155 case MVT::nxv1i8: return "MVT::nxv1i8";
156 case MVT::nxv2i8: return "MVT::nxv2i8";
157 case MVT::nxv4i8: return "MVT::nxv4i8";
158 case MVT::nxv8i8: return "MVT::nxv8i8";
159 case MVT::nxv16i8: return "MVT::nxv16i8";
160 case MVT::nxv32i8: return "MVT::nxv32i8";
161 case MVT::nxv1i16: return "MVT::nxv1i16";
162 case MVT::nxv2i16: return "MVT::nxv2i16";
163 case MVT::nxv4i16: return "MVT::nxv4i16";
164 case MVT::nxv8i16: return "MVT::nxv8i16";
165 case MVT::nxv16i16: return "MVT::nxv16i16";
166 case MVT::nxv32i16: return "MVT::nxv32i16";
167 case MVT::nxv1i32: return "MVT::nxv1i32";
168 case MVT::nxv2i32: return "MVT::nxv2i32";
169 case MVT::nxv4i32: return "MVT::nxv4i32";
170 case MVT::nxv8i32: return "MVT::nxv8i32";
171 case MVT::nxv16i32: return "MVT::nxv16i32";
172 case MVT::nxv1i64: return "MVT::nxv1i64";
173 case MVT::nxv2i64: return "MVT::nxv2i64";
174 case MVT::nxv4i64: return "MVT::nxv4i64";
175 case MVT::nxv8i64: return "MVT::nxv8i64";
176 case MVT::nxv16i64: return "MVT::nxv16i64";
177 case MVT::nxv2f16: return "MVT::nxv2f16";
178 case MVT::nxv4f16: return "MVT::nxv4f16";
179 case MVT::nxv8f16: return "MVT::nxv8f16";
180 case MVT::nxv1f32: return "MVT::nxv1f32";
181 case MVT::nxv2f32: return "MVT::nxv2f32";
182 case MVT::nxv4f32: return "MVT::nxv4f32";
183 case MVT::nxv8f32: return "MVT::nxv8f32";
184 case MVT::nxv16f32: return "MVT::nxv16f32";
185 case MVT::nxv1f64: return "MVT::nxv1f64";
186 case MVT::nxv2f64: return "MVT::nxv2f64";
187 case MVT::nxv4f64: return "MVT::nxv4f64";
188 case MVT::nxv8f64: return "MVT::nxv8f64";
189 case MVT::token: return "MVT::token";
190 case MVT::Metadata: return "MVT::Metadata";
191 case MVT::iPTR: return "MVT::iPTR";
192 case MVT::iPTRAny: return "MVT::iPTRAny";
193 case MVT::Untyped: return "MVT::Untyped";
194 case MVT::exnref: return "MVT::exnref";
195 default: llvm_unreachable("ILLEGAL VALUE TYPE!");
196 }
197 }
198
199 /// getQualifiedName - Return the name of the specified record, with a
200 /// namespace qualifier if the record contains one.
201 ///
202 std::string llvm::getQualifiedName(const Record *R) {
203 std::string Namespace;
204 if (R->getValue("Namespace"))
205 Namespace = R->getValueAsString("Namespace");
206 if (Namespace.empty()) return R->getName();
207 return Namespace + "::" + R->getName().str();
208 }
209
210
211 /// getTarget - Return the current instance of the Target class.
212 ///
213 CodeGenTarget::CodeGenTarget(RecordKeeper &records)
214 : Records(records), CGH(records) {
215 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
216 if (Targets.size() == 0)
217 PrintFatalError("ERROR: No 'Target' subclasses defined!");
218 if (Targets.size() != 1)
219 PrintFatalError("ERROR: Multiple subclasses of Target defined!");
220 TargetRec = Targets[0];
221 }
222
223 CodeGenTarget::~CodeGenTarget() {
224 }
225
226 const StringRef CodeGenTarget::getName() const {
227 return TargetRec->getName();
228 }
229
230 StringRef CodeGenTarget::getInstNamespace() const {
231 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
232 // Make sure not to pick up "TargetOpcode" by accidentally getting
233 // the namespace off the PHI instruction or something.
234 if (Inst->Namespace != "TargetOpcode")
235 return Inst->Namespace;
236 }
237
238 return "";
239 }
240
241 Record *CodeGenTarget::getInstructionSet() const {
242 return TargetRec->getValueAsDef("InstructionSet");
243 }
244
245 bool CodeGenTarget::getAllowRegisterRenaming() const {
246 return TargetRec->getValueAsInt("AllowRegisterRenaming");
247 }
248
249 /// getAsmParser - Return the AssemblyParser definition for this target.
250 ///
251 Record *CodeGenTarget::getAsmParser() const {
252 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
253 if (AsmParserNum >= LI.size())
254 PrintFatalError("Target does not have an AsmParser #" +
255 Twine(AsmParserNum) + "!");
256 return LI[AsmParserNum];
257 }
258
259 /// getAsmParserVariant - Return the AssmblyParserVariant definition for
260 /// this target.
261 ///
262 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
263 std::vector<Record*> LI =
264 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
265 if (i >= LI.size())
266 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
267 "!");
268 return LI[i];
269 }
270
271 /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
272 /// available for this target.
273 ///
274 unsigned CodeGenTarget::getAsmParserVariantCount() const {
275 std::vector<Record*> LI =
276 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
277 return LI.size();
278 }
279
280 /// getAsmWriter - Return the AssemblyWriter definition for this target.
281 ///
282 Record *CodeGenTarget::getAsmWriter() const {
283 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
284 if (AsmWriterNum >= LI.size())
285 PrintFatalError("Target does not have an AsmWriter #" +
286 Twine(AsmWriterNum) + "!");
287 return LI[AsmWriterNum];
288 }
289
290 CodeGenRegBank &CodeGenTarget::getRegBank() const {
291 if (!RegBank)
292 RegBank = llvm::make_unique<CodeGenRegBank>(Records, getHwModes());
293 return *RegBank;
294 }
295
296 void CodeGenTarget::ReadRegAltNameIndices() const {
297 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
298 llvm::sort(RegAltNameIndices, LessRecord());
299 }
300
301 /// getRegisterByName - If there is a register with the specific AsmName,
302 /// return it.
303 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
304 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
305 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
306 if (I == Regs.end())
307 return nullptr;
308 return I->second;
309 }
310
311 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
312 const {
313 const CodeGenRegister *Reg = getRegBank().getReg(R);
314 std::vector<ValueTypeByHwMode> Result;
315 for (const auto &RC : getRegBank().getRegClasses()) {
316 if (RC.contains(Reg)) {
317 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
318 Result.insert(Result.end(), InVTs.begin(), InVTs.end());
319 }
320 }
321
322 // Remove duplicates.
323 llvm::sort(Result);
324 Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
325 return Result;
326 }
327
328
329 void CodeGenTarget::ReadLegalValueTypes() const {
330 for (const auto &RC : getRegBank().getRegClasses())
331 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
332
333 // Remove duplicates.
334 llvm::sort(LegalValueTypes);
335 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
336 LegalValueTypes.end()),
337 LegalValueTypes.end());
338 }
339
340 CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
341 if (!SchedModels)
342 SchedModels = llvm::make_unique<CodeGenSchedModels>(Records, *this);
343 return *SchedModels;
344 }
345
346 void CodeGenTarget::ReadInstructions() const {
347 NamedRegionTimer T("Read Instructions", "Time spent reading instructions",
348 "CodeGenTarget", "CodeGenTarget", TimeRegions);
349 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
350 if (Insts.size() <= 2)
351 PrintFatalError("No 'Instruction' subclasses defined!");
352
353 // Parse the instructions defined in the .td file.
354 for (unsigned i = 0, e = Insts.size(); i != e; ++i)
355 Instructions[Insts[i]] = llvm::make_unique<CodeGenInstruction>(Insts[i]);
356 }
357
358 static const CodeGenInstruction *
359 GetInstByName(const char *Name,
360 const DenseMap<const Record*,
361 std::unique_ptr<CodeGenInstruction>> &Insts,
362 RecordKeeper &Records) {
363 const Record *Rec = Records.getDef(Name);
364
365 const auto I = Insts.find(Rec);
366 if (!Rec || I == Insts.end())
367 PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
368 return I->second.get();
369 }
370
371 static const char *const FixedInstrs[] = {
372 #define HANDLE_TARGET_OPCODE(OPC) #OPC,
373 #include "llvm/Support/TargetOpcodes.def"
374 nullptr};
375
376 unsigned CodeGenTarget::getNumFixedInstructions() {
377 return array_lengthof(FixedInstrs) - 1;
378 }
379
380 /// Return all of the instructions defined by the target, ordered by
381 /// their enum value.
382 void CodeGenTarget::ComputeInstrsByEnum() const {
383 const auto &Insts = getInstructions();
384 for (const char *const *p = FixedInstrs; *p; ++p) {
385 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
386 assert(Instr && "Missing target independent instruction");
387 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
388 InstrsByEnum.push_back(Instr);
389 }
390 unsigned EndOfPredefines = InstrsByEnum.size();
391 assert(EndOfPredefines == getNumFixedInstructions() &&
392 "Missing generic opcode");
393
394 for (const auto &I : Insts) {
395 const CodeGenInstruction *CGI = I.second.get();
396 if (CGI->Namespace != "TargetOpcode") {
397 InstrsByEnum.push_back(CGI);
398 if (CGI->TheDef->getValueAsBit("isPseudo"))
399 ++NumPseudoInstructions;
400 }
401 }
402
403 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
404
405 // All of the instructions are now in random order based on the map iteration.
406 llvm::sort(
407 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
408 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
409 const auto &D1 = *Rec1->TheDef;
410 const auto &D2 = *Rec2->TheDef;
411 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
412 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
413 });
414 }
415
416
417 /// isLittleEndianEncoding - Return whether this target encodes its instruction
418 /// in little-endian format, i.e. bits laid out in the order [0..n]
419 ///
420 bool CodeGenTarget::isLittleEndianEncoding() const {
421 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
422 }
423
424 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
425 /// encodings, reverse the bit order of all instructions.
426 void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
427 if (!isLittleEndianEncoding())
428 return;
429
430 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
431 for (Record *R : Insts) {
432 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
433 R->getValueAsBit("isPseudo"))
434 continue;
435
436 BitsInit *BI = R->getValueAsBitsInit("Inst");
437
438 unsigned numBits = BI->getNumBits();
439
440 SmallVector<Init *, 16> NewBits(numBits);
441
442 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
443 unsigned bitSwapIdx = numBits - bit - 1;
444 Init *OrigBit = BI->getBit(bit);
445 Init *BitSwap = BI->getBit(bitSwapIdx);
446 NewBits[bit] = BitSwap;
447 NewBits[bitSwapIdx] = OrigBit;
448 }
449 if (numBits % 2) {
450 unsigned middle = (numBits + 1) / 2;
451 NewBits[middle] = BI->getBit(middle);
452 }
453
454 BitsInit *NewBI = BitsInit::get(NewBits);
455
456 // Update the bits in reversed order so that emitInstrOpBits will get the
457 // correct endianness.
458 R->getValue("Inst")->setValue(NewBI);
459 }
460 }
461
462 /// guessInstructionProperties - Return true if it's OK to guess instruction
463 /// properties instead of raising an error.
464 ///
465 /// This is configurable as a temporary migration aid. It will eventually be
466 /// permanently false.
467 bool CodeGenTarget::guessInstructionProperties() const {
468 return getInstructionSet()->getValueAsBit("guessInstructionProperties");
469 }
470
471 //===----------------------------------------------------------------------===//
472 // ComplexPattern implementation
473 //
474 ComplexPattern::ComplexPattern(Record *R) {
475 Ty = ::getValueType(R->getValueAsDef("Ty"));
476 NumOperands = R->getValueAsInt("NumOperands");
477 SelectFunc = R->getValueAsString("SelectFunc");
478 RootNodes = R->getValueAsListOfDefs("RootNodes");
479
480 // FIXME: This is a hack to statically increase the priority of patterns which
481 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
482 // possible pattern match we'll need to dynamically calculate the complexity
483 // of all patterns a dag can potentially map to.
484 int64_t RawComplexity = R->getValueAsInt("Complexity");
485 if (RawComplexity == -1)
486 Complexity = NumOperands * 3;
487 else
488 Complexity = RawComplexity;
489
490 // FIXME: Why is this different from parseSDPatternOperatorProperties?
491 // Parse the properties.
492 Properties = 0;
493 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
494 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
495 if (PropList[i]->getName() == "SDNPHasChain") {
496 Properties |= 1 << SDNPHasChain;
497 } else if (PropList[i]->getName() == "SDNPOptInGlue") {
498 Properties |= 1 << SDNPOptInGlue;
499 } else if (PropList[i]->getName() == "SDNPMayStore") {
500 Properties |= 1 << SDNPMayStore;
501 } else if (PropList[i]->getName() == "SDNPMayLoad") {
502 Properties |= 1 << SDNPMayLoad;
503 } else if (PropList[i]->getName() == "SDNPSideEffect") {
504 Properties |= 1 << SDNPSideEffect;
505 } else if (PropList[i]->getName() == "SDNPMemOperand") {
506 Properties |= 1 << SDNPMemOperand;
507 } else if (PropList[i]->getName() == "SDNPVariadic") {
508 Properties |= 1 << SDNPVariadic;
509 } else if (PropList[i]->getName() == "SDNPWantRoot") {
510 Properties |= 1 << SDNPWantRoot;
511 } else if (PropList[i]->getName() == "SDNPWantParent") {
512 Properties |= 1 << SDNPWantParent;
513 } else {
514 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" +
515 PropList[i]->getName() +
516 "' on ComplexPattern '" + R->getName() +
517 "'!");
518 }
519 }
520
521 //===----------------------------------------------------------------------===//
522 // CodeGenIntrinsic Implementation
523 //===----------------------------------------------------------------------===//
524
525 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC,
526 bool TargetOnly) {
527 std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic");
528
529 Intrinsics.reserve(Defs.size());
530
531 for (unsigned I = 0, e = Defs.size(); I != e; ++I) {
532 bool isTarget = Defs[I]->getValueAsBit("isTarget");
533 if (isTarget == TargetOnly)
534 Intrinsics.push_back(CodeGenIntrinsic(Defs[I]));
535 }
536 llvm::sort(Intrinsics,
537 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
538 return std::tie(LHS.TargetPrefix, LHS.Name) <
539 std::tie(RHS.TargetPrefix, RHS.Name);
540 });
541 Targets.push_back({"", 0, 0});
542 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
543 if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
544 Targets.back().Count = I - Targets.back().Offset;
545 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
546 }
547 Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
548 }
549
550 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
551 TheDef = R;
552 std::string DefName = R->getName();
553 ArrayRef<SMLoc> DefLoc = R->getLoc();
554 ModRef = ReadWriteMem;
555 Properties = 0;
556 isOverloaded = false;
557 isCommutative = false;
558 canThrow = false;
559 isNoReturn = false;
560 isWillReturn = false;
561 isCold = false;
562 isNoDuplicate = false;
563 isConvergent = false;
564 isSpeculatable = false;
565 hasSideEffects = false;
566
567 if (DefName.size() <= 4 ||
568 std::string(DefName.begin(), DefName.begin() + 4) != "int_")
569 PrintFatalError(DefLoc,
570 "Intrinsic '" + DefName + "' does not start with 'int_'!");
571
572 EnumName = std::string(DefName.begin()+4, DefName.end());
573
574 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
575 GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
576 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field.
577 MSBuiltinName = R->getValueAsString("MSBuiltinName");
578
579 TargetPrefix = R->getValueAsString("TargetPrefix");
580 Name = R->getValueAsString("LLVMName");
581
582 if (Name == "") {
583 // If an explicit name isn't specified, derive one from the DefName.
584 Name = "llvm.";
585
586 for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
587 Name += (EnumName[i] == '_') ? '.' : EnumName[i];
588 } else {
589 // Verify it starts with "llvm.".
590 if (Name.size() <= 5 ||
591 std::string(Name.begin(), Name.begin() + 5) != "llvm.")
592 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
593 "'s name does not start with 'llvm.'!");
594 }
595
596 // If TargetPrefix is specified, make sure that Name starts with
597 // "llvm.<targetprefix>.".
598 if (!TargetPrefix.empty()) {
599 if (Name.size() < 6+TargetPrefix.size() ||
600 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
601 != (TargetPrefix + "."))
602 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
603 "' does not start with 'llvm." +
604 TargetPrefix + ".'!");
605 }
606
607 ListInit *RetTypes = R->getValueAsListInit("RetTypes");
608 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes");
609
610 // First collate a list of overloaded types.
611 std::vector<MVT::SimpleValueType> OverloadedVTs;
612 for (ListInit *TypeList : {RetTypes, ParamTypes}) {
613 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
614 Record *TyEl = TypeList->getElementAsRecord(i);
615 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
616
617 if (TyEl->isSubClassOf("LLVMMatchType"))
618 continue;
619
620 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT"));
621 if (MVT(VT).isOverloaded()) {
622 OverloadedVTs.push_back(VT);
623 isOverloaded = true;
624 }
625 }
626 }
627
628 // Parse the list of return types.
629 ListInit *TypeList = RetTypes;
630 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
631 Record *TyEl = TypeList->getElementAsRecord(i);
632 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
633 MVT::SimpleValueType VT;
634 if (TyEl->isSubClassOf("LLVMMatchType")) {
635 unsigned MatchTy = TyEl->getValueAsInt("Number");
636 assert(MatchTy < OverloadedVTs.size() &&
637 "Invalid matching number!");
638 VT = OverloadedVTs[MatchTy];
639 // It only makes sense to use the extended and truncated vector element
640 // variants with iAny types; otherwise, if the intrinsic is not
641 // overloaded, all the types can be specified directly.
642 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
643 !TyEl->isSubClassOf("LLVMTruncatedType")) ||
644 VT == MVT::iAny || VT == MVT::vAny) &&
645 "Expected iAny or vAny type");
646 } else {
647 VT = getValueType(TyEl->getValueAsDef("VT"));
648 }
649
650 // Reject invalid types.
651 if (VT == MVT::isVoid)
652 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
653 " has void in result type list!");
654
655 IS.RetVTs.push_back(VT);
656 IS.RetTypeDefs.push_back(TyEl);
657 }
658
659 // Parse the list of parameter types.
660 TypeList = ParamTypes;
661 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
662 Record *TyEl = TypeList->getElementAsRecord(i);
663 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
664 MVT::SimpleValueType VT;
665 if (TyEl->isSubClassOf("LLVMMatchType")) {
666 unsigned MatchTy = TyEl->getValueAsInt("Number");
667 if (MatchTy >= OverloadedVTs.size()) {
668 PrintError(R->getLoc(),
669 "Parameter #" + Twine(i) + " has out of bounds matching "
670 "number " + Twine(MatchTy));
671 PrintFatalError(DefLoc,
672 Twine("ParamTypes is ") + TypeList->getAsString());
673 }
674 VT = OverloadedVTs[MatchTy];
675 // It only makes sense to use the extended and truncated vector element
676 // variants with iAny types; otherwise, if the intrinsic is not
677 // overloaded, all the types can be specified directly.
678 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
679 !TyEl->isSubClassOf("LLVMTruncatedType") &&
680 !TyEl->isSubClassOf("LLVMScalarOrSameVectorWidth")) ||
681 VT == MVT::iAny || VT == MVT::vAny) &&
682 "Expected iAny or vAny type");
683 } else
684 VT = getValueType(TyEl->getValueAsDef("VT"));
685
686 // Reject invalid types.
687 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
688 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
689 " has void in result type list!");
690
691 IS.ParamVTs.push_back(VT);
692 IS.ParamTypeDefs.push_back(TyEl);
693 }
694
695 // Parse the intrinsic properties.
696 ListInit *PropList = R->getValueAsListInit("IntrProperties");
697 for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
698 Record *Property = PropList->getElementAsRecord(i);
699 assert(Property->isSubClassOf("IntrinsicProperty") &&
700 "Expected a property!");
701
702 if (Property->getName() == "IntrNoMem")
703 ModRef = NoMem;
704 else if (Property->getName() == "IntrReadMem")
705 ModRef = ModRefBehavior(ModRef & ~MR_Mod);
706 else if (Property->getName() == "IntrWriteMem")
707 ModRef = ModRefBehavior(ModRef & ~MR_Ref);
708 else if (Property->getName() == "IntrArgMemOnly")
709 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem);
710 else if (Property->getName() == "IntrInaccessibleMemOnly")
711 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem);
712 else if (Property->getName() == "IntrInaccessibleMemOrArgMemOnly")
713 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem |
714 MR_InaccessibleMem);
715 else if (Property->getName() == "Commutative")
716 isCommutative = true;
717 else if (Property->getName() == "Throws")
718 canThrow = true;
719 else if (Property->getName() == "IntrNoDuplicate")
720 isNoDuplicate = true;
721 else if (Property->getName() == "IntrConvergent")
722 isConvergent = true;
723 else if (Property->getName() == "IntrNoReturn")
724 isNoReturn = true;
725 else if (Property->getName() == "IntrWillReturn")
726 isWillReturn = true;
727 else if (Property->getName() == "IntrCold")
728 isCold = true;
729 else if (Property->getName() == "IntrSpeculatable")
730 isSpeculatable = true;
731 else if (Property->getName() == "IntrHasSideEffects")
732 hasSideEffects = true;
733 else if (Property->isSubClassOf("NoCapture")) {
734 unsigned ArgNo = Property->getValueAsInt("ArgNo");
735 ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
736 } else if (Property->isSubClassOf("Returned")) {
737 unsigned ArgNo = Property->getValueAsInt("ArgNo");
738 ArgumentAttributes.push_back(std::make_pair(ArgNo, Returned));
739 } else if (Property->isSubClassOf("ReadOnly")) {
740 unsigned ArgNo = Property->getValueAsInt("ArgNo");
741 ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadOnly));
742 } else if (Property->isSubClassOf("WriteOnly")) {
743 unsigned ArgNo = Property->getValueAsInt("ArgNo");
744 ArgumentAttributes.push_back(std::make_pair(ArgNo, WriteOnly));
745 } else if (Property->isSubClassOf("ReadNone")) {
746 unsigned ArgNo = Property->getValueAsInt("ArgNo");
747 ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadNone));
748 } else if (Property->isSubClassOf("ImmArg")) {
749 unsigned ArgNo = Property->getValueAsInt("ArgNo");
750 ArgumentAttributes.push_back(std::make_pair(ArgNo, ImmArg));
751 } else
752 llvm_unreachable("Unknown property!");
753 }
754
755 // Also record the SDPatternOperator Properties.
756 Properties = parseSDPatternOperatorProperties(R);
757
758 // Sort the argument attributes for later benefit.
759 llvm::sort(ArgumentAttributes);
760 }
The low level virtual machine