lib/Target/ARM/ARM.h

   1 //===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the "Instituto Nokia de Tecnologia" and
   6 // is distributed under the University of Illinois Open Source
   7 // License. See LICENSE.TXT for details.
   8 //
   9 //===----------------------------------------------------------------------===//
  10 //
  11 // This file contains the entry points for global functions defined in the LLVM
  12 // ARM back-end.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef TARGET_ARM_H
  17 #define TARGET_ARM_H
  18
  19 #include <iosfwd>
  20 #include <cassert>
  21
  22 namespace llvm {
  23
  24 class ARMTargetMachine;
  25 class FunctionPass;
  26 class MachineCodeEmitter;
  27
  28 // Enums corresponding to ARM condition codes
  29 namespace ARMCC {
  30   enum CondCodes {
  31     EQ,
  32     NE,
  33     HS,
  34     LO,
  35     MI,
  36     PL,
  37     VS,
  38     VC,
  39     HI,
  40     LS,
  41     GE,
  42     LT,
  43     GT,
  44     LE,
  45     AL
  46   };
  47
  48   inline static CondCodes getOppositeCondition(CondCodes CC){
  49     switch (CC) {
  50     default: assert(0 && "Unknown condition code");
  51     case EQ: return NE;
  52     case NE: return EQ;
  53     case HS: return LO;
  54     case LO: return HS;
  55     case MI: return PL;
  56     case PL: return MI;
  57     case VS: return VC;
  58     case VC: return VS;
  59     case HI: return LS;
  60     case LS: return HI;
  61     case GE: return LT;
  62     case LT: return GE;
  63     case GT: return LE;
  64     case LE: return GT;
  65     }
  66   }
  67 }
  68
  69 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
  70   switch (CC) {
  71   default: assert(0 && "Unknown condition code");
  72   case ARMCC::EQ:  return "eq";
  73   case ARMCC::NE:  return "ne";
  74   case ARMCC::HS:  return "hs";
  75   case ARMCC::LO:  return "lo";
  76   case ARMCC::MI:  return "mi";
  77   case ARMCC::PL:  return "pl";
  78   case ARMCC::VS:  return "vs";
  79   case ARMCC::VC:  return "vc";
  80   case ARMCC::HI:  return "hi";
  81   case ARMCC::LS:  return "ls";
  82   case ARMCC::GE:  return "ge";
  83   case ARMCC::LT:  return "lt";
  84   case ARMCC::GT:  return "gt";
  85   case ARMCC::LE:  return "le";
  86   case ARMCC::AL:  return "al";
  87   }
  88 }
  89
  90 FunctionPass *createARMISelDag(ARMTargetMachine &TM);
  91 FunctionPass *createARMCodePrinterPass(std::ostream &O, ARMTargetMachine &TM);
  92 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
  93                                        MachineCodeEmitter &MCE);
  94 FunctionPass *createARMLoadStoreOptimizationPass();
  95 FunctionPass *createARMConstantIslandPass();
  96
  97 } // end namespace llvm;
  98
  99 // Defines symbolic names for ARM registers.  This defines a mapping from
 100 // register name to register number.
 101 //
 102 #include "ARMGenRegisterNames.inc"
 103
 104 // Defines symbolic names for the ARM instructions.
 105 //
 106 #include "ARMGenInstrNames.inc"
 107
 108
 109 #endif