lib/Target/IA64/IA64ISelDAGToDAG.cpp

   1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by Duraid Madina and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a pattern matching instruction selector for IA64,
  11 // converting a legalized dag to an IA64 dag.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "ia64-codegen"
  16 #include "IA64.h"
  17 #include "IA64TargetMachine.h"
  18 #include "IA64ISelLowering.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/SSARegMap.h"
  22 #include "llvm/CodeGen/SelectionDAG.h"
  23 #include "llvm/CodeGen/SelectionDAGISel.h"
  24 #include "llvm/Target/TargetOptions.h"
  25 #include "llvm/Constants.h"
  26 #include "llvm/GlobalValue.h"
  27 #include "llvm/Intrinsics.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/MathExtras.h"
  30 #include <queue>
  31 #include <set>
  32 using namespace llvm;
  33
  34 namespace {
  35   //===--------------------------------------------------------------------===//
  36   /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
  37   /// instructions for SelectionDAG operations.
  38   ///
  39   class IA64DAGToDAGISel : public SelectionDAGISel {
  40     IA64TargetLowering IA64Lowering;
  41     unsigned GlobalBaseReg;
  42   public:
  43     IA64DAGToDAGISel(IA64TargetMachine &TM)
  44       : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
  45
  46     virtual bool runOnFunction(Function &Fn) {
  47       // Make sure we re-emit a set of the global base reg if necessary
  48       GlobalBaseReg = 0;
  49       return SelectionDAGISel::runOnFunction(Fn);
  50     }
  51
  52     /// getI64Imm - Return a target constant with the specified value, of type
  53     /// i64.
  54     inline SDOperand getI64Imm(uint64_t Imm) {
  55       return CurDAG->getTargetConstant(Imm, MVT::i64);
  56     }
  57
  58     /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
  59     /// base register.  Return the virtual register that holds this value.
  60     // SDOperand getGlobalBaseReg(); TODO: hmm
  61
  62     // Select - Convert the specified operand from a target-independent to a
  63     // target-specific node if it hasn't already been changed.
  64     SDNode *Select(SDOperand N);
  65
  66     SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
  67                                    unsigned OCHi, unsigned OCLo,
  68                                    bool IsArithmetic = false,
  69                                    bool Negate = false);
  70     SDNode *SelectBitfieldInsert(SDNode *N);
  71
  72     /// SelectCC - Select a comparison of the specified values with the
  73     /// specified condition code, returning the CR# of the expression.
  74     SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
  75
  76     /// SelectAddr - Given the specified address, return the two operands for a
  77     /// load/store instruction, and return true if it should be an indexed [r+r]
  78     /// operation.
  79     bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
  80
  81     /// InstructionSelectBasicBlock - This callback is invoked by
  82     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
  83     virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
  84
  85     virtual const char *getPassName() const {
  86       return "IA64 (Itanium) DAG->DAG Instruction Selector";
  87     }
  88
  89 // Include the pieces autogenerated from the target description.
  90 #include "IA64GenDAGISel.inc"
  91
  92 private:
  93     SDNode *SelectDIV(SDOperand Op);
  94   };
  95 }
  96
  97 /// InstructionSelectBasicBlock - This callback is invoked by
  98 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
  99 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
 100   DEBUG(BB->dump());
 101
 102   // Select target instructions for the DAG.
 103   DAG.setRoot(SelectRoot(DAG.getRoot()));
 104   DAG.RemoveDeadNodes();
 105
 106   // Emit machine code to BB.
 107   ScheduleAndEmitDAG(DAG);
 108 }
 109
 110 SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
 111   SDNode *N = Op.Val;
 112   SDOperand Chain = N->getOperand(0);
 113   SDOperand Tmp1 = N->getOperand(0);
 114   SDOperand Tmp2 = N->getOperand(1);
 115   AddToISelQueue(Chain);
 116
 117   AddToISelQueue(Tmp1);
 118   AddToISelQueue(Tmp2);
 119
 120   bool isFP=false;
 121
 122   if(MVT::isFloatingPoint(Tmp1.getValueType()))
 123     isFP=true;
 124
 125   bool isModulus=false; // is it a division or a modulus?
 126   bool isSigned=false;
 127
 128   switch(N->getOpcode()) {
 129     case ISD::FDIV:
 130     case ISD::SDIV:  isModulus=false; isSigned=true;  break;
 131     case ISD::UDIV:  isModulus=false; isSigned=false; break;
 132     case ISD::FREM:
 133     case ISD::SREM:  isModulus=true;  isSigned=true;  break;
 134     case ISD::UREM:  isModulus=true;  isSigned=false; break;
 135   }
 136
 137   // TODO: check for integer divides by powers of 2 (or other simple patterns?)
 138
 139     SDOperand TmpPR, TmpPR2;
 140     SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
 141     SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
 142     SDNode *Result;
 143
 144     // we'll need copies of F0 and F1
 145     SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
 146     SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
 147
 148     // OK, emit some code:
 149
 150     if(!isFP) {
 151       // first, load the inputs into FP regs.
 152       TmpF1 =
 153         SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
 154       Chain = TmpF1.getValue(1);
 155       TmpF2 =
 156         SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
 157       Chain = TmpF2.getValue(1);
 158
 159       // next, convert the inputs to FP
 160       if(isSigned) {
 161         TmpF3 =
 162           SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
 163         Chain = TmpF3.getValue(1);
 164         TmpF4 =
 165           SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
 166         Chain = TmpF4.getValue(1);
 167       } else { // is unsigned
 168         TmpF3 =
 169           SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
 170         Chain = TmpF3.getValue(1);
 171         TmpF4 =
 172           SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
 173         Chain = TmpF4.getValue(1);
 174       }
 175
 176     } else { // this is an FP divide/remainder, so we 'leak' some temp
 177              // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
 178       TmpF3=Tmp1;
 179       TmpF4=Tmp2;
 180     }
 181
 182     // we start by computing an approximate reciprocal (good to 9 bits?)
 183     // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
 184     if(isFP)
 185       TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
 186                                               TmpF3, TmpF4), 0);
 187     else
 188       TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
 189                                               TmpF3, TmpF4), 0);
 190
 191     TmpPR = TmpF5.getValue(1);
 192     Chain = TmpF5.getValue(2);
 193
 194     SDOperand minusB;
 195     if(isModulus) { // for remainders, it'll be handy to have
 196                              // copies of -input_b
 197       minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
 198                   CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
 199       Chain = minusB.getValue(1);
 200     }
 201
 202     SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
 203
 204     SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
 205     TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
 206                                             OpsE0, 4), 0);
 207     Chain = TmpE0.getValue(1);
 208     SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
 209     TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 210                                             OpsY1, 4), 0);
 211     Chain = TmpY1.getValue(1);
 212     SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
 213     TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 214                                             OpsE1, 4), 0);
 215     Chain = TmpE1.getValue(1);
 216     SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
 217     TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 218                                             OpsY2, 4), 0);
 219     Chain = TmpY2.getValue(1);
 220
 221     if(isFP) { // if this is an FP divide, we finish up here and exit early
 222       if(isModulus)
 223         assert(0 && "Sorry, try another FORTRAN compiler.");
 224
 225       SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
 226
 227       SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
 228       TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 229                                               OpsE2, 4), 0);
 230       Chain = TmpE2.getValue(1);
 231       SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
 232       TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 233                                               OpsY3, 4), 0);
 234       Chain = TmpY3.getValue(1);
 235       SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
 236       TmpQ0 =
 237         SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
 238                                         OpsQ0, 4), 0);
 239       Chain = TmpQ0.getValue(1);
 240       SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
 241       TmpR0 =
 242         SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
 243                                         OpsR0, 4), 0);
 244       Chain = TmpR0.getValue(1);
 245
 246 // we want Result to have the same target register as the frcpa, so
 247 // we two-address hack it. See the comment "for this to work..." on
 248 // page 48 of Intel application note #245415
 249       SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
 250       Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
 251                                      Ops, 5);
 252       Chain = SDOperand(Result, 1);
 253       return Result; // XXX: early exit!
 254     } else { // this is *not* an FP divide, so there's a bit left to do:
 255
 256       SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
 257
 258       SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
 259       TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 260                                               OpsQ2, 4), 0);
 261       Chain = TmpQ2.getValue(1);
 262       SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
 263       TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
 264                                               OpsR2, 4), 0);
 265       Chain = TmpR2.getValue(1);
 266
 267 // we want TmpQ3 to have the same target register as the frcpa? maybe we
 268 // should two-address hack it. See the comment "for this to work..." on page
 269 // 48 of Intel application note #245415
 270       SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
 271       TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
 272                                          OpsQ3, 5), 0);
 273       Chain = TmpQ3.getValue(1);
 274
 275       // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
 276       // the FPSWA won't be able to help out in the case of large/tiny
 277       // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
 278
 279       if(isSigned)
 280         TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
 281                                                MVT::f64, TmpQ3), 0);
 282       else
 283         TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
 284                                                MVT::f64, TmpQ3), 0);
 285
 286       Chain = TmpQ.getValue(1);
 287
 288       if(isModulus) {
 289         SDOperand FPminusB =
 290           SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
 291         Chain = FPminusB.getValue(1);
 292         SDOperand Remainder =
 293           SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
 294                                           TmpQ, FPminusB, TmpF1), 0);
 295         Chain = Remainder.getValue(1);
 296         Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
 297         Chain = SDOperand(Result, 1);
 298       } else { // just an integer divide
 299         Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
 300         Chain = SDOperand(Result, 1);
 301       }
 302
 303       return Result;
 304     } // wasn't an FP divide
 305 }
 306
 307 // Select - Convert the specified operand from a target-independent to a
 308 // target-specific node if it hasn't already been changed.
 309 SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
 310   SDNode *N = Op.Val;
 311   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
 312       N->getOpcode() < IA64ISD::FIRST_NUMBER)
 313     return NULL;   // Already selected.
 314
 315   switch (N->getOpcode()) {
 316   default: break;
 317
 318   case IA64ISD::BRCALL: { // XXX: this is also a hack!
 319     SDOperand Chain = N->getOperand(0);
 320     SDOperand InFlag;  // Null incoming flag value.
 321
 322     AddToISelQueue(Chain);
 323     if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
 324       InFlag = N->getOperand(2);
 325       AddToISelQueue(InFlag);
 326     }
 327
 328     unsigned CallOpcode;
 329     SDOperand CallOperand;
 330
 331     // if we can call directly, do so
 332     if (GlobalAddressSDNode *GASD =
 333       dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
 334       CallOpcode = IA64::BRCALL_IPREL_GA;
 335       CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
 336     } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
 337       // FIXME: we currently NEED this case for correctness, to avoid
 338       // "non-pic code with imm reloc.n against dynamic symbol" errors
 339     CallOpcode = IA64::BRCALL_IPREL_ES;
 340     CallOperand = N->getOperand(1);
 341   } else {
 342     // otherwise we need to load the function descriptor,
 343     // load the branch target (function)'s entry point and GP,
 344     // branch (call) then restore the GP
 345     SDOperand FnDescriptor = N->getOperand(1);
 346     AddToISelQueue(FnDescriptor);
 347
 348     // load the branch target's entry point [mem] and
 349     // GP value [mem+8]
 350     SDOperand targetEntryPoint=
 351       SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
 352     Chain = targetEntryPoint.getValue(1);
 353     SDOperand targetGPAddr=
 354       SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
 355                                       FnDescriptor,
 356                                       CurDAG->getConstant(8, MVT::i64)), 0);
 357     Chain = targetGPAddr.getValue(1);
 358     SDOperand targetGP =
 359       SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
 360     Chain = targetGP.getValue(1);
 361
 362     Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
 363     InFlag = Chain.getValue(1);
 364     Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
 365     InFlag = Chain.getValue(1);
 366
 367     CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
 368     CallOpcode = IA64::BRCALL_INDIRECT;
 369   }
 370
 371    // Finally, once everything is setup, emit the call itself
 372    if(InFlag.Val)
 373      Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
 374                                              CallOperand, InFlag), 0);
 375    else // there might be no arguments
 376      Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
 377                                              CallOperand, Chain), 0);
 378    InFlag = Chain.getValue(1);
 379
 380    std::vector<SDOperand> CallResults;
 381
 382    CallResults.push_back(Chain);
 383    CallResults.push_back(InFlag);
 384
 385    for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
 386      ReplaceUses(Op.getValue(i), CallResults[i]);
 387    return NULL;
 388   }
 389
 390   case IA64ISD::GETFD: {
 391     SDOperand Input = N->getOperand(0);
 392     AddToISelQueue(Input);
 393     return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
 394   }
 395
 396   case ISD::FDIV:
 397   case ISD::SDIV:
 398   case ISD::UDIV:
 399   case ISD::SREM:
 400   case ISD::UREM:
 401     return SelectDIV(Op);
 402
 403   case ISD::TargetConstantFP: {
 404     SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
 405
 406     SDOperand V;
 407     ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
 408     if (N2->getValueAPF().isPosZero()) {
 409       V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
 410     } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
 411                                   APFloat(+1.0f) : APFloat(+1.0))) {
 412       V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
 413     } else
 414       assert(0 && "Unexpected FP constant!");
 415
 416     ReplaceUses(SDOperand(N, 0), V);
 417     return 0;
 418   }
 419
 420   case ISD::FrameIndex: { // TODO: reduce creepyness
 421     int FI = cast<FrameIndexSDNode>(N)->getIndex();
 422     if (N->hasOneUse())
 423       return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
 424                                   CurDAG->getTargetFrameIndex(FI, MVT::i64));
 425     else
 426       return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
 427                                    CurDAG->getTargetFrameIndex(FI, MVT::i64));
 428   }
 429
 430   case ISD::ConstantPool: { // TODO: nuke the constant pool
 431     // (ia64 doesn't need one)
 432     ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
 433     Constant *C = CP->getConstVal();
 434     SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
 435                                                   CP->getAlignment());
 436     return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
 437                                  CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
 438   }
 439
 440   case ISD::GlobalAddress: {
 441     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
 442     SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
 443     SDOperand Tmp =
 444       SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
 445                                       CurDAG->getRegister(IA64::r1,
 446                                                           MVT::i64), GA), 0);
 447     return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
 448   }
 449
 450 /* XXX
 451    case ISD::ExternalSymbol: {
 452      SDOperand EA = CurDAG->getTargetExternalSymbol(
 453        cast<ExternalSymbolSDNode>(N)->getSymbol(),
 454        MVT::i64);
 455      SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
 456                                            CurDAG->getRegister(IA64::r1,
 457                                                                MVT::i64),
 458                                            EA);
 459      return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
 460    }
 461 */
 462
 463   case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
 464     LoadSDNode *LD = cast<LoadSDNode>(N);
 465     SDOperand Chain = LD->getChain();
 466     SDOperand Address = LD->getBasePtr();
 467     AddToISelQueue(Chain);
 468     AddToISelQueue(Address);
 469
 470     MVT::ValueType TypeBeingLoaded = LD->getLoadedVT();
 471     unsigned Opc;
 472     switch (TypeBeingLoaded) {
 473     default:
 474 #ifndef NDEBUG
 475       N->dump(CurDAG);
 476 #endif
 477       assert(0 && "Cannot load this type!");
 478     case MVT::i1: { // this is a bool
 479       Opc = IA64::LD1; // first we load a byte, then compare for != 0
 480       if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
 481         return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
 482                     SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
 483                                     CurDAG->getRegister(IA64::r0, MVT::i64),
 484                                     Chain);
 485       }
 486       /* otherwise, we want to load a bool into something bigger: LD1
 487          will do that for us, so we just fall through */
 488     }
 489     case MVT::i8:  Opc = IA64::LD1; break;
 490     case MVT::i16: Opc = IA64::LD2; break;
 491     case MVT::i32: Opc = IA64::LD4; break;
 492     case MVT::i64: Opc = IA64::LD8; break;
 493
 494     case MVT::f32: Opc = IA64::LDF4; break;
 495     case MVT::f64: Opc = IA64::LDF8; break;
 496     }
 497
 498     // TODO: comment this
 499     return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
 500                                 Address, Chain);
 501   }
 502
 503   case ISD::STORE: {
 504     StoreSDNode *ST = cast<StoreSDNode>(N);
 505     SDOperand Address = ST->getBasePtr();
 506     SDOperand Chain = ST->getChain();
 507     AddToISelQueue(Address);
 508     AddToISelQueue(Chain);
 509
 510     unsigned Opc;
 511     if (ISD::isNON_TRUNCStore(N)) {
 512       switch (N->getOperand(1).getValueType()) {
 513       default: assert(0 && "unknown type in store");
 514       case MVT::i1: { // this is a bool
 515         Opc = IA64::ST1; // we store either 0 or 1 as a byte
 516         // first load zero!
 517         SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
 518         Chain = Initial.getValue(1);
 519         // then load 1 into the same reg iff the predicate to store is 1
 520         SDOperand Tmp = ST->getValue();
 521         AddToISelQueue(Tmp);
 522         Tmp =
 523           SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
 524                                           CurDAG->getTargetConstant(1, MVT::i64),
 525                                           Tmp), 0);
 526         return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
 527       }
 528       case MVT::i64: Opc = IA64::ST8;  break;
 529       case MVT::f64: Opc = IA64::STF8; break;
 530       }
 531     } else { // Truncating store
 532       switch(ST->getStoredVT()) {
 533       default: assert(0 && "unknown type in truncstore");
 534       case MVT::i8:  Opc = IA64::ST1;  break;
 535       case MVT::i16: Opc = IA64::ST2;  break;
 536       case MVT::i32: Opc = IA64::ST4;  break;
 537       case MVT::f32: Opc = IA64::STF4; break;
 538       }
 539     }
 540
 541     SDOperand N1 = N->getOperand(1);
 542     SDOperand N2 = N->getOperand(2);
 543     AddToISelQueue(N1);
 544     AddToISelQueue(N2);
 545     return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
 546   }
 547
 548   case ISD::BRCOND: {
 549     SDOperand Chain = N->getOperand(0);
 550     SDOperand CC = N->getOperand(1);
 551     AddToISelQueue(Chain);
 552     AddToISelQueue(CC);
 553     MachineBasicBlock *Dest =
 554       cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
 555     //FIXME - we do NOT need long branches all the time
 556     return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
 557                                 CurDAG->getBasicBlock(Dest), Chain);
 558   }
 559
 560   case ISD::CALLSEQ_START:
 561   case ISD::CALLSEQ_END: {
 562     int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
 563     unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
 564       IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
 565     SDOperand N0 = N->getOperand(0);
 566     AddToISelQueue(N0);
 567     return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
 568   }
 569
 570   case ISD::BR:
 571     // FIXME: we don't need long branches all the time!
 572     SDOperand N0 = N->getOperand(0);
 573     AddToISelQueue(N0);
 574     return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
 575                                 N->getOperand(1), N0);
 576   }
 577
 578   return SelectCode(Op);
 579 }
 580
 581
 582 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
 583 /// into an IA64-specific DAG, ready for instruction scheduling.
 584 ///
 585 FunctionPass
 586 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
 587   return new IA64DAGToDAGISel(TM);
 588 }
 589