lib/Target/PowerPC/PPCHazardRecognizers.cpp

   1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by Chris Lattner and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements hazard recognizers for scheduling on PowerPC processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "pre-RA-sched"
  15 #include "PPCHazardRecognizers.h"
  16 #include "PPC.h"
  17 #include "PPCInstrInfo.h"
  18 #include "llvm/Support/Debug.h"
  19 using namespace llvm;
  20
  21 //===----------------------------------------------------------------------===//
  22 // PowerPC 970 Hazard Recognizer
  23 //
  24 // This models the dispatch group formation of the PPC970 processor.  Dispatch
  25 // groups are bundles of up to five instructions that can contain various mixes
  26 // of instructions.  The PPC970 can dispatch a peak of 4 non-branch and one
  27 // branch instruction per-cycle.
  28 //
  29 // There are a number of restrictions to dispatch group formation: some
  30 // instructions can only be issued in the first slot of a dispatch group, & some
  31 // instructions fill an entire dispatch group.  Additionally, only branches can
  32 // issue in the 5th (last) slot.
  33 //
  34 // Finally, there are a number of "structural" hazards on the PPC970.  These
  35 // conditions cause large performance penalties due to misprediction, recovery,
  36 // and replay logic that has to happen.  These cases include setting a CTR and
  37 // branching through it in the same dispatch group, and storing to an address,
  38 // then loading from the same address within a dispatch group.  To avoid these
  39 // conditions, we insert no-op instructions when appropriate.
  40 //
  41 // FIXME: This is missing some significant cases:
  42 //   1. Modeling of microcoded instructions.
  43 //   2. Handling of serialized operations.
  44 //   3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
  45 //
  46
  47 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
  48   : TII(tii) {
  49   EndDispatchGroup();
  50 }
  51
  52 void PPCHazardRecognizer970::EndDispatchGroup() {
  53   DOUT << "=== Start of dispatch group\n";
  54   NumIssued = 0;
  55
  56   // Structural hazard info.
  57   HasCTRSet = false;
  58   NumStores = 0;
  59 }
  60
  61
  62 PPCII::PPC970_Unit
  63 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
  64                                      bool &isFirst, bool &isSingle,
  65                                      bool &isCracked,
  66                                      bool &isLoad, bool &isStore) {
  67   if (Opcode < ISD::BUILTIN_OP_END) {
  68     isFirst = isSingle = isCracked = isLoad = isStore = false;
  69     return PPCII::PPC970_Pseudo;
  70   }
  71   Opcode -= ISD::BUILTIN_OP_END;
  72
  73   const TargetInstrDescriptor &TID = TII.get(Opcode);
  74
  75   isLoad  = TID.Flags & M_LOAD_FLAG;
  76   isStore = TID.Flags & M_STORE_FLAG;
  77
  78   unsigned TSFlags = TID.TSFlags;
  79
  80   isFirst   = TSFlags & PPCII::PPC970_First;
  81   isSingle  = TSFlags & PPCII::PPC970_Single;
  82   isCracked = TSFlags & PPCII::PPC970_Cracked;
  83   return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
  84 }
  85
  86 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer
  87 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
  88 bool PPCHazardRecognizer970::
  89 isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2) const {
  90   for (unsigned i = 0, e = NumStores; i != e; ++i) {
  91     // Handle exact and commuted addresses.
  92     if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i])
  93       return true;
  94     if (Ptr2 == StorePtr1[i] && Ptr1 == StorePtr2[i])
  95       return true;
  96
  97     // Okay, we don't have an exact match, if this is an indexed offset, see if
  98     // we have overlap (which happens during fp->int conversion for example).
  99     if (StorePtr2[i] == Ptr2) {
 100       if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1[i]))
 101         if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
 102           // Okay the base pointers match, so we have [c1+r] vs [c2+r].  Check
 103           // to see if the load and store actually overlap.
 104           int StoreOffs = StoreOffset->getValue();
 105           int LoadOffs  = LoadOffset->getValue();
 106           if (StoreOffs < LoadOffs) {
 107             if (int(StoreOffs+StoreSize[i]) > LoadOffs) return true;
 108           } else {
 109             if (int(LoadOffs+LoadSize) > StoreOffs) return true;
 110           }
 111         }
 112     }
 113   }
 114   return false;
 115 }
 116
 117 /// getHazardType - We return hazard for any non-branch instruction that would
 118 /// terminate terminate the dispatch group.  We turn NoopHazard for any
 119 /// instructions that wouldn't terminate the dispatch group that would cause a
 120 /// pipeline flush.
 121 HazardRecognizer::HazardType PPCHazardRecognizer970::
 122 getHazardType(SDNode *Node) {
 123   bool isFirst, isSingle, isCracked, isLoad, isStore;
 124   PPCII::PPC970_Unit InstrType =
 125     GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
 126                  isLoad, isStore);
 127   if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
 128   unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
 129
 130   // We can only issue a PPC970_First/PPC970_Single instruction (such as
 131   // crand/mtspr/etc) if this is the first cycle of the dispatch group.
 132   if (NumIssued != 0 && (isFirst || isSingle))
 133     return Hazard;
 134
 135   // If this instruction is cracked into two ops by the decoder, we know that
 136   // it is not a branch and that it cannot issue if 3 other instructions are
 137   // already in the dispatch group.
 138   if (isCracked && NumIssued > 2)
 139     return Hazard;
 140
 141   switch (InstrType) {
 142   default: assert(0 && "Unknown instruction type!");
 143   case PPCII::PPC970_FXU:
 144   case PPCII::PPC970_LSU:
 145   case PPCII::PPC970_FPU:
 146   case PPCII::PPC970_VALU:
 147   case PPCII::PPC970_VPERM:
 148     // We can only issue a branch as the last instruction in a group.
 149     if (NumIssued == 4) return Hazard;
 150     break;
 151   case PPCII::PPC970_CRU:
 152     // We can only issue a CR instruction in the first two slots.
 153     if (NumIssued >= 2) return Hazard;
 154     break;
 155   case PPCII::PPC970_BRU:
 156     break;
 157   }
 158
 159   // Do not allow MTCTR and BCTRL to be in the same dispatch group.
 160   if (HasCTRSet && (Opcode == PPC::BCTRL_Macho || Opcode == PPC::BCTRL_ELF))
 161     return NoopHazard;
 162
 163   // If this is a load following a store, make sure it's not to the same or
 164   // overlapping address.
 165   if (isLoad && NumStores) {
 166     unsigned LoadSize;
 167     switch (Opcode) {
 168     default: assert(0 && "Unknown load!");
 169     case PPC::LBZ:   case PPC::LBZU:
 170     case PPC::LBZX:
 171     case PPC::LBZ8:  case PPC::LBZU8:
 172     case PPC::LBZX8:
 173     case PPC::LVEBX:
 174       LoadSize = 1;
 175       break;
 176     case PPC::LHA:   case PPC::LHAU:
 177     case PPC::LHAX:
 178     case PPC::LHZ:   case PPC::LHZU:
 179     case PPC::LHZX:
 180     case PPC::LVEHX:
 181     case PPC::LHBRX:
 182     case PPC::LHA8:   case PPC::LHAU8:
 183     case PPC::LHAX8:
 184     case PPC::LHZ8:   case PPC::LHZU8:
 185     case PPC::LHZX8:
 186       LoadSize = 2;
 187       break;
 188     case PPC::LFS:    case PPC::LFSU:
 189     case PPC::LFSX:
 190     case PPC::LWZ:    case PPC::LWZU:
 191     case PPC::LWZX:
 192     case PPC::LWA:
 193     case PPC::LWAX:
 194     case PPC::LVEWX:
 195     case PPC::LWBRX:
 196     case PPC::LWZ8:
 197     case PPC::LWZX8:
 198       LoadSize = 4;
 199       break;
 200     case PPC::LFD:    case PPC::LFDU:
 201     case PPC::LFDX:
 202     case PPC::LD:     case PPC::LDU:
 203     case PPC::LDX:
 204       LoadSize = 8;
 205       break;
 206     case PPC::LVX:
 207     case PPC::LVXL:
 208       LoadSize = 16;
 209       break;
 210     }
 211
 212     if (isLoadOfStoredAddress(LoadSize,
 213                               Node->getOperand(0), Node->getOperand(1)))
 214       return NoopHazard;
 215   }
 216
 217   return NoHazard;
 218 }
 219
 220 void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
 221   bool isFirst, isSingle, isCracked, isLoad, isStore;
 222   PPCII::PPC970_Unit InstrType =
 223     GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
 224                  isLoad, isStore);
 225   if (InstrType == PPCII::PPC970_Pseudo) return;
 226   unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
 227
 228   // Update structural hazard information.
 229   if (Opcode == PPC::MTCTR) HasCTRSet = true;
 230
 231   // Track the address stored to.
 232   if (isStore) {
 233     unsigned ThisStoreSize;
 234     switch (Opcode) {
 235     default: assert(0 && "Unknown store instruction!");
 236     case PPC::STB:    case PPC::STB8:
 237     case PPC::STBU:   case PPC::STBU8:
 238     case PPC::STBX:   case PPC::STBX8:
 239     case PPC::STVEBX:
 240       ThisStoreSize = 1;
 241       break;
 242     case PPC::STH:    case PPC::STH8:
 243     case PPC::STHU:   case PPC::STHU8:
 244     case PPC::STHX:   case PPC::STHX8:
 245     case PPC::STVEHX:
 246     case PPC::STHBRX:
 247       ThisStoreSize = 2;
 248       break;
 249     case PPC::STFS:
 250     case PPC::STFSU:
 251     case PPC::STFSX:
 252     case PPC::STWX:   case PPC::STWX8:
 253     case PPC::STWUX:
 254     case PPC::STW:    case PPC::STW8:
 255     case PPC::STWU:   case PPC::STWU8:
 256     case PPC::STVEWX:
 257     case PPC::STFIWX:
 258     case PPC::STWBRX:
 259       ThisStoreSize = 4;
 260       break;
 261     case PPC::STD_32:
 262     case PPC::STDX_32:
 263     case PPC::STD:
 264     case PPC::STDU:
 265     case PPC::STFD:
 266     case PPC::STFDX:
 267     case PPC::STDX:
 268     case PPC::STDUX:
 269       ThisStoreSize = 8;
 270       break;
 271     case PPC::STVX:
 272     case PPC::STVXL:
 273       ThisStoreSize = 16;
 274       break;
 275     }
 276
 277     StoreSize[NumStores] = ThisStoreSize;
 278     StorePtr1[NumStores] = Node->getOperand(1);
 279     StorePtr2[NumStores] = Node->getOperand(2);
 280     ++NumStores;
 281   }
 282
 283   if (InstrType == PPCII::PPC970_BRU || isSingle)
 284     NumIssued = 4;  // Terminate a d-group.
 285   ++NumIssued;
 286
 287   // If this instruction is cracked into two ops by the decoder, remember that
 288   // we issued two pieces.
 289   if (isCracked)
 290     ++NumIssued;
 291
 292   if (NumIssued == 5)
 293     EndDispatchGroup();
 294 }
 295
 296 void PPCHazardRecognizer970::AdvanceCycle() {
 297   assert(NumIssued < 5 && "Illegal dispatch group!");
 298   ++NumIssued;
 299   if (NumIssued == 5)
 300     EndDispatchGroup();
 301 }
 302
 303 void PPCHazardRecognizer970::EmitNoop() {
 304   AdvanceCycle();
 305 }