lib/Target/X86/X86Subtarget.cpp

   1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by Nate Begeman and is distributed under the
   6 // University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the X86 specific subclass of TargetSubtarget.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "X86Subtarget.h"
  15 #include "X86GenSubtarget.inc"
  16 #include "llvm/Module.h"
  17 #include "llvm/Support/CommandLine.h"
  18 #include "llvm/Target/TargetMachine.h"
  19 using namespace llvm;
  20
  21 cl::opt<X86Subtarget::AsmWriterFlavorTy>
  22 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
  23   cl::desc("Choose style of code to emit from X86 backend:"),
  24   cl::values(
  25     clEnumValN(X86Subtarget::ATT,   "att",   "  Emit AT&T-style assembly"),
  26     clEnumValN(X86Subtarget::Intel, "intel", "  Emit Intel-style assembly"),
  27     clEnumValEnd));
  28
  29
  30 /// True if accessing the GV requires an extra load. For Windows, dllimported
  31 /// symbols are indirect, loading the value at address GV rather then the
  32 /// value of GV itself. This means that the GlobalAddress must be in the base
  33 /// or index register of the address, not the GV offset field.
  34 bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
  35                                        const TargetMachine& TM,
  36                                        bool isDirectCall) const
  37 {
  38   // FIXME: PIC
  39   if (TM.getRelocationModel() != Reloc::Static)
  40     if (isTargetDarwin()) {
  41       return (!isDirectCall &&
  42               (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
  43                (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode())));
  44     } else if (TM.getRelocationModel() == Reloc::PIC_ && isPICStyleGOT()) {
  45       // Extra load is needed for all non-statics.
  46       return (!isDirectCall &&
  47               (GV->isDeclaration() || !GV->hasInternalLinkage()));
  48     } else if (isTargetCygMing() || isTargetWindows()) {
  49       return (GV->hasDLLImportLinkage());
  50     }
  51
  52   return false;
  53 }
  54
  55 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
  56 /// specified arguments.  If we can't run cpuid on the host, return true.
  57 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
  58                           unsigned *rECX, unsigned *rEDX) {
  59 #if defined(__x86_64__)
  60   // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
  61   asm ("movq\t%%rbx, %%rsi\n\t"
  62        "cpuid\n\t"
  63        "xchgq\t%%rbx, %%rsi\n\t"
  64        : "=a" (*rEAX),
  65          "=S" (*rEBX),
  66          "=c" (*rECX),
  67          "=d" (*rEDX)
  68        :  "a" (value));
  69   return false;
  70 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
  71 #if defined(__GNUC__)
  72   asm ("movl\t%%ebx, %%esi\n\t"
  73        "cpuid\n\t"
  74        "xchgl\t%%ebx, %%esi\n\t"
  75        : "=a" (*rEAX),
  76          "=S" (*rEBX),
  77          "=c" (*rECX),
  78          "=d" (*rEDX)
  79        :  "a" (value));
  80   return false;
  81 #elif defined(_MSC_VER)
  82   __asm {
  83     mov   eax,value
  84     cpuid
  85     mov   esi,rEAX
  86     mov   dword ptr [esi],eax
  87     mov   esi,rEBX
  88     mov   dword ptr [esi],ebx
  89     mov   esi,rECX
  90     mov   dword ptr [esi],ecx
  91     mov   esi,rEDX
  92     mov   dword ptr [esi],edx
  93   }
  94   return false;
  95 #endif
  96 #endif
  97   return true;
  98 }
  99
 100 void X86Subtarget::AutoDetectSubtargetFeatures() {
 101   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
 102   union {
 103     unsigned u[3];
 104     char     c[12];
 105   } text;
 106
 107   if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
 108     return;
 109
 110   X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
 111
 112   if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
 113   if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
 114   if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
 115   if (ECX & 0x1)         X86SSELevel = SSE3;
 116   if ((ECX >> 9)  & 0x1) X86SSELevel = SSSE3;
 117
 118   if (memcmp(text.c, "GenuineIntel", 12) == 0 ||
 119       memcmp(text.c, "AuthenticAMD", 12) == 0) {
 120     X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
 121     HasX86_64 = (EDX >> 29) & 0x1;
 122   }
 123 }
 124
 125 static const char *GetCurrentX86CPU() {
 126   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
 127   if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
 128     return "generic";
 129   unsigned Family  = (EAX >> 8) & 0xf; // Bits 8 - 11
 130   unsigned Model   = (EAX >> 4) & 0xf; // Bits 4 - 7
 131   X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
 132   bool Em64T = (EDX >> 29) & 0x1;
 133
 134   union {
 135     unsigned u[3];
 136     char     c[12];
 137   } text;
 138
 139   X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
 140   if (memcmp(text.c, "GenuineIntel", 12) == 0) {
 141     switch (Family) {
 142       case 3:
 143         return "i386";
 144       case 4:
 145         return "i486";
 146       case 5:
 147         switch (Model) {
 148         case 4:  return "pentium-mmx";
 149         default: return "pentium";
 150         }
 151       case 6:
 152         switch (Model) {
 153         case 1:  return "pentiumpro";
 154         case 3:
 155         case 5:
 156         case 6:  return "pentium2";
 157         case 7:
 158         case 8:
 159         case 10:
 160         case 11: return "pentium3";
 161         case 9:
 162         case 13: return "pentium-m";
 163         case 14: return "yonah";
 164         case 15: return "core2";
 165         default: return "i686";
 166         }
 167       case 15: {
 168         switch (Model) {
 169         case 3:
 170         case 4:
 171           return (Em64T) ? "nocona" : "prescott";
 172         default:
 173           return (Em64T) ? "x86-64" : "pentium4";
 174         }
 175       }
 176
 177     default:
 178       return "generic";
 179     }
 180   } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
 181     // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
 182     // appears to be no way to generate the wide variety of AMD-specific targets
 183     // from the information returned from CPUID.
 184     switch (Family) {
 185       case 4:
 186         return "i486";
 187       case 5:
 188         switch (Model) {
 189         case 6:
 190         case 7:  return "k6";
 191         case 8:  return "k6-2";
 192         case 9:
 193         case 13: return "k6-3";
 194         default: return "pentium";
 195         }
 196       case 6:
 197         switch (Model) {
 198         case 4:  return "athlon-tbird";
 199         case 6:
 200         case 7:
 201         case 8:  return "athlon-mp";
 202         case 10: return "athlon-xp";
 203         default: return "athlon";
 204         }
 205       case 15:
 206         switch (Model) {
 207         case 1:  return "opteron";
 208         case 5:  return "athlon-fx"; // also opteron
 209         default: return "athlon64";
 210         }
 211     default:
 212       return "generic";
 213     }
 214   } else {
 215     return "generic";
 216   }
 217 }
 218
 219 X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
 220   : AsmFlavor(AsmWriterFlavor)
 221   , PICStyle(PICStyle::None)
 222   , X86SSELevel(NoMMXSSE)
 223   , HasX86_64(false)
 224   , stackAlignment(8)
 225   // FIXME: this is a known good value for Yonah. How about others?
 226   , MinRepStrSizeThreshold(128)
 227   , Is64Bit(is64Bit)
 228   , HasLow4GUserAddress(true)
 229   , TargetType(isELF) { // Default to ELF unless otherwise specified.
 230
 231   // Determine default and user specified characteristics
 232   if (!FS.empty()) {
 233     // If feature string is not empty, parse features string.
 234     std::string CPU = GetCurrentX86CPU();
 235     ParseSubtargetFeatures(FS, CPU);
 236
 237     if (Is64Bit && !HasX86_64)
 238       cerr << "Warning: Generation of 64-bit code for a 32-bit processor "
 239            << "requested.\n";
 240     if (Is64Bit && X86SSELevel < SSE2)
 241       cerr << "Warning: 64-bit processors all have at least SSE2.\n";
 242   } else {
 243     // Otherwise, use CPUID to auto-detect feature set.
 244     AutoDetectSubtargetFeatures();
 245   }
 246
 247   // If requesting codegen for X86-64, make sure that 64-bit and SSE2 features
 248   // are enabled.  These are available on all x86-64 CPUs.
 249   if (Is64Bit) {
 250     HasX86_64 = true;
 251     if (X86SSELevel < SSE2)
 252       X86SSELevel = SSE2;
 253   }
 254
 255   // Set the boolean corresponding to the current target triple, or the default
 256   // if one cannot be determined, to true.
 257   const std::string& TT = M.getTargetTriple();
 258   if (TT.length() > 5) {
 259     if (TT.find("cygwin") != std::string::npos)
 260       TargetType = isCygwin;
 261     else if (TT.find("mingw") != std::string::npos)
 262       TargetType = isMingw;
 263     else if (TT.find("darwin") != std::string::npos)
 264       TargetType = isDarwin;
 265     else if (TT.find("win32") != std::string::npos)
 266       TargetType = isWindows;
 267   } else if (TT.empty()) {
 268 #if defined(__CYGWIN__)
 269     TargetType = isCygwin;
 270 #elif defined(__MINGW32__)
 271     TargetType = isMingw;
 272 #elif defined(__APPLE__)
 273     TargetType = isDarwin;
 274 #elif defined(_WIN32)
 275     TargetType = isWindows;
 276 #endif
 277   }
 278
 279   // If the asm syntax hasn't been overridden on the command line, use whatever
 280   // the target wants.
 281   if (AsmFlavor == X86Subtarget::Unset) {
 282     if (TargetType == isWindows) {
 283       AsmFlavor = X86Subtarget::Intel;
 284     } else {
 285       AsmFlavor = X86Subtarget::ATT;
 286     }
 287   }
 288
 289   if (TargetType == isDarwin && Is64Bit)
 290     HasLow4GUserAddress = false;
 291
 292   if (TargetType == isDarwin ||
 293       TargetType == isCygwin ||
 294       TargetType == isMingw  ||
 295       (TargetType == isELF && Is64Bit))
 296     stackAlignment = 16;
 297 }