lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

   1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file provides Mips specific target streamer methods.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "MipsTargetStreamer.h"
  14 #include "MipsInstPrinter.h"
  15 #include "MCTargetDesc/MipsABIInfo.h"
  16 #include "MipsELFStreamer.h"
  17 #include "MipsMCExpr.h"
  18 #include "MipsMCTargetDesc.h"
  19 #include "MipsTargetObjectFile.h"
  20 #include "llvm/BinaryFormat/ELF.h"
  21 #include "llvm/MC/MCContext.h"
  22 #include "llvm/MC/MCSectionELF.h"
  23 #include "llvm/MC/MCSubtargetInfo.h"
  24 #include "llvm/MC/MCSymbolELF.h"
  25 #include "llvm/Support/CommandLine.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/FormattedStream.h"
  28
  29 using namespace llvm;
  30
  31 namespace {
  32 static cl::opt<bool> RoundSectionSizes(
  33     "mips-round-section-sizes", cl::init(false),
  34     cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
  35 } // end anonymous namespace
  36
  37 static bool isMipsR6(const MCSubtargetInfo *STI) {
  38   return STI->getFeatureBits()[Mips::FeatureMips32r6] ||
  39          STI->getFeatureBits()[Mips::FeatureMips64r6];
  40 }
  41
  42 static bool isMicroMips(const MCSubtargetInfo *STI) {
  43   return STI->getFeatureBits()[Mips::FeatureMicroMips];
  44 }
  45
  46 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
  47     : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
  48   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
  49 }
  50 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
  51 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
  52 void MipsTargetStreamer::setUsesMicroMips() {}
  53 void MipsTargetStreamer::emitDirectiveSetMips16() {}
  54 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
  55 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
  56 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
  57 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
  58 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
  59 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
  60 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
  61 void MipsTargetStreamer::emitDirectiveSetMt() {}
  62 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
  63 void MipsTargetStreamer::emitDirectiveSetCRC() {}
  64 void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
  65 void MipsTargetStreamer::emitDirectiveSetVirt() {}
  66 void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
  67 void MipsTargetStreamer::emitDirectiveSetGINV() {}
  68 void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
  69 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
  70 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
  71   forbidModuleDirective();
  72 }
  73 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
  74 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
  75 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
  76 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
  77 void MipsTargetStreamer::emitDirectiveNaN2008() {}
  78 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
  79 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
  80 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
  81 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
  82 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
  83                                    unsigned ReturnReg) {}
  84 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
  85 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
  86 }
  87 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
  88   forbidModuleDirective();
  89 }
  90 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
  91 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
  92 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
  93 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
  94 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
  95 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
  96 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
  97 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
  98 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
  99 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
 100 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
 101 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
 102 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
 103 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
 104 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
 105 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
 106 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
 107 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
 108 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
 109   forbidModuleDirective();
 110 }
 111 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
 112   forbidModuleDirective();
 113 }
 114 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
 115 void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
 116 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
 117 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
 118 void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) {
 119   // .cplocal $reg
 120   // This directive forces to use the alternate register for context pointer.
 121   // For example
 122   //   .cplocal $4
 123   //   jal foo
 124   // expands to
 125   //   ld    $25, %call16(foo)($4)
 126   //   jalr  $25
 127
 128   if (!getABI().IsN32() && !getABI().IsN64())
 129     return;
 130
 131   GPReg = RegNo;
 132
 133   forbidModuleDirective();
 134 }
 135 bool MipsTargetStreamer::emitDirectiveCpRestore(
 136     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
 137     const MCSubtargetInfo *STI) {
 138   forbidModuleDirective();
 139   return true;
 140 }
 141 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
 142                                               const MCSymbol &Sym, bool IsReg) {
 143 }
 144 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
 145                                                bool SaveLocationIsRegister) {}
 146
 147 void MipsTargetStreamer::emitDirectiveModuleFP() {}
 148
 149 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
 150   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
 151     report_fatal_error("+nooddspreg is only valid for O32");
 152 }
 153 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
 154 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
 155 void MipsTargetStreamer::emitDirectiveModuleMT() {}
 156 void MipsTargetStreamer::emitDirectiveModuleCRC() {}
 157 void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
 158 void MipsTargetStreamer::emitDirectiveModuleVirt() {}
 159 void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
 160 void MipsTargetStreamer::emitDirectiveModuleGINV() {}
 161 void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
 162 void MipsTargetStreamer::emitDirectiveSetFp(
 163     MipsABIFlagsSection::FpABIKind Value) {
 164   forbidModuleDirective();
 165 }
 166 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
 167 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
 168   forbidModuleDirective();
 169 }
 170
 171 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
 172                                const MCSubtargetInfo *STI) {
 173   MCInst TmpInst;
 174   TmpInst.setOpcode(Opcode);
 175   TmpInst.addOperand(MCOperand::createReg(Reg0));
 176   TmpInst.setLoc(IDLoc);
 177   getStreamer().EmitInstruction(TmpInst, *STI);
 178 }
 179
 180 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
 181                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
 182   MCInst TmpInst;
 183   TmpInst.setOpcode(Opcode);
 184   TmpInst.addOperand(MCOperand::createReg(Reg0));
 185   TmpInst.addOperand(Op1);
 186   TmpInst.setLoc(IDLoc);
 187   getStreamer().EmitInstruction(TmpInst, *STI);
 188 }
 189
 190 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
 191                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
 192   emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
 193 }
 194
 195 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
 196                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
 197   emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
 198 }
 199
 200 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
 201                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
 202   MCInst TmpInst;
 203   TmpInst.setOpcode(Opcode);
 204   TmpInst.addOperand(MCOperand::createImm(Imm1));
 205   TmpInst.addOperand(MCOperand::createImm(Imm2));
 206   TmpInst.setLoc(IDLoc);
 207   getStreamer().EmitInstruction(TmpInst, *STI);
 208 }
 209
 210 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
 211                                  MCOperand Op2, SMLoc IDLoc,
 212                                  const MCSubtargetInfo *STI) {
 213   MCInst TmpInst;
 214   TmpInst.setOpcode(Opcode);
 215   TmpInst.addOperand(MCOperand::createReg(Reg0));
 216   TmpInst.addOperand(MCOperand::createReg(Reg1));
 217   TmpInst.addOperand(Op2);
 218   TmpInst.setLoc(IDLoc);
 219   getStreamer().EmitInstruction(TmpInst, *STI);
 220 }
 221
 222 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
 223                                  unsigned Reg2, SMLoc IDLoc,
 224                                  const MCSubtargetInfo *STI) {
 225   emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
 226 }
 227
 228 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
 229                                   unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
 230                                   const MCSubtargetInfo *STI) {
 231   MCInst TmpInst;
 232   TmpInst.setOpcode(Opcode);
 233   TmpInst.addOperand(MCOperand::createReg(Reg0));
 234   TmpInst.addOperand(MCOperand::createReg(Reg1));
 235   TmpInst.addOperand(MCOperand::createReg(Reg2));
 236   TmpInst.addOperand(Op3);
 237   TmpInst.setLoc(IDLoc);
 238   getStreamer().EmitInstruction(TmpInst, *STI);
 239 }
 240
 241 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
 242                                  int16_t Imm, SMLoc IDLoc,
 243                                  const MCSubtargetInfo *STI) {
 244   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
 245 }
 246
 247 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
 248                                    unsigned Reg1, int16_t Imm0, int16_t Imm1,
 249                                    int16_t Imm2, SMLoc IDLoc,
 250                                    const MCSubtargetInfo *STI) {
 251   MCInst TmpInst;
 252   TmpInst.setOpcode(Opcode);
 253   TmpInst.addOperand(MCOperand::createReg(Reg0));
 254   TmpInst.addOperand(MCOperand::createReg(Reg1));
 255   TmpInst.addOperand(MCOperand::createImm(Imm0));
 256   TmpInst.addOperand(MCOperand::createImm(Imm1));
 257   TmpInst.addOperand(MCOperand::createImm(Imm2));
 258   TmpInst.setLoc(IDLoc);
 259   getStreamer().EmitInstruction(TmpInst, *STI);
 260 }
 261
 262 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
 263                                   unsigned TrgReg, bool Is64Bit,
 264                                   const MCSubtargetInfo *STI) {
 265   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
 266           STI);
 267 }
 268
 269 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
 270                                   int16_t ShiftAmount, SMLoc IDLoc,
 271                                   const MCSubtargetInfo *STI) {
 272   if (ShiftAmount >= 32) {
 273     emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
 274     return;
 275   }
 276
 277   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
 278 }
 279
 280 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
 281                                             const MCSubtargetInfo *STI) {
 282   if (hasShortDelaySlot)
 283     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
 284   else
 285     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
 286 }
 287
 288 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
 289   if (isMicroMips(STI))
 290     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
 291   else
 292     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
 293 }
 294
 295 /// Emit the $gp restore operation for .cprestore.
 296 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
 297                                        const MCSubtargetInfo *STI) {
 298   emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
 299 }
 300
 301 /// Emit a store instruction with an immediate offset.
 302 void MipsTargetStreamer::emitStoreWithImmOffset(
 303     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
 304     function_ref<unsigned()> GetATReg, SMLoc IDLoc,
 305     const MCSubtargetInfo *STI) {
 306   if (isInt<16>(Offset)) {
 307     emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
 308     return;
 309   }
 310
 311   // sw $8, offset($8) => lui $at, %hi(offset)
 312   //                      add $at, $at, $8
 313   //                      sw $8, %lo(offset)($at)
 314
 315   unsigned ATReg = GetATReg();
 316   if (!ATReg)
 317     return;
 318
 319   unsigned LoOffset = Offset & 0x0000ffff;
 320   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
 321
 322   // If msb of LoOffset is 1(negative number) we must increment HiOffset
 323   // to account for the sign-extension of the low part.
 324   if (LoOffset & 0x8000)
 325     HiOffset++;
 326
 327   // Generate the base address in ATReg.
 328   emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
 329   if (BaseReg != Mips::ZERO)
 330     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
 331   // Emit the store with the adjusted base and offset.
 332   emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
 333 }
 334
 335 /// Emit a store instruction with an symbol offset.
 336 void MipsTargetStreamer::emitSCWithSymOffset(unsigned Opcode, unsigned SrcReg,
 337                                              unsigned BaseReg,
 338                                              MCOperand &HiOperand,
 339                                              MCOperand &LoOperand,
 340                                              unsigned ATReg, SMLoc IDLoc,
 341                                              const MCSubtargetInfo *STI) {
 342   // sc $8, sym => lui $at, %hi(sym)
 343   //               sc $8, %lo(sym)($at)
 344
 345   // Generate the base address in ATReg.
 346   emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
 347   if (!isMicroMips(STI) && isMipsR6(STI)) {
 348     // For non-micromips r6 offset for 'sc' is not in the lower 16 bits so we
 349     // put it in 'at'.
 350     // sc $8, sym => lui $at, %hi(sym)
 351     //               addiu $at, $at, %lo(sym)
 352     //               sc $8, 0($at)
 353     emitRRX(Mips::ADDiu, ATReg, ATReg, LoOperand, IDLoc, STI);
 354     MCOperand Offset = MCOperand::createImm(0);
 355     // Emit the store with the adjusted base and offset.
 356     emitRRRX(Opcode, SrcReg, SrcReg, ATReg, Offset, IDLoc, STI);
 357   } else {
 358     if (BaseReg != Mips::ZERO)
 359       emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
 360     // Emit the store with the adjusted base and offset.
 361     emitRRRX(Opcode, SrcReg, SrcReg, ATReg, LoOperand, IDLoc, STI);
 362   }
 363 }
 364
 365 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
 366 /// permitted to be the same register iff DstReg is distinct from BaseReg and
 367 /// DstReg is a GPR. It is the callers responsibility to identify such cases
 368 /// and pass the appropriate register in TmpReg.
 369 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
 370                                                unsigned BaseReg, int64_t Offset,
 371                                                unsigned TmpReg, SMLoc IDLoc,
 372                                                const MCSubtargetInfo *STI) {
 373   if (isInt<16>(Offset)) {
 374     emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
 375     return;
 376   }
 377
 378   // 1) lw $8, offset($9) => lui $8, %hi(offset)
 379   //                         add $8, $8, $9
 380   //                         lw $8, %lo(offset)($9)
 381   // 2) lw $8, offset($8) => lui $at, %hi(offset)
 382   //                         add $at, $at, $8
 383   //                         lw $8, %lo(offset)($at)
 384
 385   unsigned LoOffset = Offset & 0x0000ffff;
 386   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
 387
 388   // If msb of LoOffset is 1(negative number) we must increment HiOffset
 389   // to account for the sign-extension of the low part.
 390   if (LoOffset & 0x8000)
 391     HiOffset++;
 392
 393   // Generate the base address in TmpReg.
 394   emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
 395   if (BaseReg != Mips::ZERO)
 396     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
 397   // Emit the load with the adjusted base and offset.
 398   emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
 399 }
 400
 401 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
 402                                              formatted_raw_ostream &OS)
 403     : MipsTargetStreamer(S), OS(OS) {}
 404
 405 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
 406   OS << "\t.set\tmicromips\n";
 407   forbidModuleDirective();
 408 }
 409
 410 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
 411   OS << "\t.set\tnomicromips\n";
 412   forbidModuleDirective();
 413 }
 414
 415 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
 416   OS << "\t.set\tmips16\n";
 417   forbidModuleDirective();
 418 }
 419
 420 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
 421   OS << "\t.set\tnomips16\n";
 422   MipsTargetStreamer::emitDirectiveSetNoMips16();
 423 }
 424
 425 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
 426   OS << "\t.set\treorder\n";
 427   MipsTargetStreamer::emitDirectiveSetReorder();
 428 }
 429
 430 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
 431   OS << "\t.set\tnoreorder\n";
 432   forbidModuleDirective();
 433 }
 434
 435 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
 436   OS << "\t.set\tmacro\n";
 437   MipsTargetStreamer::emitDirectiveSetMacro();
 438 }
 439
 440 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
 441   OS << "\t.set\tnomacro\n";
 442   MipsTargetStreamer::emitDirectiveSetNoMacro();
 443 }
 444
 445 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
 446   OS << "\t.set\tmsa\n";
 447   MipsTargetStreamer::emitDirectiveSetMsa();
 448 }
 449
 450 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
 451   OS << "\t.set\tnomsa\n";
 452   MipsTargetStreamer::emitDirectiveSetNoMsa();
 453 }
 454
 455 void MipsTargetAsmStreamer::emitDirectiveSetMt() {
 456   OS << "\t.set\tmt\n";
 457   MipsTargetStreamer::emitDirectiveSetMt();
 458 }
 459
 460 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
 461   OS << "\t.set\tnomt\n";
 462   MipsTargetStreamer::emitDirectiveSetNoMt();
 463 }
 464
 465 void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
 466   OS << "\t.set\tcrc\n";
 467   MipsTargetStreamer::emitDirectiveSetCRC();
 468 }
 469
 470 void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
 471   OS << "\t.set\tnocrc\n";
 472   MipsTargetStreamer::emitDirectiveSetNoCRC();
 473 }
 474
 475 void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
 476   OS << "\t.set\tvirt\n";
 477   MipsTargetStreamer::emitDirectiveSetVirt();
 478 }
 479
 480 void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
 481   OS << "\t.set\tnovirt\n";
 482   MipsTargetStreamer::emitDirectiveSetNoVirt();
 483 }
 484
 485 void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
 486   OS << "\t.set\tginv\n";
 487   MipsTargetStreamer::emitDirectiveSetGINV();
 488 }
 489
 490 void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
 491   OS << "\t.set\tnoginv\n";
 492   MipsTargetStreamer::emitDirectiveSetNoGINV();
 493 }
 494
 495 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
 496   OS << "\t.set\tat\n";
 497   MipsTargetStreamer::emitDirectiveSetAt();
 498 }
 499
 500 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
 501   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
 502   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
 503 }
 504
 505 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
 506   OS << "\t.set\tnoat\n";
 507   MipsTargetStreamer::emitDirectiveSetNoAt();
 508 }
 509
 510 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
 511   OS << "\t.end\t" << Name << '\n';
 512 }
 513
 514 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
 515   OS << "\t.ent\t" << Symbol.getName() << '\n';
 516 }
 517
 518 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
 519
 520 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
 521
 522 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
 523   OS << "\t.nan\tlegacy\n";
 524 }
 525
 526 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
 527   OS << "\t.option\tpic0\n";
 528 }
 529
 530 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
 531   OS << "\t.option\tpic2\n";
 532 }
 533
 534 void MipsTargetAsmStreamer::emitDirectiveInsn() {
 535   MipsTargetStreamer::emitDirectiveInsn();
 536   OS << "\t.insn\n";
 537 }
 538
 539 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
 540                                       unsigned ReturnReg) {
 541   OS << "\t.frame\t$"
 542      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
 543      << StackSize << ",$"
 544      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
 545 }
 546
 547 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
 548   OS << "\t.set arch=" << Arch << "\n";
 549   MipsTargetStreamer::emitDirectiveSetArch(Arch);
 550 }
 551
 552 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
 553   OS << "\t.set\tmips0\n";
 554   MipsTargetStreamer::emitDirectiveSetMips0();
 555 }
 556
 557 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
 558   OS << "\t.set\tmips1\n";
 559   MipsTargetStreamer::emitDirectiveSetMips1();
 560 }
 561
 562 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
 563   OS << "\t.set\tmips2\n";
 564   MipsTargetStreamer::emitDirectiveSetMips2();
 565 }
 566
 567 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
 568   OS << "\t.set\tmips3\n";
 569   MipsTargetStreamer::emitDirectiveSetMips3();
 570 }
 571
 572 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
 573   OS << "\t.set\tmips4\n";
 574   MipsTargetStreamer::emitDirectiveSetMips4();
 575 }
 576
 577 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
 578   OS << "\t.set\tmips5\n";
 579   MipsTargetStreamer::emitDirectiveSetMips5();
 580 }
 581
 582 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
 583   OS << "\t.set\tmips32\n";
 584   MipsTargetStreamer::emitDirectiveSetMips32();
 585 }
 586
 587 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
 588   OS << "\t.set\tmips32r2\n";
 589   MipsTargetStreamer::emitDirectiveSetMips32R2();
 590 }
 591
 592 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
 593   OS << "\t.set\tmips32r3\n";
 594   MipsTargetStreamer::emitDirectiveSetMips32R3();
 595 }
 596
 597 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
 598   OS << "\t.set\tmips32r5\n";
 599   MipsTargetStreamer::emitDirectiveSetMips32R5();
 600 }
 601
 602 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
 603   OS << "\t.set\tmips32r6\n";
 604   MipsTargetStreamer::emitDirectiveSetMips32R6();
 605 }
 606
 607 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
 608   OS << "\t.set\tmips64\n";
 609   MipsTargetStreamer::emitDirectiveSetMips64();
 610 }
 611
 612 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
 613   OS << "\t.set\tmips64r2\n";
 614   MipsTargetStreamer::emitDirectiveSetMips64R2();
 615 }
 616
 617 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
 618   OS << "\t.set\tmips64r3\n";
 619   MipsTargetStreamer::emitDirectiveSetMips64R3();
 620 }
 621
 622 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
 623   OS << "\t.set\tmips64r5\n";
 624   MipsTargetStreamer::emitDirectiveSetMips64R5();
 625 }
 626
 627 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
 628   OS << "\t.set\tmips64r6\n";
 629   MipsTargetStreamer::emitDirectiveSetMips64R6();
 630 }
 631
 632 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
 633   OS << "\t.set\tdsp\n";
 634   MipsTargetStreamer::emitDirectiveSetDsp();
 635 }
 636
 637 void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
 638   OS << "\t.set\tdspr2\n";
 639   MipsTargetStreamer::emitDirectiveSetDspr2();
 640 }
 641
 642 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
 643   OS << "\t.set\tnodsp\n";
 644   MipsTargetStreamer::emitDirectiveSetNoDsp();
 645 }
 646
 647 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
 648   OS << "\t.set\tpop\n";
 649   MipsTargetStreamer::emitDirectiveSetPop();
 650 }
 651
 652 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
 653  OS << "\t.set\tpush\n";
 654  MipsTargetStreamer::emitDirectiveSetPush();
 655 }
 656
 657 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
 658   OS << "\t.set\tsoftfloat\n";
 659   MipsTargetStreamer::emitDirectiveSetSoftFloat();
 660 }
 661
 662 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
 663   OS << "\t.set\thardfloat\n";
 664   MipsTargetStreamer::emitDirectiveSetHardFloat();
 665 }
 666
 667 // Print a 32 bit hex number with all numbers.
 668 static void printHex32(unsigned Value, raw_ostream &OS) {
 669   OS << "0x";
 670   for (int i = 7; i >= 0; i--)
 671     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
 672 }
 673
 674 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
 675                                      int CPUTopSavedRegOff) {
 676   OS << "\t.mask \t";
 677   printHex32(CPUBitmask, OS);
 678   OS << ',' << CPUTopSavedRegOff << '\n';
 679 }
 680
 681 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
 682                                       int FPUTopSavedRegOff) {
 683   OS << "\t.fmask\t";
 684   printHex32(FPUBitmask, OS);
 685   OS << "," << FPUTopSavedRegOff << '\n';
 686 }
 687
 688 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
 689   OS << "\t.cpload\t$"
 690      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
 691   forbidModuleDirective();
 692 }
 693
 694 void MipsTargetAsmStreamer::emitDirectiveCpLocal(unsigned RegNo) {
 695   OS << "\t.cplocal\t$"
 696      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
 697   MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
 698 }
 699
 700 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
 701     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
 702     const MCSubtargetInfo *STI) {
 703   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
 704   OS << "\t.cprestore\t" << Offset << "\n";
 705   return true;
 706 }
 707
 708 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
 709                                                  int RegOrOffset,
 710                                                  const MCSymbol &Sym,
 711                                                  bool IsReg) {
 712   OS << "\t.cpsetup\t$"
 713      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
 714
 715   if (IsReg)
 716     OS << "$"
 717        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
 718   else
 719     OS << RegOrOffset;
 720
 721   OS << ", ";
 722
 723   OS << Sym.getName();
 724   forbidModuleDirective();
 725 }
 726
 727 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
 728                                                   bool SaveLocationIsRegister) {
 729   OS << "\t.cpreturn";
 730   forbidModuleDirective();
 731 }
 732
 733 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
 734   MipsABIFlagsSection::FpABIKind FpABI = ABIFlagsSection.getFpABI();
 735   if (FpABI == MipsABIFlagsSection::FpABIKind::SOFT)
 736     OS << "\t.module\tsoftfloat\n";
 737   else
 738     OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(FpABI) << "\n";
 739 }
 740
 741 void MipsTargetAsmStreamer::emitDirectiveSetFp(
 742     MipsABIFlagsSection::FpABIKind Value) {
 743   MipsTargetStreamer::emitDirectiveSetFp(Value);
 744
 745   OS << "\t.set\tfp=";
 746   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
 747 }
 748
 749 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
 750   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
 751
 752   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
 753 }
 754
 755 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
 756   MipsTargetStreamer::emitDirectiveSetOddSPReg();
 757   OS << "\t.set\toddspreg\n";
 758 }
 759
 760 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
 761   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
 762   OS << "\t.set\tnooddspreg\n";
 763 }
 764
 765 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
 766   OS << "\t.module\tsoftfloat\n";
 767 }
 768
 769 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
 770   OS << "\t.module\thardfloat\n";
 771 }
 772
 773 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
 774   OS << "\t.module\tmt\n";
 775 }
 776
 777 void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
 778   OS << "\t.module\tcrc\n";
 779 }
 780
 781 void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
 782   OS << "\t.module\tnocrc\n";
 783 }
 784
 785 void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
 786   OS << "\t.module\tvirt\n";
 787 }
 788
 789 void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
 790   OS << "\t.module\tnovirt\n";
 791 }
 792
 793 void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
 794   OS << "\t.module\tginv\n";
 795 }
 796
 797 void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
 798   OS << "\t.module\tnoginv\n";
 799 }
 800
 801 // This part is for ELF object output.
 802 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
 803                                              const MCSubtargetInfo &STI)
 804     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
 805   MCAssembler &MCA = getStreamer().getAssembler();
 806
 807   // It's possible that MCObjectFileInfo isn't fully initialized at this point
 808   // due to an initialization order problem where LLVMTargetMachine creates the
 809   // target streamer before TargetLoweringObjectFile calls
 810   // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
 811   // covers all cases so this statement covers most cases and direct object
 812   // emission must call setPic() once MCObjectFileInfo has been initialized. The
 813   // cases we don't handle here are covered by MipsAsmPrinter.
 814   Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
 815
 816   const FeatureBitset &Features = STI.getFeatureBits();
 817
 818   // Set the header flags that we can in the constructor.
 819   // FIXME: This is a fairly terrible hack. We set the rest
 820   // of these in the destructor. The problem here is two-fold:
 821   //
 822   // a: Some of the eflags can be set/reset by directives.
 823   // b: There aren't any usage paths that initialize the ABI
 824   //    pointer until after we initialize either an assembler
 825   //    or the target machine.
 826   // We can fix this by making the target streamer construct
 827   // the ABI, but this is fraught with wide ranging dependency
 828   // issues as well.
 829   unsigned EFlags = MCA.getELFHeaderEFlags();
 830
 831   // FIXME: Fix a dependency issue by instantiating the ABI object to some
 832   // default based off the triple. The triple doesn't describe the target
 833   // fully, but any external user of the API that uses the MCTargetStreamer
 834   // would otherwise crash on assertion failure.
 835
 836   ABI = MipsABIInfo(
 837       STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
 838               STI.getTargetTriple().getArch() == Triple::ArchType::mips
 839           ? MipsABIInfo::O32()
 840           : MipsABIInfo::N64());
 841
 842   // Architecture
 843   if (Features[Mips::FeatureMips64r6])
 844     EFlags |= ELF::EF_MIPS_ARCH_64R6;
 845   else if (Features[Mips::FeatureMips64r2] ||
 846            Features[Mips::FeatureMips64r3] ||
 847            Features[Mips::FeatureMips64r5])
 848     EFlags |= ELF::EF_MIPS_ARCH_64R2;
 849   else if (Features[Mips::FeatureMips64])
 850     EFlags |= ELF::EF_MIPS_ARCH_64;
 851   else if (Features[Mips::FeatureMips5])
 852     EFlags |= ELF::EF_MIPS_ARCH_5;
 853   else if (Features[Mips::FeatureMips4])
 854     EFlags |= ELF::EF_MIPS_ARCH_4;
 855   else if (Features[Mips::FeatureMips3])
 856     EFlags |= ELF::EF_MIPS_ARCH_3;
 857   else if (Features[Mips::FeatureMips32r6])
 858     EFlags |= ELF::EF_MIPS_ARCH_32R6;
 859   else if (Features[Mips::FeatureMips32r2] ||
 860            Features[Mips::FeatureMips32r3] ||
 861            Features[Mips::FeatureMips32r5])
 862     EFlags |= ELF::EF_MIPS_ARCH_32R2;
 863   else if (Features[Mips::FeatureMips32])
 864     EFlags |= ELF::EF_MIPS_ARCH_32;
 865   else if (Features[Mips::FeatureMips2])
 866     EFlags |= ELF::EF_MIPS_ARCH_2;
 867   else
 868     EFlags |= ELF::EF_MIPS_ARCH_1;
 869
 870   // Machine
 871   if (Features[Mips::FeatureCnMips])
 872     EFlags |= ELF::EF_MIPS_MACH_OCTEON;
 873
 874   // Other options.
 875   if (Features[Mips::FeatureNaN2008])
 876     EFlags |= ELF::EF_MIPS_NAN2008;
 877
 878   MCA.setELFHeaderEFlags(EFlags);
 879 }
 880
 881 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
 882   auto *Symbol = cast<MCSymbolELF>(S);
 883   getStreamer().getAssembler().registerSymbol(*Symbol);
 884   uint8_t Type = Symbol->getType();
 885   if (Type != ELF::STT_FUNC)
 886     return;
 887
 888   if (isMicroMipsEnabled())
 889     Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
 890 }
 891
 892 void MipsTargetELFStreamer::finish() {
 893   MCAssembler &MCA = getStreamer().getAssembler();
 894   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
 895
 896   // .bss, .text and .data are always at least 16-byte aligned.
 897   MCSection &TextSection = *OFI.getTextSection();
 898   MCA.registerSection(TextSection);
 899   MCSection &DataSection = *OFI.getDataSection();
 900   MCA.registerSection(DataSection);
 901   MCSection &BSSSection = *OFI.getBSSSection();
 902   MCA.registerSection(BSSSection);
 903
 904   TextSection.setAlignment(Align(std::max(16u, TextSection.getAlignment())));
 905   DataSection.setAlignment(Align(std::max(16u, DataSection.getAlignment())));
 906   BSSSection.setAlignment(Align(std::max(16u, BSSSection.getAlignment())));
 907
 908   if (RoundSectionSizes) {
 909     // Make sections sizes a multiple of the alignment. This is useful for
 910     // verifying the output of IAS against the output of other assemblers but
 911     // it's not necessary to produce a correct object and increases section
 912     // size.
 913     MCStreamer &OS = getStreamer();
 914     for (MCSection &S : MCA) {
 915       MCSectionELF &Section = static_cast<MCSectionELF &>(S);
 916
 917       unsigned Alignment = Section.getAlignment();
 918       if (Alignment) {
 919         OS.SwitchSection(&Section);
 920         if (Section.UseCodeAlign())
 921           OS.EmitCodeAlignment(Alignment, Alignment);
 922         else
 923           OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
 924       }
 925     }
 926   }
 927
 928   const FeatureBitset &Features = STI.getFeatureBits();
 929
 930   // Update e_header flags. See the FIXME and comment above in
 931   // the constructor for a full rundown on this.
 932   unsigned EFlags = MCA.getELFHeaderEFlags();
 933
 934   // ABI
 935   // N64 does not require any ABI bits.
 936   if (getABI().IsO32())
 937     EFlags |= ELF::EF_MIPS_ABI_O32;
 938   else if (getABI().IsN32())
 939     EFlags |= ELF::EF_MIPS_ABI2;
 940
 941   if (Features[Mips::FeatureGP64Bit]) {
 942     if (getABI().IsO32())
 943       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
 944   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
 945     EFlags |= ELF::EF_MIPS_32BITMODE;
 946
 947   // -mplt is not implemented but we should act as if it was
 948   // given.
 949   if (!Features[Mips::FeatureNoABICalls])
 950     EFlags |= ELF::EF_MIPS_CPIC;
 951
 952   if (Pic)
 953     EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
 954
 955   MCA.setELFHeaderEFlags(EFlags);
 956
 957   // Emit all the option records.
 958   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
 959   // .reginfo.
 960   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
 961   MEF.EmitMipsOptionRecords();
 962
 963   emitMipsAbiFlags();
 964 }
 965
 966 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
 967   auto *Symbol = cast<MCSymbolELF>(S);
 968   // If on rhs is micromips symbol then mark Symbol as microMips.
 969   if (Value->getKind() != MCExpr::SymbolRef)
 970     return;
 971   const auto &RhsSym = cast<MCSymbolELF>(
 972       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
 973
 974   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
 975     return;
 976
 977   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
 978 }
 979
 980 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
 981   return static_cast<MCELFStreamer &>(Streamer);
 982 }
 983
 984 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
 985   MicroMipsEnabled = true;
 986   forbidModuleDirective();
 987 }
 988
 989 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
 990   MicroMipsEnabled = false;
 991   forbidModuleDirective();
 992 }
 993
 994 void MipsTargetELFStreamer::setUsesMicroMips() {
 995   MCAssembler &MCA = getStreamer().getAssembler();
 996   unsigned Flags = MCA.getELFHeaderEFlags();
 997   Flags |= ELF::EF_MIPS_MICROMIPS;
 998   MCA.setELFHeaderEFlags(Flags);
 999 }
1000
1001 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
1002   MCAssembler &MCA = getStreamer().getAssembler();
1003   unsigned Flags = MCA.getELFHeaderEFlags();
1004   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
1005   MCA.setELFHeaderEFlags(Flags);
1006   forbidModuleDirective();
1007 }
1008
1009 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
1010   MCAssembler &MCA = getStreamer().getAssembler();
1011   unsigned Flags = MCA.getELFHeaderEFlags();
1012   Flags |= ELF::EF_MIPS_NOREORDER;
1013   MCA.setELFHeaderEFlags(Flags);
1014   forbidModuleDirective();
1015 }
1016
1017 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
1018   MCAssembler &MCA = getStreamer().getAssembler();
1019   MCContext &Context = MCA.getContext();
1020   MCStreamer &OS = getStreamer();
1021
1022   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
1023
1024   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
1025   const MCSymbolRefExpr *ExprRef =
1026       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
1027
1028   MCA.registerSection(*Sec);
1029   Sec->setAlignment(Align(4));
1030
1031   OS.PushSection();
1032
1033   OS.SwitchSection(Sec);
1034
1035   OS.EmitValueImpl(ExprRef, 4);
1036
1037   OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
1038   OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
1039
1040   OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
1041   OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
1042
1043   OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
1044   OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
1045   OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
1046
1047   // The .end directive marks the end of a procedure. Invalidate
1048   // the information gathered up until this point.
1049   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1050
1051   OS.PopSection();
1052
1053   // .end also implicitly sets the size.
1054   MCSymbol *CurPCSym = Context.createTempSymbol();
1055   OS.EmitLabel(CurPCSym);
1056   const MCExpr *Size = MCBinaryExpr::createSub(
1057       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
1058       ExprRef, Context);
1059
1060   // The ELFObjectWriter can determine the absolute size as it has access to
1061   // the layout information of the assembly file, so a size expression rather
1062   // than an absolute value is ok here.
1063   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1064 }
1065
1066 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
1067   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1068
1069   // .ent also acts like an implicit '.type symbol, STT_FUNC'
1070   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1071 }
1072
1073 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
1074   MCAssembler &MCA = getStreamer().getAssembler();
1075   unsigned Flags = MCA.getELFHeaderEFlags();
1076   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
1077   MCA.setELFHeaderEFlags(Flags);
1078 }
1079
1080 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
1081   MCAssembler &MCA = getStreamer().getAssembler();
1082   unsigned Flags = MCA.getELFHeaderEFlags();
1083   Flags |= ELF::EF_MIPS_NAN2008;
1084   MCA.setELFHeaderEFlags(Flags);
1085 }
1086
1087 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
1088   MCAssembler &MCA = getStreamer().getAssembler();
1089   unsigned Flags = MCA.getELFHeaderEFlags();
1090   Flags &= ~ELF::EF_MIPS_NAN2008;
1091   MCA.setELFHeaderEFlags(Flags);
1092 }
1093
1094 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
1095   MCAssembler &MCA = getStreamer().getAssembler();
1096   unsigned Flags = MCA.getELFHeaderEFlags();
1097   // This option overrides other PIC options like -KPIC.
1098   Pic = false;
1099   Flags &= ~ELF::EF_MIPS_PIC;
1100   MCA.setELFHeaderEFlags(Flags);
1101 }
1102
1103 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1104   MCAssembler &MCA = getStreamer().getAssembler();
1105   unsigned Flags = MCA.getELFHeaderEFlags();
1106   Pic = true;
1107   // NOTE: We are following the GAS behaviour here which means the directive
1108   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1109   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1110   // EF_MIPS_CPIC to be mutually exclusive.
1111   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1112   MCA.setELFHeaderEFlags(Flags);
1113 }
1114
1115 void MipsTargetELFStreamer::emitDirectiveInsn() {
1116   MipsTargetStreamer::emitDirectiveInsn();
1117   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1118   MEF.createPendingLabelRelocs();
1119 }
1120
1121 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1122                                       unsigned ReturnReg_) {
1123   MCContext &Context = getStreamer().getAssembler().getContext();
1124   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1125
1126   FrameInfoSet = true;
1127   FrameReg = RegInfo->getEncodingValue(StackReg);
1128   FrameOffset = StackSize;
1129   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1130 }
1131
1132 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1133                                      int CPUTopSavedRegOff) {
1134   GPRInfoSet = true;
1135   GPRBitMask = CPUBitmask;
1136   GPROffset = CPUTopSavedRegOff;
1137 }
1138
1139 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1140                                       int FPUTopSavedRegOff) {
1141   FPRInfoSet = true;
1142   FPRBitMask = FPUBitmask;
1143   FPROffset = FPUTopSavedRegOff;
1144 }
1145
1146 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1147   // .cpload $reg
1148   // This directive expands to:
1149   // lui   $gp, %hi(_gp_disp)
1150   // addui $gp, $gp, %lo(_gp_disp)
1151   // addu  $gp, $gp, $reg
1152   // when support for position independent code is enabled.
1153   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1154     return;
1155
1156   // There's a GNU extension controlled by -mno-shared that allows
1157   // locally-binding symbols to be accessed using absolute addresses.
1158   // This is currently not supported. When supported -mno-shared makes
1159   // .cpload expand to:
1160   //   lui     $gp, %hi(__gnu_local_gp)
1161   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
1162
1163   StringRef SymName("_gp_disp");
1164   MCAssembler &MCA = getStreamer().getAssembler();
1165   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1166   MCA.registerSymbol(*GP_Disp);
1167
1168   MCInst TmpInst;
1169   TmpInst.setOpcode(Mips::LUi);
1170   TmpInst.addOperand(MCOperand::createReg(GPReg));
1171   const MCExpr *HiSym = MipsMCExpr::create(
1172       MipsMCExpr::MEK_HI,
1173       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1174                               MCA.getContext()),
1175       MCA.getContext());
1176   TmpInst.addOperand(MCOperand::createExpr(HiSym));
1177   getStreamer().EmitInstruction(TmpInst, STI);
1178
1179   TmpInst.clear();
1180
1181   TmpInst.setOpcode(Mips::ADDiu);
1182   TmpInst.addOperand(MCOperand::createReg(GPReg));
1183   TmpInst.addOperand(MCOperand::createReg(GPReg));
1184   const MCExpr *LoSym = MipsMCExpr::create(
1185       MipsMCExpr::MEK_LO,
1186       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1187                               MCA.getContext()),
1188       MCA.getContext());
1189   TmpInst.addOperand(MCOperand::createExpr(LoSym));
1190   getStreamer().EmitInstruction(TmpInst, STI);
1191
1192   TmpInst.clear();
1193
1194   TmpInst.setOpcode(Mips::ADDu);
1195   TmpInst.addOperand(MCOperand::createReg(GPReg));
1196   TmpInst.addOperand(MCOperand::createReg(GPReg));
1197   TmpInst.addOperand(MCOperand::createReg(RegNo));
1198   getStreamer().EmitInstruction(TmpInst, STI);
1199
1200   forbidModuleDirective();
1201 }
1202
1203 void MipsTargetELFStreamer::emitDirectiveCpLocal(unsigned RegNo) {
1204   if (Pic)
1205     MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
1206 }
1207
1208 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1209     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1210     const MCSubtargetInfo *STI) {
1211   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1212   // .cprestore offset
1213   // When PIC mode is enabled and the O32 ABI is used, this directive expands
1214   // to:
1215   //    sw $gp, offset($sp)
1216   // and adds a corresponding LW after every JAL.
1217
1218   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1219   // is used in non-PIC mode.
1220   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1221     return true;
1222
1223   // Store the $gp on the stack.
1224   emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
1225                          STI);
1226   return true;
1227 }
1228
1229 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1230                                                  int RegOrOffset,
1231                                                  const MCSymbol &Sym,
1232                                                  bool IsReg) {
1233   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1234   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1235     return;
1236
1237   forbidModuleDirective();
1238
1239   MCAssembler &MCA = getStreamer().getAssembler();
1240   MCInst Inst;
1241
1242   // Either store the old $gp in a register or on the stack
1243   if (IsReg) {
1244     // move $save, $gpreg
1245     emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
1246   } else {
1247     // sd $gpreg, offset($sp)
1248     emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
1249   }
1250
1251   if (getABI().IsN32()) {
1252     MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1253     const MipsMCExpr *HiExpr = MipsMCExpr::create(
1254         MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1255         MCA.getContext());
1256     const MipsMCExpr *LoExpr = MipsMCExpr::create(
1257         MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1258         MCA.getContext());
1259
1260     // lui $gp, %hi(__gnu_local_gp)
1261     emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1262
1263     // addiu  $gp, $gp, %lo(__gnu_local_gp)
1264     emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1265             &STI);
1266
1267     return;
1268   }
1269
1270   const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1271       MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1272       MCA.getContext());
1273   const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1274       MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1275       MCA.getContext());
1276
1277   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1278   emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1279
1280   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1281   emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1282           &STI);
1283
1284   // daddu  $gp, $gp, $funcreg
1285   emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI);
1286 }
1287
1288 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1289                                                   bool SaveLocationIsRegister) {
1290   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1291   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1292     return;
1293
1294   MCInst Inst;
1295   // Either restore the old $gp from a register or on the stack
1296   if (SaveLocationIsRegister) {
1297     Inst.setOpcode(Mips::OR);
1298     Inst.addOperand(MCOperand::createReg(GPReg));
1299     Inst.addOperand(MCOperand::createReg(SaveLocation));
1300     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1301   } else {
1302     Inst.setOpcode(Mips::LD);
1303     Inst.addOperand(MCOperand::createReg(GPReg));
1304     Inst.addOperand(MCOperand::createReg(Mips::SP));
1305     Inst.addOperand(MCOperand::createImm(SaveLocation));
1306   }
1307   getStreamer().EmitInstruction(Inst, STI);
1308
1309   forbidModuleDirective();
1310 }
1311
1312 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1313   MCAssembler &MCA = getStreamer().getAssembler();
1314   MCContext &Context = MCA.getContext();
1315   MCStreamer &OS = getStreamer();
1316   MCSectionELF *Sec = Context.getELFSection(
1317       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1318   MCA.registerSection(*Sec);
1319   Sec->setAlignment(Align(8));
1320   OS.SwitchSection(Sec);
1321
1322   OS << ABIFlagsSection;
1323 }