lib/Target/RISCV/RISCV.td

   1 //===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 include "llvm/Target/Target.td"
  10
  11 //===----------------------------------------------------------------------===//
  12 // RISC-V subtarget features and instruction predicates.
  13 //===----------------------------------------------------------------------===//
  14
  15 def FeatureStdExtM
  16     : SubtargetFeature<"m", "HasStdExtM", "true",
  17                        "'M' (Integer Multiplication and Division)">;
  18 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
  19                            AssemblerPredicate<"FeatureStdExtM">;
  20
  21 def FeatureStdExtA
  22     : SubtargetFeature<"a", "HasStdExtA", "true",
  23                        "'A' (Atomic Instructions)">;
  24 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
  25                            AssemblerPredicate<"FeatureStdExtA">;
  26
  27 def FeatureStdExtF
  28     : SubtargetFeature<"f", "HasStdExtF", "true",
  29                        "'F' (Single-Precision Floating-Point)">;
  30 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
  31                            AssemblerPredicate<"FeatureStdExtF">;
  32
  33 def FeatureStdExtD
  34     : SubtargetFeature<"d", "HasStdExtD", "true",
  35                        "'D' (Double-Precision Floating-Point)",
  36                        [FeatureStdExtF]>;
  37 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
  38                            AssemblerPredicate<"FeatureStdExtD">;
  39
  40 def FeatureStdExtC
  41     : SubtargetFeature<"c", "HasStdExtC", "true",
  42                        "'C' (Compressed Instructions)">;
  43 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
  44                            AssemblerPredicate<"FeatureStdExtC">;
  45
  46 def FeatureRVCHints
  47     : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true",
  48                        "Enable RVC Hint Instructions.">;
  49 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
  50                             AssemblerPredicate<"FeatureRVCHints">;
  51
  52 def Feature64Bit
  53     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
  54 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
  55                        AssemblerPredicate<"Feature64Bit">;
  56 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
  57                        AssemblerPredicate<"!Feature64Bit">;
  58
  59 def RV64           : HwMode<"+64bit">;
  60 def RV32           : HwMode<"-64bit">;
  61
  62 def FeatureRV32E
  63     : SubtargetFeature<"e", "IsRV32E", "true",
  64                        "Implements RV32E (provides 16 rather than 32 GPRs)">;
  65 def IsRV32E : Predicate<"Subtarget->isRV32E()">,
  66                         AssemblerPredicate<"FeatureRV32E">;
  67
  68 def FeatureRelax
  69     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
  70                        "Enable Linker relaxation.">;
  71
  72 //===----------------------------------------------------------------------===//
  73 // Named operands for CSR instructions.
  74 //===----------------------------------------------------------------------===//
  75
  76 include "RISCVSystemOperands.td"
  77
  78 //===----------------------------------------------------------------------===//
  79 // Registers, calling conventions, instruction descriptions.
  80 //===----------------------------------------------------------------------===//
  81
  82 include "RISCVRegisterInfo.td"
  83 include "RISCVCallingConv.td"
  84 include "RISCVInstrInfo.td"
  85 include "RISCVRegisterBanks.td"
  86
  87 //===----------------------------------------------------------------------===//
  88 // RISC-V processors supported.
  89 //===----------------------------------------------------------------------===//
  90
  91 def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>;
  92
  93 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit,
  94                      FeatureRVCHints]>;
  95
  96 //===----------------------------------------------------------------------===//
  97 // Define the RISC-V target.
  98 //===----------------------------------------------------------------------===//
  99
 100 def RISCVInstrInfo : InstrInfo {
 101   let guessInstructionProperties = 0;
 102 }
 103
 104 def RISCVAsmParser : AsmParser {
 105   let ShouldEmitMatchRegisterAltName = 1;
 106   let AllowDuplicateRegisterNames = 1;
 107 }
 108
 109 def RISCVAsmWriter : AsmWriter {
 110   int PassSubtarget = 1;
 111 }
 112
 113 def RISCV : Target {
 114   let InstructionSet = RISCVInstrInfo;
 115   let AssemblyParsers = [RISCVAsmParser];
 116   let AssemblyWriters = [RISCVAsmWriter];
 117   let AllowRegisterRenaming = 1;
 118 }