[ARM] VQADD instructions
[llvm-complete.git] / lib / Target / Sparc / Disassembler / SparcDisassembler.cpp
blobbee331874e961f1204e8e775a8b27d59171d279d
1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the Sparc Disassembler.
11 //===----------------------------------------------------------------------===//
13 #include "MCTargetDesc/SparcMCTargetDesc.h"
14 #include "TargetInfo/SparcTargetInfo.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/TargetRegistry.h"
22 using namespace llvm;
24 #define DEBUG_TYPE "sparc-disassembler"
26 typedef MCDisassembler::DecodeStatus DecodeStatus;
28 namespace {
30 /// A disassembler class for Sparc.
31 class SparcDisassembler : public MCDisassembler {
32 public:
33 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
34 : MCDisassembler(STI, Ctx) {}
35 virtual ~SparcDisassembler() {}
37 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
38 ArrayRef<uint8_t> Bytes, uint64_t Address,
39 raw_ostream &VStream,
40 raw_ostream &CStream) const override;
44 static MCDisassembler *createSparcDisassembler(const Target &T,
45 const MCSubtargetInfo &STI,
46 MCContext &Ctx) {
47 return new SparcDisassembler(STI, Ctx);
51 extern "C" void LLVMInitializeSparcDisassembler() {
52 // Register the disassembler.
53 TargetRegistry::RegisterMCDisassembler(getTheSparcTarget(),
54 createSparcDisassembler);
55 TargetRegistry::RegisterMCDisassembler(getTheSparcV9Target(),
56 createSparcDisassembler);
57 TargetRegistry::RegisterMCDisassembler(getTheSparcelTarget(),
58 createSparcDisassembler);
61 static const unsigned IntRegDecoderTable[] = {
62 SP::G0, SP::G1, SP::G2, SP::G3,
63 SP::G4, SP::G5, SP::G6, SP::G7,
64 SP::O0, SP::O1, SP::O2, SP::O3,
65 SP::O4, SP::O5, SP::O6, SP::O7,
66 SP::L0, SP::L1, SP::L2, SP::L3,
67 SP::L4, SP::L5, SP::L6, SP::L7,
68 SP::I0, SP::I1, SP::I2, SP::I3,
69 SP::I4, SP::I5, SP::I6, SP::I7 };
71 static const unsigned FPRegDecoderTable[] = {
72 SP::F0, SP::F1, SP::F2, SP::F3,
73 SP::F4, SP::F5, SP::F6, SP::F7,
74 SP::F8, SP::F9, SP::F10, SP::F11,
75 SP::F12, SP::F13, SP::F14, SP::F15,
76 SP::F16, SP::F17, SP::F18, SP::F19,
77 SP::F20, SP::F21, SP::F22, SP::F23,
78 SP::F24, SP::F25, SP::F26, SP::F27,
79 SP::F28, SP::F29, SP::F30, SP::F31 };
81 static const unsigned DFPRegDecoderTable[] = {
82 SP::D0, SP::D16, SP::D1, SP::D17,
83 SP::D2, SP::D18, SP::D3, SP::D19,
84 SP::D4, SP::D20, SP::D5, SP::D21,
85 SP::D6, SP::D22, SP::D7, SP::D23,
86 SP::D8, SP::D24, SP::D9, SP::D25,
87 SP::D10, SP::D26, SP::D11, SP::D27,
88 SP::D12, SP::D28, SP::D13, SP::D29,
89 SP::D14, SP::D30, SP::D15, SP::D31 };
91 static const unsigned QFPRegDecoderTable[] = {
92 SP::Q0, SP::Q8, ~0U, ~0U,
93 SP::Q1, SP::Q9, ~0U, ~0U,
94 SP::Q2, SP::Q10, ~0U, ~0U,
95 SP::Q3, SP::Q11, ~0U, ~0U,
96 SP::Q4, SP::Q12, ~0U, ~0U,
97 SP::Q5, SP::Q13, ~0U, ~0U,
98 SP::Q6, SP::Q14, ~0U, ~0U,
99 SP::Q7, SP::Q15, ~0U, ~0U } ;
101 static const unsigned FCCRegDecoderTable[] = {
102 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
104 static const unsigned ASRRegDecoderTable[] = {
105 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
106 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
107 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
108 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
109 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
110 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
111 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
112 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
114 static const unsigned PRRegDecoderTable[] = {
115 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
116 SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
117 SP::OTHERWIN, SP::WSTATE
120 static const uint16_t IntPairDecoderTable[] = {
121 SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
122 SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
123 SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
124 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
127 static const unsigned CPRegDecoderTable[] = {
128 SP::C0, SP::C1, SP::C2, SP::C3,
129 SP::C4, SP::C5, SP::C6, SP::C7,
130 SP::C8, SP::C9, SP::C10, SP::C11,
131 SP::C12, SP::C13, SP::C14, SP::C15,
132 SP::C16, SP::C17, SP::C18, SP::C19,
133 SP::C20, SP::C21, SP::C22, SP::C23,
134 SP::C24, SP::C25, SP::C26, SP::C27,
135 SP::C28, SP::C29, SP::C30, SP::C31
139 static const uint16_t CPPairDecoderTable[] = {
140 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,
141 SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,
142 SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
143 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
146 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
147 unsigned RegNo,
148 uint64_t Address,
149 const void *Decoder) {
150 if (RegNo > 31)
151 return MCDisassembler::Fail;
152 unsigned Reg = IntRegDecoderTable[RegNo];
153 Inst.addOperand(MCOperand::createReg(Reg));
154 return MCDisassembler::Success;
157 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
158 unsigned RegNo,
159 uint64_t Address,
160 const void *Decoder) {
161 if (RegNo > 31)
162 return MCDisassembler::Fail;
163 unsigned Reg = IntRegDecoderTable[RegNo];
164 Inst.addOperand(MCOperand::createReg(Reg));
165 return MCDisassembler::Success;
169 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
170 unsigned RegNo,
171 uint64_t Address,
172 const void *Decoder) {
173 if (RegNo > 31)
174 return MCDisassembler::Fail;
175 unsigned Reg = FPRegDecoderTable[RegNo];
176 Inst.addOperand(MCOperand::createReg(Reg));
177 return MCDisassembler::Success;
181 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
182 unsigned RegNo,
183 uint64_t Address,
184 const void *Decoder) {
185 if (RegNo > 31)
186 return MCDisassembler::Fail;
187 unsigned Reg = DFPRegDecoderTable[RegNo];
188 Inst.addOperand(MCOperand::createReg(Reg));
189 return MCDisassembler::Success;
193 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
194 unsigned RegNo,
195 uint64_t Address,
196 const void *Decoder) {
197 if (RegNo > 31)
198 return MCDisassembler::Fail;
200 unsigned Reg = QFPRegDecoderTable[RegNo];
201 if (Reg == ~0U)
202 return MCDisassembler::Fail;
203 Inst.addOperand(MCOperand::createReg(Reg));
204 return MCDisassembler::Success;
207 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst,
208 unsigned RegNo,
209 uint64_t Address,
210 const void *Decoder) {
211 if (RegNo > 31)
212 return MCDisassembler::Fail;
213 unsigned Reg = CPRegDecoderTable[RegNo];
214 Inst.addOperand(MCOperand::createReg(Reg));
215 return MCDisassembler::Success;
218 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
219 uint64_t Address,
220 const void *Decoder) {
221 if (RegNo > 3)
222 return MCDisassembler::Fail;
223 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
224 return MCDisassembler::Success;
227 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
228 uint64_t Address,
229 const void *Decoder) {
230 if (RegNo > 31)
231 return MCDisassembler::Fail;
232 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
233 return MCDisassembler::Success;
236 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
237 uint64_t Address,
238 const void *Decoder) {
239 if (RegNo >= array_lengthof(PRRegDecoderTable))
240 return MCDisassembler::Fail;
241 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo]));
242 return MCDisassembler::Success;
245 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
246 uint64_t Address, const void *Decoder) {
247 DecodeStatus S = MCDisassembler::Success;
249 if (RegNo > 31)
250 return MCDisassembler::Fail;
252 if ((RegNo & 1))
253 S = MCDisassembler::SoftFail;
255 unsigned RegisterPair = IntPairDecoderTable[RegNo/2];
256 Inst.addOperand(MCOperand::createReg(RegisterPair));
257 return S;
260 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,
261 uint64_t Address, const void *Decoder) {
262 if (RegNo > 31)
263 return MCDisassembler::Fail;
265 unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
266 Inst.addOperand(MCOperand::createReg(RegisterPair));
267 return MCDisassembler::Success;
270 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
271 const void *Decoder);
272 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
273 const void *Decoder);
274 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
275 const void *Decoder);
276 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
277 const void *Decoder);
278 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
279 const void *Decoder);
280 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
281 const void *Decoder);
282 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
283 const void *Decoder);
284 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
303 const void *Decoder);
304 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
305 const void *Decoder);
306 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
307 const void *Decoder);
308 static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address,
309 const void *Decoder);
311 #include "SparcGenDisassemblerTables.inc"
313 /// Read four bytes from the ArrayRef and return 32 bit word.
314 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
315 uint64_t &Size, uint32_t &Insn,
316 bool IsLittleEndian) {
317 // We want to read exactly 4 Bytes of data.
318 if (Bytes.size() < 4) {
319 Size = 0;
320 return MCDisassembler::Fail;
323 Insn = IsLittleEndian
324 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
325 (Bytes[3] << 24)
326 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
327 (Bytes[0] << 24);
329 return MCDisassembler::Success;
332 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
333 ArrayRef<uint8_t> Bytes,
334 uint64_t Address,
335 raw_ostream &VStream,
336 raw_ostream &CStream) const {
337 uint32_t Insn;
338 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
339 DecodeStatus Result =
340 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
341 if (Result == MCDisassembler::Fail)
342 return MCDisassembler::Fail;
344 // Calling the auto-generated decoder function.
346 if (STI.getFeatureBits()[Sparc::FeatureV9])
348 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
350 else
352 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
354 if (Result != MCDisassembler::Fail)
355 return Result;
357 Result =
358 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
360 if (Result != MCDisassembler::Fail) {
361 Size = 4;
362 return Result;
365 return MCDisassembler::Fail;
369 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
370 const void *Decoder);
372 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
373 const void *Decoder,
374 bool isLoad, DecodeFunc DecodeRD) {
375 unsigned rd = fieldFromInstruction(insn, 25, 5);
376 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
377 bool isImm = fieldFromInstruction(insn, 13, 1);
378 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
379 unsigned asi = fieldFromInstruction(insn, 5, 8);
380 unsigned rs2 = 0;
381 unsigned simm13 = 0;
382 if (isImm)
383 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
384 else
385 rs2 = fieldFromInstruction(insn, 0, 5);
387 DecodeStatus status;
388 if (isLoad) {
389 status = DecodeRD(MI, rd, Address, Decoder);
390 if (status != MCDisassembler::Success)
391 return status;
394 // Decode rs1.
395 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
396 if (status != MCDisassembler::Success)
397 return status;
399 // Decode imm|rs2.
400 if (isImm)
401 MI.addOperand(MCOperand::createImm(simm13));
402 else {
403 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
404 if (status != MCDisassembler::Success)
405 return status;
408 if (hasAsi)
409 MI.addOperand(MCOperand::createImm(asi));
411 if (!isLoad) {
412 status = DecodeRD(MI, rd, Address, Decoder);
413 if (status != MCDisassembler::Success)
414 return status;
416 return MCDisassembler::Success;
419 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
420 const void *Decoder) {
421 return DecodeMem(Inst, insn, Address, Decoder, true,
422 DecodeIntRegsRegisterClass);
425 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
426 const void *Decoder) {
427 return DecodeMem(Inst, insn, Address, Decoder, true,
428 DecodeIntPairRegisterClass);
431 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
432 const void *Decoder) {
433 return DecodeMem(Inst, insn, Address, Decoder, true,
434 DecodeFPRegsRegisterClass);
437 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
438 const void *Decoder) {
439 return DecodeMem(Inst, insn, Address, Decoder, true,
440 DecodeDFPRegsRegisterClass);
443 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
444 const void *Decoder) {
445 return DecodeMem(Inst, insn, Address, Decoder, true,
446 DecodeQFPRegsRegisterClass);
449 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
450 const void *Decoder) {
451 return DecodeMem(Inst, insn, Address, Decoder, true,
452 DecodeCPRegsRegisterClass);
455 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
456 const void *Decoder) {
457 return DecodeMem(Inst, insn, Address, Decoder, true,
458 DecodeCPPairRegisterClass);
461 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
462 uint64_t Address, const void *Decoder) {
463 return DecodeMem(Inst, insn, Address, Decoder, false,
464 DecodeIntRegsRegisterClass);
467 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
468 uint64_t Address, const void *Decoder) {
469 return DecodeMem(Inst, insn, Address, Decoder, false,
470 DecodeIntPairRegisterClass);
473 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
474 const void *Decoder) {
475 return DecodeMem(Inst, insn, Address, Decoder, false,
476 DecodeFPRegsRegisterClass);
479 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
480 uint64_t Address, const void *Decoder) {
481 return DecodeMem(Inst, insn, Address, Decoder, false,
482 DecodeDFPRegsRegisterClass);
485 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
486 uint64_t Address, const void *Decoder) {
487 return DecodeMem(Inst, insn, Address, Decoder, false,
488 DecodeQFPRegsRegisterClass);
491 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
492 uint64_t Address, const void *Decoder) {
493 return DecodeMem(Inst, insn, Address, Decoder, false,
494 DecodeCPRegsRegisterClass);
497 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
498 uint64_t Address, const void *Decoder) {
499 return DecodeMem(Inst, insn, Address, Decoder, false,
500 DecodeCPPairRegisterClass);
503 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
504 uint64_t Address, uint64_t Offset,
505 uint64_t Width, MCInst &MI,
506 const void *Decoder) {
507 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
508 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
509 Offset, Width);
512 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
513 uint64_t Address, const void *Decoder) {
514 unsigned tgt = fieldFromInstruction(insn, 0, 30);
515 tgt <<= 2;
516 if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
517 0, 30, MI, Decoder))
518 MI.addOperand(MCOperand::createImm(tgt));
519 return MCDisassembler::Success;
522 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
523 uint64_t Address, const void *Decoder) {
524 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
525 MI.addOperand(MCOperand::createImm(tgt));
526 return MCDisassembler::Success;
529 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
530 const void *Decoder) {
532 unsigned rd = fieldFromInstruction(insn, 25, 5);
533 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
534 unsigned isImm = fieldFromInstruction(insn, 13, 1);
535 unsigned rs2 = 0;
536 unsigned simm13 = 0;
537 if (isImm)
538 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
539 else
540 rs2 = fieldFromInstruction(insn, 0, 5);
542 // Decode RD.
543 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
544 if (status != MCDisassembler::Success)
545 return status;
547 // Decode RS1.
548 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
549 if (status != MCDisassembler::Success)
550 return status;
552 // Decode RS1 | SIMM13.
553 if (isImm)
554 MI.addOperand(MCOperand::createImm(simm13));
555 else {
556 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
557 if (status != MCDisassembler::Success)
558 return status;
560 return MCDisassembler::Success;
563 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
564 const void *Decoder) {
566 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
567 unsigned isImm = fieldFromInstruction(insn, 13, 1);
568 unsigned rs2 = 0;
569 unsigned simm13 = 0;
570 if (isImm)
571 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
572 else
573 rs2 = fieldFromInstruction(insn, 0, 5);
575 // Decode RS1.
576 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
577 if (status != MCDisassembler::Success)
578 return status;
580 // Decode RS2 | SIMM13.
581 if (isImm)
582 MI.addOperand(MCOperand::createImm(simm13));
583 else {
584 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
585 if (status != MCDisassembler::Success)
586 return status;
588 return MCDisassembler::Success;
591 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
592 const void *Decoder) {
594 unsigned rd = fieldFromInstruction(insn, 25, 5);
595 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
596 unsigned isImm = fieldFromInstruction(insn, 13, 1);
597 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
598 unsigned asi = fieldFromInstruction(insn, 5, 8);
599 unsigned rs2 = 0;
600 unsigned simm13 = 0;
601 if (isImm)
602 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
603 else
604 rs2 = fieldFromInstruction(insn, 0, 5);
606 // Decode RD.
607 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
608 if (status != MCDisassembler::Success)
609 return status;
611 // Decode RS1.
612 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
613 if (status != MCDisassembler::Success)
614 return status;
616 // Decode RS1 | SIMM13.
617 if (isImm)
618 MI.addOperand(MCOperand::createImm(simm13));
619 else {
620 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
621 if (status != MCDisassembler::Success)
622 return status;
625 if (hasAsi)
626 MI.addOperand(MCOperand::createImm(asi));
628 return MCDisassembler::Success;
631 static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address,
632 const void *Decoder) {
634 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
635 unsigned isImm = fieldFromInstruction(insn, 13, 1);
636 unsigned cc =fieldFromInstruction(insn, 25, 4);
637 unsigned rs2 = 0;
638 unsigned imm7 = 0;
639 if (isImm)
640 imm7 = fieldFromInstruction(insn, 0, 7);
641 else
642 rs2 = fieldFromInstruction(insn, 0, 5);
644 // Decode RS1.
645 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
646 if (status != MCDisassembler::Success)
647 return status;
649 // Decode RS1 | IMM7.
650 if (isImm)
651 MI.addOperand(MCOperand::createImm(imm7));
652 else {
653 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
654 if (status != MCDisassembler::Success)
655 return status;
658 // Decode CC
659 MI.addOperand(MCOperand::createImm(cc));
661 return MCDisassembler::Success;