lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp

   1 //===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This class prints an Sparc MCInst to a .s file.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "SparcInstPrinter.h"
  14 #include "Sparc.h"
  15 #include "llvm/MC/MCExpr.h"
  16 #include "llvm/MC/MCInst.h"
  17 #include "llvm/MC/MCRegisterInfo.h"
  18 #include "llvm/MC/MCSubtargetInfo.h"
  19 #include "llvm/MC/MCSymbol.h"
  20 #include "llvm/Support/raw_ostream.h"
  21 using namespace llvm;
  22
  23 #define DEBUG_TYPE "asm-printer"
  24
  25 // The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
  26 // namespace. But SPARC backend uses "SP" as its namespace.
  27 namespace llvm {
  28 namespace Sparc {
  29   using namespace SP;
  30 }
  31 }
  32
  33 #define GET_INSTRUCTION_NAME
  34 #define PRINT_ALIAS_INSTR
  35 #include "SparcGenAsmWriter.inc"
  36
  37 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const {
  38   return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0;
  39 }
  40
  41 void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
  42 {
  43   OS << '%' << StringRef(getRegisterName(RegNo)).lower();
  44 }
  45
  46 void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
  47                                  StringRef Annot, const MCSubtargetInfo &STI) {
  48   if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O))
  49     printInstruction(MI, STI, O);
  50   printAnnotation(O, Annot);
  51 }
  52
  53 bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI,
  54                                             const MCSubtargetInfo &STI,
  55                                             raw_ostream &O) {
  56   switch (MI->getOpcode()) {
  57   default: return false;
  58   case SP::JMPLrr:
  59   case SP::JMPLri: {
  60     if (MI->getNumOperands() != 3)
  61       return false;
  62     if (!MI->getOperand(0).isReg())
  63       return false;
  64     switch (MI->getOperand(0).getReg()) {
  65     default: return false;
  66     case SP::G0: // jmp $addr | ret | retl
  67       if (MI->getOperand(2).isImm() &&
  68           MI->getOperand(2).getImm() == 8) {
  69         switch(MI->getOperand(1).getReg()) {
  70         default: break;
  71         case SP::I7: O << "\tret"; return true;
  72         case SP::O7: O << "\tretl"; return true;
  73         }
  74       }
  75       O << "\tjmp "; printMemOperand(MI, 1, STI, O);
  76       return true;
  77     case SP::O7: // call $addr
  78       O << "\tcall "; printMemOperand(MI, 1, STI, O);
  79       return true;
  80     }
  81   }
  82   case SP::V9FCMPS:  case SP::V9FCMPD:  case SP::V9FCMPQ:
  83   case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {
  84     if (isV9(STI)
  85         || (MI->getNumOperands() != 3)
  86         || (!MI->getOperand(0).isReg())
  87         || (MI->getOperand(0).getReg() != SP::FCC0))
  88       return false;
  89     // if V8, skip printing %fcc0.
  90     switch(MI->getOpcode()) {
  91     default:
  92     case SP::V9FCMPS:  O << "\tfcmps "; break;
  93     case SP::V9FCMPD:  O << "\tfcmpd "; break;
  94     case SP::V9FCMPQ:  O << "\tfcmpq "; break;
  95     case SP::V9FCMPES: O << "\tfcmpes "; break;
  96     case SP::V9FCMPED: O << "\tfcmped "; break;
  97     case SP::V9FCMPEQ: O << "\tfcmpeq "; break;
  98     }
  99     printOperand(MI, 1, STI, O);
 100     O << ", ";
 101     printOperand(MI, 2, STI, O);
 102     return true;
 103   }
 104   }
 105 }
 106
 107 void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
 108                                     const MCSubtargetInfo &STI,
 109                                     raw_ostream &O) {
 110   const MCOperand &MO = MI->getOperand (opNum);
 111
 112   if (MO.isReg()) {
 113     printRegName(O, MO.getReg());
 114     return ;
 115   }
 116
 117   if (MO.isImm()) {
 118     switch (MI->getOpcode()) {
 119       default:
 120         O << (int)MO.getImm();
 121         return;
 122
 123       case SP::TICCri: // Fall through
 124       case SP::TICCrr: // Fall through
 125       case SP::TRAPri: // Fall through
 126       case SP::TRAPrr: // Fall through
 127       case SP::TXCCri: // Fall through
 128       case SP::TXCCrr: // Fall through
 129         // Only seven-bit values up to 127.
 130         O << ((int) MO.getImm() & 0x7f);
 131         return;
 132     }
 133   }
 134
 135   assert(MO.isExpr() && "Unknown operand kind in printOperand");
 136   MO.getExpr()->print(O, &MAI);
 137 }
 138
 139 void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
 140                                        const MCSubtargetInfo &STI,
 141                                        raw_ostream &O, const char *Modifier) {
 142   printOperand(MI, opNum, STI, O);
 143
 144   // If this is an ADD operand, emit it like normal operands.
 145   if (Modifier && !strcmp(Modifier, "arith")) {
 146     O << ", ";
 147     printOperand(MI, opNum+1, STI, O);
 148     return;
 149   }
 150   const MCOperand &MO = MI->getOperand(opNum+1);
 151
 152   if (MO.isReg() && MO.getReg() == SP::G0)
 153     return;   // don't print "+%g0"
 154   if (MO.isImm() && MO.getImm() == 0)
 155     return;   // don't print "+0"
 156
 157   O << "+";
 158
 159   printOperand(MI, opNum+1, STI, O);
 160 }
 161
 162 void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
 163                                       const MCSubtargetInfo &STI,
 164                                       raw_ostream &O) {
 165   int CC = (int)MI->getOperand(opNum).getImm();
 166   switch (MI->getOpcode()) {
 167   default: break;
 168   case SP::FBCOND:
 169   case SP::FBCONDA:
 170   case SP::BPFCC:
 171   case SP::BPFCCA:
 172   case SP::BPFCCNT:
 173   case SP::BPFCCANT:
 174   case SP::MOVFCCrr:  case SP::V9MOVFCCrr:
 175   case SP::MOVFCCri:  case SP::V9MOVFCCri:
 176   case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
 177   case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
 178   case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
 179     // Make sure CC is a fp conditional flag.
 180     CC = (CC < 16) ? (CC + 16) : CC;
 181     break;
 182   case SP::CBCOND:
 183   case SP::CBCONDA:
 184     // Make sure CC is a cp conditional flag.
 185     CC = (CC < 32) ? (CC + 32) : CC;
 186     break;
 187   }
 188   O << SPARCCondCodeToString((SPCC::CondCodes)CC);
 189 }
 190
 191 bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
 192                                    const MCSubtargetInfo &STI,
 193                                    raw_ostream &O) {
 194   llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX.");
 195   return true;
 196 }
 197
 198 void SparcInstPrinter::printMembarTag(const MCInst *MI, int opNum,
 199                                       const MCSubtargetInfo &STI,
 200                                       raw_ostream &O) {
 201   static const char *const TagNames[] = {
 202       "#LoadLoad",  "#StoreLoad", "#LoadStore", "#StoreStore",
 203       "#Lookaside", "#MemIssue",  "#Sync"};
 204
 205   unsigned Imm = MI->getOperand(opNum).getImm();
 206
 207   if (Imm > 127) {
 208     O << Imm;
 209     return;
 210   }
 211
 212   bool First = true;
 213   for (unsigned i = 0; i < sizeof(TagNames) / sizeof(char *); i++) {
 214     if (Imm & (1 << i)) {
 215       O << (First ? "" : " | ") << TagNames[i];
 216       First = false;
 217     }
 218   }
 219 }