lib/Target/Sparc/SparcISelLowering.h

   1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the interfaces that Sparc uses to lower LLVM code into a
  10 // selection DAG.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
  15 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
  16
  17 #include "Sparc.h"
  18 #include "llvm/CodeGen/TargetLowering.h"
  19
  20 namespace llvm {
  21   class SparcSubtarget;
  22
  23   namespace SPISD {
  24     enum NodeType : unsigned {
  25       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  26       CMPICC,      // Compare two GPR operands, set icc+xcc.
  27       CMPFCC,      // Compare two FP operands, set fcc.
  28       BRICC,       // Branch to dest on icc condition
  29       BRXCC,       // Branch to dest on xcc condition (64-bit only).
  30       BRFCC,       // Branch to dest on fcc condition
  31       SELECT_ICC,  // Select between two values using the current ICC flags.
  32       SELECT_XCC,  // Select between two values using the current XCC flags.
  33       SELECT_FCC,  // Select between two values using the current FCC flags.
  34
  35       Hi, Lo,      // Hi/Lo operations, typically on a global address.
  36
  37       FTOI,        // FP to Int within a FP register.
  38       ITOF,        // Int to FP within a FP register.
  39       FTOX,        // FP to Int64 within a FP register.
  40       XTOF,        // Int64 to FP within a FP register.
  41
  42       CALL,        // A call instruction.
  43       RET_FLAG,    // Return with a flag operand.
  44       GLOBAL_BASE_REG, // Global base reg for PIC.
  45       FLUSHW,      // FLUSH register windows to stack.
  46
  47       TLS_ADD,     // For Thread Local Storage (TLS).
  48       TLS_LD,
  49       TLS_CALL
  50     };
  51   }
  52
  53   class SparcTargetLowering : public TargetLowering {
  54     const SparcSubtarget *Subtarget;
  55   public:
  56     SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
  57     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
  58
  59     bool useSoftFloat() const override;
  60
  61     /// computeKnownBitsForTargetNode - Determine which of the bits specified
  62     /// in Mask are known to be either zero or one and return them in the
  63     /// KnownZero/KnownOne bitsets.
  64     void computeKnownBitsForTargetNode(const SDValue Op,
  65                                        KnownBits &Known,
  66                                        const APInt &DemandedElts,
  67                                        const SelectionDAG &DAG,
  68                                        unsigned Depth = 0) const override;
  69
  70     MachineBasicBlock *
  71     EmitInstrWithCustomInserter(MachineInstr &MI,
  72                                 MachineBasicBlock *MBB) const override;
  73
  74     const char *getTargetNodeName(unsigned Opcode) const override;
  75
  76     ConstraintType getConstraintType(StringRef Constraint) const override;
  77     ConstraintWeight
  78     getSingleConstraintMatchWeight(AsmOperandInfo &info,
  79                                    const char *constraint) const override;
  80     void LowerAsmOperandForConstraint(SDValue Op,
  81                                       std::string &Constraint,
  82                                       std::vector<SDValue> &Ops,
  83                                       SelectionDAG &DAG) const override;
  84
  85     unsigned
  86     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
  87       if (ConstraintCode == "o")
  88         return InlineAsm::Constraint_o;
  89       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
  90     }
  91
  92     std::pair<unsigned, const TargetRegisterClass *>
  93     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
  94                                  StringRef Constraint, MVT VT) const override;
  95
  96     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
  97     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
  98       return MVT::i32;
  99     }
 100
 101     Register getRegisterByName(const char* RegName, EVT VT,
 102                                const MachineFunction &MF) const override;
 103
 104     /// If a physical register, this returns the register that receives the
 105     /// exception address on entry to an EH pad.
 106     unsigned
 107     getExceptionPointerRegister(const Constant *PersonalityFn) const override {
 108       return SP::I0;
 109     }
 110
 111     /// If a physical register, this returns the register that receives the
 112     /// exception typeid on entry to a landing pad.
 113     unsigned
 114     getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
 115       return SP::I1;
 116     }
 117
 118     /// Override to support customized stack guard loading.
 119     bool useLoadStackGuardNode() const override;
 120     void insertSSPDeclarations(Module &M) const override;
 121
 122     /// getSetCCResultType - Return the ISD::SETCC ValueType
 123     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 124                            EVT VT) const override;
 125
 126     SDValue
 127     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 128                          const SmallVectorImpl<ISD::InputArg> &Ins,
 129                          const SDLoc &dl, SelectionDAG &DAG,
 130                          SmallVectorImpl<SDValue> &InVals) const override;
 131     SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,
 132                                     bool isVarArg,
 133                                     const SmallVectorImpl<ISD::InputArg> &Ins,
 134                                     const SDLoc &dl, SelectionDAG &DAG,
 135                                     SmallVectorImpl<SDValue> &InVals) const;
 136     SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,
 137                                     bool isVarArg,
 138                                     const SmallVectorImpl<ISD::InputArg> &Ins,
 139                                     const SDLoc &dl, SelectionDAG &DAG,
 140                                     SmallVectorImpl<SDValue> &InVals) const;
 141
 142     SDValue
 143       LowerCall(TargetLowering::CallLoweringInfo &CLI,
 144                 SmallVectorImpl<SDValue> &InVals) const override;
 145     SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
 146                          SmallVectorImpl<SDValue> &InVals) const;
 147     SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
 148                          SmallVectorImpl<SDValue> &InVals) const;
 149
 150     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 151                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 152                         const SmallVectorImpl<SDValue> &OutVals,
 153                         const SDLoc &dl, SelectionDAG &DAG) const override;
 154     SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
 155                            bool IsVarArg,
 156                            const SmallVectorImpl<ISD::OutputArg> &Outs,
 157                            const SmallVectorImpl<SDValue> &OutVals,
 158                            const SDLoc &DL, SelectionDAG &DAG) const;
 159     SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
 160                            bool IsVarArg,
 161                            const SmallVectorImpl<ISD::OutputArg> &Outs,
 162                            const SmallVectorImpl<SDValue> &OutVals,
 163                            const SDLoc &DL, SelectionDAG &DAG) const;
 164
 165     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 166     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 167     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 168     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 169
 170     SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
 171     SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
 172                          SelectionDAG &DAG) const;
 173     SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
 174
 175     SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
 176                                  const SDLoc &DL, SelectionDAG &DAG) const;
 177     SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
 178                         const char *LibFuncName,
 179                         unsigned numArgs) const;
 180     SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
 181                              const SDLoc &DL, SelectionDAG &DAG) const;
 182
 183     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 184
 185     SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 186
 187     SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
 188                                    SelectionDAG &DAG) const;
 189
 190     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 191
 192     bool ShouldShrinkFPConstant(EVT VT) const override {
 193       // Do not shrink FP constpool if VT == MVT::f128.
 194       // (ldd, call _Q_fdtoq) is more expensive than two ldds.
 195       return VT != MVT::f128;
 196     }
 197
 198     bool shouldInsertFencesForAtomic(const Instruction *I) const override {
 199       // FIXME: We insert fences for each atomics and generate
 200       // sub-optimal code for PSO/TSO. (Approximately nobody uses any
 201       // mode but TSO, which makes this even more silly)
 202       return true;
 203     }
 204
 205     AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
 206
 207     void ReplaceNodeResults(SDNode *N,
 208                             SmallVectorImpl<SDValue>& Results,
 209                             SelectionDAG &DAG) const override;
 210
 211     MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
 212                                       unsigned BROpcode) const;
 213   };
 214 } // end namespace llvm
 215
 216 #endif    // SPARC_ISELLOWERING_H