include/llvm/MCA/Context.h

   1 //===---------------------------- Context.h ---------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 ///
  10 /// This file defines a class for holding ownership of various simulated
  11 /// hardware units.  A Context also provides a utility routine for constructing
  12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
  13 /// stages.
  14 ///
  15 //===----------------------------------------------------------------------===//
  16
  17 #ifndef LLVM_MCA_CONTEXT_H
  18 #define LLVM_MCA_CONTEXT_H
  19
  20 #include "llvm/MC/MCRegisterInfo.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/MCA/HardwareUnits/HardwareUnit.h"
  23 #include "llvm/MCA/InstrBuilder.h"
  24 #include "llvm/MCA/Pipeline.h"
  25 #include "llvm/MCA/SourceMgr.h"
  26 #include <memory>
  27
  28 namespace llvm {
  29 namespace mca {
  30
  31 /// This is a convenience struct to hold the parameters necessary for creating
  32 /// the pre-built "default" out-of-order pipeline.
  33 struct PipelineOptions {
  34   PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS,
  35                   unsigned LQS, unsigned SQS, bool NoAlias,
  36                   bool ShouldEnableBottleneckAnalysis = false)
  37       : MicroOpQueueSize(UOPQSize), DecodersThroughput(DecThr),
  38         DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS),
  39         StoreQueueSize(SQS), AssumeNoAlias(NoAlias),
  40         EnableBottleneckAnalysis(ShouldEnableBottleneckAnalysis) {}
  41   unsigned MicroOpQueueSize;
  42   unsigned DecodersThroughput; // Instructions per cycle.
  43   unsigned DispatchWidth;
  44   unsigned RegisterFileSize;
  45   unsigned LoadQueueSize;
  46   unsigned StoreQueueSize;
  47   bool AssumeNoAlias;
  48   bool EnableBottleneckAnalysis;
  49 };
  50
  51 class Context {
  52   SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware;
  53   const MCRegisterInfo &MRI;
  54   const MCSubtargetInfo &STI;
  55
  56 public:
  57   Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
  58   Context(const Context &C) = delete;
  59   Context &operator=(const Context &C) = delete;
  60
  61   void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
  62     Hardware.push_back(std::move(H));
  63   }
  64
  65   /// Construct a basic pipeline for simulating an out-of-order pipeline.
  66   /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
  67   std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
  68                                                   InstrBuilder &IB,
  69                                                   SourceMgr &SrcMgr);
  70 };
  71
  72 } // namespace mca
  73 } // namespace llvm
  74 #endif // LLVM_MCA_CONTEXT_H