include/llvm/Support/ARMTargetParser.h

   1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements a target parser to recognise ARM hardware features
  10 // such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_SUPPORT_ARMTARGETPARSER_H
  15 #define LLVM_SUPPORT_ARMTARGETPARSER_H
  16
  17 #include "llvm/ADT/StringRef.h"
  18 #include "llvm/ADT/Triple.h"
  19 #include "llvm/Support/ARMBuildAttributes.h"
  20 #include <vector>
  21
  22 namespace llvm {
  23 namespace ARM {
  24
  25 // Arch extension modifiers for CPUs.
  26 // Note that this is not the same as the AArch64 list
  27 enum ArchExtKind : unsigned {
  28   AEK_INVALID =     0,
  29   AEK_NONE =        1,
  30   AEK_CRC =         1 << 1,
  31   AEK_CRYPTO =      1 << 2,
  32   AEK_FP =          1 << 3,
  33   AEK_HWDIVTHUMB =  1 << 4,
  34   AEK_HWDIVARM =    1 << 5,
  35   AEK_MP =          1 << 6,
  36   AEK_SIMD =        1 << 7,
  37   AEK_SEC =         1 << 8,
  38   AEK_VIRT =        1 << 9,
  39   AEK_DSP =         1 << 10,
  40   AEK_FP16 =        1 << 11,
  41   AEK_RAS =         1 << 12,
  42   AEK_SVE =         1 << 13,
  43   AEK_DOTPROD =     1 << 14,
  44   AEK_SHA2    =     1 << 15,
  45   AEK_AES     =     1 << 16,
  46   AEK_FP16FML =     1 << 17,
  47   AEK_SB      =     1 << 18,
  48   AEK_SVE2 =        1 << 19,
  49   AEK_SVE2AES =     1 << 20,
  50   AEK_SVE2SM4 =     1 << 21,
  51   AEK_SVE2SHA3 =    1 << 22,
  52   AEK_BITPERM =     1 << 23,
  53   AEK_FP_DP   =     1 << 24,
  54   AEK_LOB     =     1 << 25,
  55   // Unsupported extensions.
  56   AEK_OS = 0x8000000,
  57   AEK_IWMMXT = 0x10000000,
  58   AEK_IWMMXT2 = 0x20000000,
  59   AEK_MAVERICK = 0x40000000,
  60   AEK_XSCALE = 0x80000000,
  61 };
  62
  63 // List of Arch Extension names.
  64 // FIXME: TableGen this.
  65 struct ExtName {
  66   const char *NameCStr;
  67   size_t NameLength;
  68   unsigned ID;
  69   const char *Feature;
  70   const char *NegFeature;
  71
  72   StringRef getName() const { return StringRef(NameCStr, NameLength); }
  73 };
  74
  75 const ExtName ARCHExtNames[] = {
  76 #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)                       \
  77   {NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE},
  78 #include "ARMTargetParser.def"
  79 };
  80
  81 // List of HWDiv names (use getHWDivSynonym) and which architectural
  82 // features they correspond to (use getHWDivFeatures).
  83 // FIXME: TableGen this.
  84 const struct {
  85   const char *NameCStr;
  86   size_t NameLength;
  87   unsigned ID;
  88
  89   StringRef getName() const { return StringRef(NameCStr, NameLength); }
  90 } HWDivNames[] = {
  91 #define ARM_HW_DIV_NAME(NAME, ID) {NAME, sizeof(NAME) - 1, ID},
  92 #include "ARMTargetParser.def"
  93 };
  94
  95 // Arch names.
  96 enum class ArchKind {
  97 #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
  98 #include "ARMTargetParser.def"
  99 };
 100
 101 // List of CPU names and their arches.
 102 // The same CPU can have multiple arches and can be default on multiple arches.
 103 // When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
 104 // When this becomes table-generated, we'd probably need two tables.
 105 // FIXME: TableGen this.
 106 template <typename T> struct CpuNames {
 107   const char *NameCStr;
 108   size_t NameLength;
 109   T ArchID;
 110   bool Default; // is $Name the default CPU for $ArchID ?
 111   unsigned DefaultExtensions;
 112
 113   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 114 };
 115
 116 const CpuNames<ArchKind> CPUNames[] = {
 117 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)           \
 118   {NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
 119 #include "ARMTargetParser.def"
 120 };
 121
 122 // FPU names.
 123 enum FPUKind {
 124 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
 125 #include "ARMTargetParser.def"
 126   FK_LAST
 127 };
 128
 129 // FPU Version
 130 enum class FPUVersion {
 131   NONE,
 132   VFPV2,
 133   VFPV3,
 134   VFPV3_FP16,
 135   VFPV4,
 136   VFPV5,
 137   VFPV5_FULLFP16,
 138 };
 139
 140 // An FPU name restricts the FPU in one of three ways:
 141 enum class FPURestriction {
 142   None = 0, ///< No restriction
 143   D16,      ///< Only 16 D registers
 144   SP_D16    ///< Only single-precision instructions, with 16 D registers
 145 };
 146
 147 // An FPU name implies one of three levels of Neon support:
 148 enum class NeonSupportLevel {
 149   None = 0, ///< No Neon
 150   Neon,     ///< Neon
 151   Crypto    ///< Neon with Crypto
 152 };
 153
 154 // ISA kinds.
 155 enum class ISAKind { INVALID = 0, ARM, THUMB, AARCH64 };
 156
 157 // Endianness
 158 // FIXME: BE8 vs. BE32?
 159 enum class EndianKind { INVALID = 0, LITTLE, BIG };
 160
 161 // v6/v7/v8 Profile
 162 enum class ProfileKind { INVALID = 0, A, R, M };
 163
 164 // List of canonical FPU names (use getFPUSynonym) and which architectural
 165 // features they correspond to (use getFPUFeatures).
 166 // FIXME: TableGen this.
 167 // The entries must appear in the order listed in ARM::FPUKind for correct
 168 // indexing
 169 struct FPUName {
 170   const char *NameCStr;
 171   size_t NameLength;
 172   FPUKind ID;
 173   FPUVersion FPUVer;
 174   NeonSupportLevel NeonSupport;
 175   FPURestriction Restriction;
 176
 177   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 178 };
 179
 180 static const FPUName FPUNames[] = {
 181 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION)                \
 182   {NAME, sizeof(NAME) - 1, KIND, VERSION, NEON_SUPPORT, RESTRICTION},
 183 #include "llvm/Support/ARMTargetParser.def"
 184 };
 185
 186 // List of canonical arch names (use getArchSynonym).
 187 // This table also provides the build attribute fields for CPU arch
 188 // and Arch ID, according to the Addenda to the ARM ABI, chapters
 189 // 2.4 and 2.3.5.2 respectively.
 190 // FIXME: SubArch values were simplified to fit into the expectations
 191 // of the triples and are not conforming with their official names.
 192 // Check to see if the expectation should be changed.
 193 // FIXME: TableGen this.
 194 template <typename T> struct ArchNames {
 195   const char *NameCStr;
 196   size_t NameLength;
 197   const char *CPUAttrCStr;
 198   size_t CPUAttrLength;
 199   const char *SubArchCStr;
 200   size_t SubArchLength;
 201   unsigned DefaultFPU;
 202   unsigned ArchBaseExtensions;
 203   T ID;
 204   ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
 205
 206   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 207
 208   // CPU class in build attributes.
 209   StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); }
 210
 211   // Sub-Arch name.
 212   StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); }
 213 };
 214
 215 static const ArchNames<ArchKind> ARCHNames[] = {
 216 #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU,            \
 217                  ARCH_BASE_EXT)                                                \
 218   {NAME,         sizeof(NAME) - 1,                                             \
 219    CPU_ATTR,     sizeof(CPU_ATTR) - 1,                                         \
 220    SUB_ARCH,     sizeof(SUB_ARCH) - 1,                                         \
 221    ARCH_FPU,     ARCH_BASE_EXT,                                                \
 222    ArchKind::ID, ARCH_ATTR},
 223 #include "llvm/Support/ARMTargetParser.def"
 224 };
 225
 226 // Information by ID
 227 StringRef getFPUName(unsigned FPUKind);
 228 FPUVersion getFPUVersion(unsigned FPUKind);
 229 NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);
 230 FPURestriction getFPURestriction(unsigned FPUKind);
 231
 232 // FIXME: These should be moved to TargetTuple once it exists
 233 bool getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features);
 234 bool getHWDivFeatures(unsigned HWDivKind, std::vector<StringRef> &Features);
 235 bool getExtensionFeatures(unsigned Extensions,
 236                           std::vector<StringRef> &Features);
 237
 238 StringRef getArchName(ArchKind AK);
 239 unsigned getArchAttr(ArchKind AK);
 240 StringRef getCPUAttr(ArchKind AK);
 241 StringRef getSubArch(ArchKind AK);
 242 StringRef getArchExtName(unsigned ArchExtKind);
 243 StringRef getArchExtFeature(StringRef ArchExt);
 244 bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK, StringRef ArchExt,
 245                            std::vector<StringRef> &Features);
 246 StringRef getHWDivName(unsigned HWDivKind);
 247
 248 // Information by Name
 249 unsigned getDefaultFPU(StringRef CPU, ArchKind AK);
 250 unsigned getDefaultExtensions(StringRef CPU, ArchKind AK);
 251 StringRef getDefaultCPU(StringRef Arch);
 252 StringRef getCanonicalArchName(StringRef Arch);
 253 StringRef getFPUSynonym(StringRef FPU);
 254 StringRef getArchSynonym(StringRef Arch);
 255
 256 // Parser
 257 unsigned parseHWDiv(StringRef HWDiv);
 258 unsigned parseFPU(StringRef FPU);
 259 ArchKind parseArch(StringRef Arch);
 260 unsigned parseArchExt(StringRef ArchExt);
 261 ArchKind parseCPUArch(StringRef CPU);
 262 ISAKind parseArchISA(StringRef Arch);
 263 EndianKind parseArchEndian(StringRef Arch);
 264 ProfileKind parseArchProfile(StringRef Arch);
 265 unsigned parseArchVersion(StringRef Arch);
 266
 267 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
 268 StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
 269
 270 } // namespace ARM
 271 } // namespace llvm
 272
 273 #endif