[ARM] MVE integer min and max
[llvm-complete.git] / lib / MCA / Support.cpp
blobce1f0f6f211b510f57d4482dec41b68e3d38ad7d
1 //===--------------------- Support.cpp --------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file implements a few helper functions used by various pipeline
11 /// components.
12 ///
13 //===----------------------------------------------------------------------===//
15 #include "llvm/MCA/Support.h"
16 #include "llvm/MC/MCSchedule.h"
18 namespace llvm {
19 namespace mca {
21 #define DEBUG_TYPE "llvm-mca"
23 ResourceCycles &ResourceCycles::operator+=(const ResourceCycles &RHS) {
24 if (Denominator == RHS.Denominator)
25 Numerator += RHS.Numerator;
26 else {
27 // Create a common denominator for LHS and RHS by calculating the least
28 // common multiple from the GCD.
29 unsigned GCD = GreatestCommonDivisor64(Denominator, RHS.Denominator);
30 unsigned LCM = (Denominator * RHS.Denominator) / GCD;
31 unsigned LHSNumerator = Numerator * (LCM / Denominator);
32 unsigned RHSNumerator = RHS.Numerator * (LCM / RHS.Denominator);
33 Numerator = LHSNumerator + RHSNumerator;
34 Denominator = LCM;
36 return *this;
39 void computeProcResourceMasks(const MCSchedModel &SM,
40 MutableArrayRef<uint64_t> Masks) {
41 unsigned ProcResourceID = 0;
43 assert(Masks.size() == SM.getNumProcResourceKinds() &&
44 "Invalid number of elements");
45 // Resource at index 0 is the 'InvalidUnit'. Set an invalid mask for it.
46 Masks[0] = 0;
48 // Create a unique bitmask for every processor resource unit.
49 for (unsigned I = 1, E = SM.getNumProcResourceKinds(); I < E; ++I) {
50 const MCProcResourceDesc &Desc = *SM.getProcResource(I);
51 if (Desc.SubUnitsIdxBegin)
52 continue;
53 Masks[I] = 1ULL << ProcResourceID;
54 ProcResourceID++;
57 // Create a unique bitmask for every processor resource group.
58 for (unsigned I = 1, E = SM.getNumProcResourceKinds(); I < E; ++I) {
59 const MCProcResourceDesc &Desc = *SM.getProcResource(I);
60 if (!Desc.SubUnitsIdxBegin)
61 continue;
62 Masks[I] = 1ULL << ProcResourceID;
63 for (unsigned U = 0; U < Desc.NumUnits; ++U) {
64 uint64_t OtherMask = Masks[Desc.SubUnitsIdxBegin[U]];
65 Masks[I] |= OtherMask;
67 ProcResourceID++;
70 #ifndef NDEBUG
71 LLVM_DEBUG(dbgs() << "\nProcessor resource masks:"
72 << "\n");
73 for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
74 const MCProcResourceDesc &Desc = *SM.getProcResource(I);
75 LLVM_DEBUG(dbgs() << '[' << format_decimal(I,2) << "] " << " - "
76 << format_hex(Masks[I],16) << " - "
77 << Desc.Name << '\n');
79 #endif
82 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
83 unsigned NumMicroOps,
84 ArrayRef<unsigned> ProcResourceUsage) {
85 // The block throughput is bounded from above by the hardware dispatch
86 // throughput. That is because the DispatchWidth is an upper bound on the
87 // number of opcodes that can be part of a single dispatch group.
88 double Max = static_cast<double>(NumMicroOps) / DispatchWidth;
90 // The block throughput is also limited by the amount of hardware parallelism.
91 // The number of available resource units affects the resource pressure
92 // distribution, as well as how many blocks can be executed every cycle.
93 for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
94 unsigned ResourceCycles = ProcResourceUsage[I];
95 if (!ResourceCycles)
96 continue;
98 const MCProcResourceDesc &MCDesc = *SM.getProcResource(I);
99 double Throughput = static_cast<double>(ResourceCycles) / MCDesc.NumUnits;
100 Max = std::max(Max, Throughput);
103 // The block reciprocal throughput is computed as the MAX of:
104 // - (NumMicroOps / DispatchWidth)
105 // - (NumUnits / ResourceCycles) for every consumed processor resource.
106 return Max;
109 } // namespace mca
110 } // namespace llvm