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1 //===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 // Primary reference:
10 // PowerPC 440x6 Embedded Processor Core User's Manual.
11 // IBM (as updated in) 2010.
13 // The basic PPC 440 does not include a floating-point unit; the pipeline
14 // timings here are constructed to match the FP2 unit shipped with the
15 // PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers.
16 // References:
17 // S. Chatterjee, et al. Design and exploitation of a high-performance
18 // SIMD floating-point unit for Blue Gene/L.
19 // IBM J. Res. & Dev. 49 (2/3) March/May 2005.
20 // also:
21 // Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution:
22 // Blue Gene/P Application Development.
23 // IBM (as updated in) 2009.
25 //===----------------------------------------------------------------------===//
26 // Functional units on the PowerPC 440/450 chip sets
27 //
28 def P440_DISS1 : FuncUnit; // Issue unit 1
29 def P440_DISS2 : FuncUnit; // Issue unit 2
30 def P440_LRACC : FuncUnit; // Register access and dispatch for
31 // the simple integer (J-pipe) and
32 // load/store (L-pipe) pipelines
33 def P440_IRACC : FuncUnit; // Register access and dispatch for
34 // the complex integer (I-pipe) pipeline
35 def P440_FRACC : FuncUnit; // Register access and dispatch for
36 // the floating-point execution (F-pipe) pipeline
37 def P440_IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
38 def P440_IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
39 def P440_IWB : FuncUnit; // Write-back unit for the I pipeline
40 def P440_JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
41 def P440_JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
42 def P440_JWB : FuncUnit; // Write-back unit for the J pipeline
43 def P440_AGEN : FuncUnit; // Address generation for the L pipeline
44 def P440_CRD : FuncUnit; // D-cache access for the L pipeline
45 def P440_LWB : FuncUnit; // Write-back unit for the L pipeline
46 def P440_FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline
47 def P440_FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline
48 def P440_FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline
49 def P440_FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline
50 def P440_FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline
51 def P440_FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline
52 def P440_FWB : FuncUnit; // Write-back unit for the F pipeline
54 def P440_LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used
55 // to make sure that no lwarx/stwcx.
56 // instructions are issued while another
57 // lwarx/stwcx. is in the L pipe.
59 def P440_GPR_Bypass : Bypass; // The bypass for general-purpose regs.
60 def P440_FPR_Bypass : Bypass; // The bypass for floating-point regs.
62 // Notes:
63 // Instructions are held in the FRACC, LRACC and IRACC pipeline
64 // stages until their source operands become ready. Exceptions:
65 // - Store instructions will hold in the AGEN stage
66 // - The integer multiply-accumulate instruction will hold in
67 // the IEXE1 stage
68 //
69 // For most I-pipe operations, the result is available at the end of
70 // the IEXE1 stage. Operations such as multiply and divide must
71 // continue to execute in IEXE2 and IWB. Divide resides in IWB for
72 // 33 cycles (multiply also calculates its result in IWB). For all
73 // J-pipe instructions, the result is available
74 // at the end of the JEXE1 stage. Loads have a 3-cycle latency
75 // (data is not available until after the LWB stage).
76 //
77 // The L1 cache hit latency is four cycles for floating point loads
78 // and three cycles for integer loads.
79 //
80 // The stwcx. instruction requires both the LRACC and the IRACC
81 // dispatch stages. It must be issued from DISS0.
82 //
83 // All lwarx/stwcx. instructions hold in LRACC if another
84 // uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB.
85 //
86 // msync (a.k.a. sync) and mbar will hold in LWB until all load/store
87 // resources are empty. AGEN and CRD are held empty until the msync/mbar
88 // commits.
89 //
90 // Most floating-point instructions, computational and move,
91 // have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
92 // update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
93 // loads take 4 cycles (for L1 hit).
95 //
96 // This file defines the itinerary class data for the PPC 440 processor.
97 //
98 //===----------------------------------------------------------------------===//
101 def PPC440Itineraries : ProcessorItineraries<
102 [P440_DISS1, P440_DISS2, P440_FRACC, P440_IRACC, P440_IEXE1, P440_IEXE2,
103 P440_IWB, P440_LRACC, P440_JEXE1, P440_JEXE2, P440_JWB, P440_AGEN, P440_CRD,
104 P440_LWB, P440_FEXE1, P440_FEXE2, P440_FEXE3, P440_FEXE4, P440_FEXE5,
105 P440_FEXE6, P440_FWB, P440_LWARX_Hold],
106 [P440_GPR_Bypass, P440_FPR_Bypass], [
107 InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
108 InstrStage<1, [P440_IRACC, P440_LRACC]>,
109 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
110 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
111 InstrStage<1, [P440_IWB, P440_JWB]>],
112 [2, 0, 0],
113 [P440_GPR_Bypass,
114 P440_GPR_Bypass, P440_GPR_Bypass]>,
115 InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
116 InstrStage<1, [P440_IRACC, P440_LRACC]>,
117 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
118 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
119 InstrStage<1, [P440_IWB, P440_JWB]>],
120 [2, 0, 0],
121 [P440_GPR_Bypass,
122 P440_GPR_Bypass, P440_GPR_Bypass]>,
123 InstrItinData<IIC_IntISEL, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
124 InstrStage<1, [P440_IRACC, P440_LRACC]>,
125 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
126 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
127 InstrStage<1, [P440_IWB, P440_JWB]>],
128 [2, 0, 0, 0],
129 [P440_GPR_Bypass,
130 P440_GPR_Bypass, P440_GPR_Bypass, NoBypass]>,
131 InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
132 InstrStage<1, [P440_IRACC, P440_LRACC]>,
133 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
134 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
135 InstrStage<1, [P440_IWB, P440_JWB]>],
136 [2, 0, 0],
137 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
138 InstrItinData<IIC_IntDivW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
139 InstrStage<1, [P440_IRACC]>,
140 InstrStage<1, [P440_IEXE1]>,
141 InstrStage<1, [P440_IEXE2]>,
142 InstrStage<33, [P440_IWB]>],
143 [36, 0, 0],
144 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
145 InstrItinData<IIC_IntMFFS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
146 InstrStage<1, [P440_IRACC]>,
147 InstrStage<1, [P440_IEXE1]>,
148 InstrStage<1, [P440_IEXE2]>,
149 InstrStage<1, [P440_IWB]>],
150 [3, 0, 0],
151 [P440_GPR_Bypass,
152 P440_GPR_Bypass, P440_GPR_Bypass]>,
153 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
154 InstrStage<1, [P440_IRACC]>,
155 InstrStage<1, [P440_IEXE1]>,
156 InstrStage<1, [P440_IEXE2]>,
157 InstrStage<1, [P440_IWB]>],
158 [3, 0, 0],
159 [P440_GPR_Bypass,
160 P440_GPR_Bypass, P440_GPR_Bypass]>,
161 InstrItinData<IIC_IntMulHW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
162 InstrStage<1, [P440_IRACC]>,
163 InstrStage<1, [P440_IEXE1]>,
164 InstrStage<1, [P440_IEXE2]>,
165 InstrStage<1, [P440_IWB]>],
166 [4, 0, 0],
167 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
168 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
169 InstrStage<1, [P440_IRACC]>,
170 InstrStage<1, [P440_IEXE1]>,
171 InstrStage<1, [P440_IEXE2]>,
172 InstrStage<1, [P440_IWB]>],
173 [4, 0, 0],
174 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
175 InstrItinData<IIC_IntMulLI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
176 InstrStage<1, [P440_IRACC]>,
177 InstrStage<1, [P440_IEXE1]>,
178 InstrStage<1, [P440_IEXE2]>,
179 InstrStage<1, [P440_IWB]>],
180 [4, 0, 0],
181 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
182 InstrItinData<IIC_IntRotate, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
183 InstrStage<1, [P440_IRACC, P440_LRACC]>,
184 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
185 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
186 InstrStage<1, [P440_IWB, P440_JWB]>],
187 [2, 0, 0],
188 [P440_GPR_Bypass,
189 P440_GPR_Bypass, P440_GPR_Bypass]>,
190 InstrItinData<IIC_IntShift, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
191 InstrStage<1, [P440_IRACC, P440_LRACC]>,
192 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
193 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
194 InstrStage<1, [P440_IWB, P440_JWB]>],
195 [2, 0, 0],
196 [P440_GPR_Bypass,
197 P440_GPR_Bypass, P440_GPR_Bypass]>,
198 InstrItinData<IIC_IntTrapW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
199 InstrStage<1, [P440_IRACC]>,
200 InstrStage<1, [P440_IEXE1]>,
201 InstrStage<1, [P440_IEXE2]>,
202 InstrStage<1, [P440_IWB]>],
203 [2, 0],
204 [P440_GPR_Bypass, P440_GPR_Bypass]>,
205 InstrItinData<IIC_BrB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
206 InstrStage<1, [P440_IRACC]>,
207 InstrStage<1, [P440_IEXE1]>,
208 InstrStage<1, [P440_IEXE2]>,
209 InstrStage<1, [P440_IWB]>],
210 [4, 0],
211 [NoBypass, P440_GPR_Bypass]>,
212 InstrItinData<IIC_BrCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
213 InstrStage<1, [P440_IRACC]>,
214 InstrStage<1, [P440_IEXE1]>,
215 InstrStage<1, [P440_IEXE2]>,
216 InstrStage<1, [P440_IWB]>],
217 [4, 0, 0],
218 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
219 InstrItinData<IIC_BrMCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
220 InstrStage<1, [P440_IRACC]>,
221 InstrStage<1, [P440_IEXE1]>,
222 InstrStage<1, [P440_IEXE2]>,
223 InstrStage<1, [P440_IWB]>],
224 [4, 0, 0],
225 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
226 InstrItinData<IIC_BrMCRX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
227 InstrStage<1, [P440_IRACC]>,
228 InstrStage<1, [P440_IEXE1]>,
229 InstrStage<1, [P440_IEXE2]>,
230 InstrStage<1, [P440_IWB]>],
231 [4, 0, 0],
232 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
233 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
234 InstrStage<1, [P440_LRACC]>,
235 InstrStage<1, [P440_AGEN]>,
236 InstrStage<1, [P440_CRD]>,
237 InstrStage<1, [P440_LWB]>],
238 [1, 1],
239 [NoBypass, P440_GPR_Bypass]>,
240 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
241 InstrStage<1, [P440_LRACC]>,
242 InstrStage<1, [P440_AGEN]>,
243 InstrStage<1, [P440_CRD]>,
244 InstrStage<1, [P440_LWB]>],
245 [1, 1],
246 [NoBypass, P440_GPR_Bypass]>,
247 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
248 InstrStage<1, [P440_LRACC]>,
249 InstrStage<1, [P440_AGEN]>,
250 InstrStage<1, [P440_CRD]>,
251 InstrStage<1, [P440_LWB]>],
252 [1, 1],
253 [NoBypass, P440_GPR_Bypass]>,
254 InstrItinData<IIC_LdStLoad, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
255 InstrStage<1, [P440_LRACC]>,
256 InstrStage<1, [P440_AGEN]>,
257 InstrStage<1, [P440_CRD]>,
258 InstrStage<2, [P440_LWB]>],
259 [5, 1, 1],
260 [P440_GPR_Bypass, P440_GPR_Bypass]>,
261 InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
262 InstrStage<1, [P440_LRACC]>,
263 InstrStage<1, [P440_AGEN]>,
264 InstrStage<1, [P440_CRD]>,
265 InstrStage<2, [P440_LWB]>],
266 [5, 2, 1, 1],
267 [P440_GPR_Bypass, P440_GPR_Bypass]>,
268 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
269 InstrStage<1, [P440_LRACC]>,
270 InstrStage<1, [P440_AGEN]>,
271 InstrStage<1, [P440_CRD]>,
272 InstrStage<2, [P440_LWB]>],
273 [5, 2, 1, 1],
274 [P440_GPR_Bypass, P440_GPR_Bypass]>,
275 InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
276 InstrStage<1, [P440_LRACC]>,
277 InstrStage<1, [P440_AGEN]>,
278 InstrStage<1, [P440_CRD]>,
279 InstrStage<2, [P440_LWB]>],
280 [1, 1, 1],
281 [NoBypass, P440_GPR_Bypass]>,
282 InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
283 InstrStage<1, [P440_LRACC]>,
284 InstrStage<1, [P440_AGEN]>,
285 InstrStage<1, [P440_CRD]>,
286 InstrStage<1, [P440_LWB]>],
287 [4, 1, 1],
288 [NoBypass, P440_GPR_Bypass]>,
289 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
290 InstrStage<1, [P440_LRACC]>,
291 InstrStage<1, [P440_AGEN]>,
292 InstrStage<1, [P440_CRD]>,
293 InstrStage<1, [P440_LWB]>],
294 [1, 1, 1],
295 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
296 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
297 InstrStage<1, [P440_LRACC]>,
298 InstrStage<1, [P440_AGEN]>,
299 InstrStage<1, [P440_CRD]>,
300 InstrStage<1, [P440_LWB]>],
301 [2, 1, 1, 1],
302 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
303 InstrItinData<IIC_LdStLFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
304 InstrStage<1, [P440_LRACC]>,
305 InstrStage<1, [P440_AGEN]>,
306 InstrStage<1, [P440_CRD]>,
307 InstrStage<2, [P440_LWB]>],
308 [5, 1, 1],
309 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
310 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
311 InstrStage<1, [P440_LRACC]>,
312 InstrStage<1, [P440_AGEN]>,
313 InstrStage<1, [P440_CRD]>,
314 InstrStage<1, [P440_LWB]>],
315 [5, 2, 1, 1],
316 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
317 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
318 InstrStage<1, [P440_LRACC]>,
319 InstrStage<1, [P440_AGEN]>,
320 InstrStage<1, [P440_CRD]>,
321 InstrStage<1, [P440_LWB]>],
322 [5, 2, 1, 1],
323 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
324 InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
325 InstrStage<1, [P440_LRACC]>,
326 InstrStage<1, [P440_AGEN]>,
327 InstrStage<1, [P440_CRD]>,
328 InstrStage<1, [P440_LWB]>],
329 [4, 1, 1],
330 [NoBypass, P440_GPR_Bypass]>,
331 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
332 InstrStage<1, [P440_LRACC]>,
333 InstrStage<1, [P440_AGEN]>,
334 InstrStage<1, [P440_CRD]>,
335 InstrStage<1, [P440_LWB]>],
336 [4, 1, 1],
337 [NoBypass, P440_GPR_Bypass]>,
338 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
339 InstrStage<1, [P440_LRACC]>,
340 InstrStage<1, [P440_AGEN]>,
341 InstrStage<1, [P440_CRD]>,
342 InstrStage<1, [P440_LWB]>],
343 [4, 1, 1],
344 [NoBypass, P440_GPR_Bypass]>,
345 InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
346 InstrStage<1, [P440_LRACC]>,
347 InstrStage<1, [P440_AGEN]>,
348 InstrStage<1, [P440_CRD]>,
349 InstrStage<1, [P440_LWB]>],
350 [4, 1, 1],
351 [NoBypass, P440_GPR_Bypass]>,
352 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P440_DISS1]>,
353 InstrStage<1, [P440_IRACC], 0>,
354 InstrStage<4, [P440_LWARX_Hold], 0>,
355 InstrStage<1, [P440_LRACC]>,
356 InstrStage<1, [P440_AGEN]>,
357 InstrStage<1, [P440_CRD]>,
358 InstrStage<1, [P440_LWB]>],
359 [4, 1, 1],
360 [NoBypass, P440_GPR_Bypass]>,
361 InstrItinData<IIC_LdStSTD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
362 InstrStage<1, [P440_LRACC]>,
363 InstrStage<1, [P440_AGEN]>,
364 InstrStage<1, [P440_CRD]>,
365 InstrStage<2, [P440_LWB]>],
366 [4, 1, 1],
367 [NoBypass, P440_GPR_Bypass]>,
368 InstrItinData<IIC_LdStSTU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
369 InstrStage<1, [P440_LRACC]>,
370 InstrStage<1, [P440_AGEN]>,
371 InstrStage<1, [P440_CRD]>,
372 InstrStage<2, [P440_LWB]>],
373 [2, 1, 1, 1],
374 [NoBypass, P440_GPR_Bypass]>,
375 InstrItinData<IIC_LdStSTUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
376 InstrStage<1, [P440_LRACC]>,
377 InstrStage<1, [P440_AGEN]>,
378 InstrStage<1, [P440_CRD]>,
379 InstrStage<2, [P440_LWB]>],
380 [2, 1, 1, 1],
381 [NoBypass, P440_GPR_Bypass]>,
382 InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_DISS1]>,
383 InstrStage<1, [P440_IRACC], 0>,
384 InstrStage<4, [P440_LWARX_Hold], 0>,
385 InstrStage<1, [P440_LRACC]>,
386 InstrStage<1, [P440_AGEN]>,
387 InstrStage<1, [P440_CRD]>,
388 InstrStage<1, [P440_LWB]>],
389 [4, 1, 1],
390 [NoBypass, P440_GPR_Bypass]>,
391 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [P440_DISS1]>,
392 InstrStage<1, [P440_IRACC], 0>,
393 InstrStage<4, [P440_LWARX_Hold], 0>,
394 InstrStage<1, [P440_LRACC]>,
395 InstrStage<1, [P440_AGEN]>,
396 InstrStage<1, [P440_CRD]>,
397 InstrStage<1, [P440_LWB]>],
398 [4, 1, 1],
399 [NoBypass, P440_GPR_Bypass]>,
400 InstrItinData<IIC_LdStSync, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
401 InstrStage<1, [P440_LRACC]>,
402 InstrStage<3, [P440_AGEN], 1>,
403 InstrStage<2, [P440_CRD], 1>,
404 InstrStage<1, [P440_LWB]>]>,
405 InstrItinData<IIC_SprISYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
406 InstrStage<1, [P440_FRACC], 0>,
407 InstrStage<1, [P440_LRACC], 0>,
408 InstrStage<1, [P440_IRACC]>,
409 InstrStage<1, [P440_FEXE1], 0>,
410 InstrStage<1, [P440_AGEN], 0>,
411 InstrStage<1, [P440_JEXE1], 0>,
412 InstrStage<1, [P440_IEXE1]>,
413 InstrStage<1, [P440_FEXE2], 0>,
414 InstrStage<1, [P440_CRD], 0>,
415 InstrStage<1, [P440_JEXE2], 0>,
416 InstrStage<1, [P440_IEXE2]>,
417 InstrStage<6, [P440_FEXE3], 0>,
418 InstrStage<6, [P440_LWB], 0>,
419 InstrStage<6, [P440_JWB], 0>,
420 InstrStage<6, [P440_IWB]>]>,
421 InstrItinData<IIC_SprMFSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
422 InstrStage<1, [P440_IRACC]>,
423 InstrStage<1, [P440_IEXE1]>,
424 InstrStage<1, [P440_IEXE2]>,
425 InstrStage<1, [P440_IWB]>],
426 [2, 0],
427 [P440_GPR_Bypass, P440_GPR_Bypass]>,
428 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
429 InstrStage<1, [P440_IRACC]>,
430 InstrStage<1, [P440_IEXE1]>,
431 InstrStage<1, [P440_IEXE2]>,
432 InstrStage<1, [P440_IWB]>],
433 [2, 0],
434 [P440_GPR_Bypass, P440_GPR_Bypass]>,
435 InstrItinData<IIC_SprMTSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
436 InstrStage<1, [P440_IRACC]>,
437 InstrStage<1, [P440_IEXE1]>,
438 InstrStage<1, [P440_IEXE2]>,
439 InstrStage<3, [P440_IWB]>],
440 [5, 0],
441 [NoBypass, P440_GPR_Bypass]>,
442 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
443 InstrStage<1, [P440_IRACC]>,
444 InstrStage<1, [P440_IEXE1]>,
445 InstrStage<1, [P440_IEXE2]>,
446 InstrStage<1, [P440_IWB]>]>,
447 InstrItinData<IIC_SprMFCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
448 InstrStage<1, [P440_IRACC]>,
449 InstrStage<1, [P440_IEXE1]>,
450 InstrStage<1, [P440_IEXE2]>,
451 InstrStage<1, [P440_IWB]>],
452 [4, 0],
453 [NoBypass, P440_GPR_Bypass]>,
454 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
455 InstrStage<1, [P440_IRACC]>,
456 InstrStage<1, [P440_IEXE1]>,
457 InstrStage<1, [P440_IEXE2]>,
458 InstrStage<1, [P440_IWB]>],
459 [3, 0],
460 [P440_GPR_Bypass, P440_GPR_Bypass]>,
461 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
462 InstrStage<1, [P440_IRACC]>,
463 InstrStage<1, [P440_IEXE1]>,
464 InstrStage<1, [P440_IEXE2]>,
465 InstrStage<3, [P440_IWB]>],
466 [6, 0],
467 [NoBypass, P440_GPR_Bypass]>,
468 InstrItinData<IIC_SprMFTB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
469 InstrStage<1, [P440_IRACC]>,
470 InstrStage<1, [P440_IEXE1]>,
471 InstrStage<1, [P440_IEXE2]>,
472 InstrStage<3, [P440_IWB]>],
473 [6, 0],
474 [NoBypass, P440_GPR_Bypass]>,
475 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
476 InstrStage<1, [P440_IRACC]>,
477 InstrStage<1, [P440_IEXE1]>,
478 InstrStage<1, [P440_IEXE2]>,
479 InstrStage<3, [P440_IWB]>],
480 [6, 0],
481 [NoBypass, P440_GPR_Bypass]>,
482 InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
483 InstrStage<1, [P440_IRACC]>,
484 InstrStage<1, [P440_IEXE1]>,
485 InstrStage<1, [P440_IEXE2]>,
486 InstrStage<3, [P440_IWB]>],
487 [6, 0],
488 [NoBypass, P440_GPR_Bypass]>,
489 InstrItinData<IIC_SprRFI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
490 InstrStage<1, [P440_IRACC]>,
491 InstrStage<1, [P440_IEXE1]>,
492 InstrStage<1, [P440_IEXE2]>,
493 InstrStage<1, [P440_IWB]>],
494 [4, 0],
495 [NoBypass, P440_GPR_Bypass]>,
496 InstrItinData<IIC_SprSC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
497 InstrStage<1, [P440_IRACC]>,
498 InstrStage<1, [P440_IEXE1]>,
499 InstrStage<1, [P440_IEXE2]>,
500 InstrStage<1, [P440_IWB]>],
501 [4, 0],
502 [NoBypass, P440_GPR_Bypass]>,
503 InstrItinData<IIC_FPGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
504 InstrStage<1, [P440_FRACC]>,
505 InstrStage<1, [P440_FEXE1]>,
506 InstrStage<1, [P440_FEXE2]>,
507 InstrStage<1, [P440_FEXE3]>,
508 InstrStage<1, [P440_FEXE4]>,
509 InstrStage<1, [P440_FEXE5]>,
510 InstrStage<1, [P440_FEXE6]>,
511 InstrStage<1, [P440_FWB]>],
512 [6, 0, 0],
513 [P440_FPR_Bypass,
514 P440_FPR_Bypass, P440_FPR_Bypass]>,
515 InstrItinData<IIC_FPAddSub, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
516 InstrStage<1, [P440_FRACC]>,
517 InstrStage<1, [P440_FEXE1]>,
518 InstrStage<1, [P440_FEXE2]>,
519 InstrStage<1, [P440_FEXE3]>,
520 InstrStage<1, [P440_FEXE4]>,
521 InstrStage<1, [P440_FEXE5]>,
522 InstrStage<1, [P440_FEXE6]>,
523 InstrStage<1, [P440_FWB]>],
524 [6, 0, 0],
525 [P440_FPR_Bypass,
526 P440_FPR_Bypass, P440_FPR_Bypass]>,
527 InstrItinData<IIC_FPCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
528 InstrStage<1, [P440_FRACC]>,
529 InstrStage<1, [P440_FEXE1]>,
530 InstrStage<1, [P440_FEXE2]>,
531 InstrStage<1, [P440_FEXE3]>,
532 InstrStage<1, [P440_FEXE4]>,
533 InstrStage<1, [P440_FEXE5]>,
534 InstrStage<1, [P440_FEXE6]>,
535 InstrStage<1, [P440_FWB]>],
536 [6, 0, 0],
537 [P440_FPR_Bypass, P440_FPR_Bypass,
538 P440_FPR_Bypass]>,
539 InstrItinData<IIC_FPDivD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
540 InstrStage<1, [P440_FRACC]>,
541 InstrStage<1, [P440_FEXE1]>,
542 InstrStage<1, [P440_FEXE2]>,
543 InstrStage<1, [P440_FEXE3]>,
544 InstrStage<1, [P440_FEXE4]>,
545 InstrStage<1, [P440_FEXE5]>,
546 InstrStage<1, [P440_FEXE6]>,
547 InstrStage<25, [P440_FWB]>],
548 [31, 0, 0],
549 [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
550 InstrItinData<IIC_FPDivS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
551 InstrStage<1, [P440_FRACC]>,
552 InstrStage<1, [P440_FEXE1]>,
553 InstrStage<1, [P440_FEXE2]>,
554 InstrStage<1, [P440_FEXE3]>,
555 InstrStage<1, [P440_FEXE4]>,
556 InstrStage<1, [P440_FEXE5]>,
557 InstrStage<1, [P440_FEXE6]>,
558 InstrStage<13, [P440_FWB]>],
559 [19, 0, 0],
560 [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
561 InstrItinData<IIC_FPFused, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
562 InstrStage<1, [P440_FRACC]>,
563 InstrStage<1, [P440_FEXE1]>,
564 InstrStage<1, [P440_FEXE2]>,
565 InstrStage<1, [P440_FEXE3]>,
566 InstrStage<1, [P440_FEXE4]>,
567 InstrStage<1, [P440_FEXE5]>,
568 InstrStage<1, [P440_FEXE6]>,
569 InstrStage<1, [P440_FWB]>],
570 [6, 0, 0, 0],
571 [P440_FPR_Bypass,
572 P440_FPR_Bypass, P440_FPR_Bypass,
573 P440_FPR_Bypass]>,
574 InstrItinData<IIC_FPRes, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
575 InstrStage<1, [P440_FRACC]>,
576 InstrStage<1, [P440_FEXE1]>,
577 InstrStage<1, [P440_FEXE2]>,
578 InstrStage<1, [P440_FEXE3]>,
579 InstrStage<1, [P440_FEXE4]>,
580 InstrStage<1, [P440_FEXE5]>,
581 InstrStage<1, [P440_FEXE6]>,
582 InstrStage<1, [P440_FWB]>],
583 [6, 0],
584 [P440_FPR_Bypass, P440_FPR_Bypass]>
585 ]>;
587 // ===---------------------------------------------------------------------===//
588 // PPC440 machine model for scheduling and other instruction cost heuristics.
590 def PPC440Model : SchedMachineModel {
591 let IssueWidth = 2; // 2 instructions are dispatched per cycle.
592 let LoadLatency = 5; // Optimistic load latency assuming bypass.
593 // This is overriden by OperandCycles if the
594 // Itineraries are queried instead.
596 let CompleteModel = 0;
598 let Itineraries = PPC440Itineraries;
599 }