lib/Target/RISCV/RISCVSystemOperands.td

   1 //===- RISCVSystemOperands.td ----------------------------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the symbolic operands permitted for various kinds of
  10 // RISC-V system instruction.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "llvm/TableGen/SearchableTable.td"
  15
  16 //===----------------------------------------------------------------------===//
  17 // CSR (control and status register read/write) instruction options.
  18 //===----------------------------------------------------------------------===//
  19
  20 class SysReg<string name, bits<12> op> {
  21   string Name = name;
  22   bits<12> Encoding = op;
  23   // FIXME: add these additional fields when needed.
  24   // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
  25   // Privilege Mode: User = 0, System = 1 or Machine = 3.
  26   // bits<2> ReadWrite = op{11 - 10};
  27   // bits<2> XMode = op{9 - 8};
  28   // Check Extra field name and what bits 7-6 correspond to.
  29   // bits<2> Extra = op{7 - 6};
  30   // Register number without the privilege bits.
  31   // bits<6> Number = op{5 - 0};
  32   code FeaturesRequired = [{ {} }];
  33   bit isRV32Only = 0;
  34 }
  35
  36 def SysRegsList : GenericTable {
  37   let FilterClass = "SysReg";
  38   // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
  39   let Fields = [ "Name", "Encoding", "FeaturesRequired", "isRV32Only" ];
  40
  41   let PrimaryKey = [ "Encoding" ];
  42   let PrimaryKeyName = "lookupSysRegByEncoding";
  43 }
  44
  45 def lookupSysRegByName : SearchIndex {
  46   let Table = SysRegsList;
  47   let Key = [ "Name" ];
  48 }
  49
  50 // The following CSR encodings match those given in Tables 2.2,
  51 // 2.3, 2.4 and  2.5 in the RISC-V Instruction Set Manual
  52 // Volume II: Privileged Architecture.
  53
  54 //===--------------------------
  55 // User Trap Setup
  56 //===--------------------------
  57 def : SysReg<"ustatus", 0x000>;
  58 def : SysReg<"uie", 0x004>;
  59 def : SysReg<"utvec", 0x005>;
  60
  61 //===--------------------------
  62 // User Trap Handling
  63 //===--------------------------
  64 def : SysReg<"uscratch", 0x040>;
  65 def : SysReg<"uepc", 0x041>;
  66 def : SysReg<"ucause", 0x042>;
  67 def : SysReg<"utval", 0x043>;
  68 def : SysReg<"uip", 0x044>;
  69
  70 //===--------------------------
  71 // User Floating-Point CSRs
  72 //===--------------------------
  73
  74 def FFLAGS : SysReg<"fflags", 0x001>;
  75 def FRM    : SysReg<"frm", 0x002>;
  76 def FCSR   : SysReg<"fcsr", 0x003>;
  77
  78 //===--------------------------
  79 // User Counter/Timers
  80 //===--------------------------
  81 def CYCLE   : SysReg<"cycle", 0xC00>;
  82 def TIME    : SysReg<"time", 0xC01>;
  83 def INSTRET : SysReg<"instret", 0xC02>;
  84
  85 def : SysReg<"hpmcounter3", 0xC03>;
  86 def : SysReg<"hpmcounter4", 0xC04>;
  87 def : SysReg<"hpmcounter5", 0xC05>;
  88 def : SysReg<"hpmcounter6", 0xC06>;
  89 def : SysReg<"hpmcounter7", 0xC07>;
  90 def : SysReg<"hpmcounter8", 0xC08>;
  91 def : SysReg<"hpmcounter9", 0xC09>;
  92 def : SysReg<"hpmcounter10", 0xC0A>;
  93 def : SysReg<"hpmcounter11", 0xC0B>;
  94 def : SysReg<"hpmcounter12", 0xC0C>;
  95 def : SysReg<"hpmcounter13", 0xC0D>;
  96 def : SysReg<"hpmcounter14", 0xC0E>;
  97 def : SysReg<"hpmcounter15", 0xC0F>;
  98 def : SysReg<"hpmcounter16", 0xC10>;
  99 def : SysReg<"hpmcounter17", 0xC11>;
 100 def : SysReg<"hpmcounter18", 0xC12>;
 101 def : SysReg<"hpmcounter19", 0xC13>;
 102 def : SysReg<"hpmcounter20", 0xC14>;
 103 def : SysReg<"hpmcounter21", 0xC15>;
 104 def : SysReg<"hpmcounter22", 0xC16>;
 105 def : SysReg<"hpmcounter23", 0xC17>;
 106 def : SysReg<"hpmcounter24", 0xC18>;
 107 def : SysReg<"hpmcounter25", 0xC19>;
 108 def : SysReg<"hpmcounter26", 0xC1A>;
 109 def : SysReg<"hpmcounter27", 0xC1B>;
 110 def : SysReg<"hpmcounter28", 0xC1C>;
 111 def : SysReg<"hpmcounter29", 0xC1D>;
 112 def : SysReg<"hpmcounter30", 0xC1E>;
 113 def : SysReg<"hpmcounter31", 0xC1F>;
 114
 115 let isRV32Only = 1 in {
 116 def CYCLEH   : SysReg<"cycleh", 0xC80>;
 117 def TIMEH    : SysReg<"timeh", 0xC81>;
 118 def INSTRETH : SysReg<"instreth", 0xC82>;
 119
 120 def: SysReg<"hpmcounter3h", 0xC83>;
 121 def: SysReg<"hpmcounter4h", 0xC84>;
 122 def: SysReg<"hpmcounter5h", 0xC85>;
 123 def: SysReg<"hpmcounter6h", 0xC86>;
 124 def: SysReg<"hpmcounter7h", 0xC87>;
 125 def: SysReg<"hpmcounter8h", 0xC88>;
 126 def: SysReg<"hpmcounter9h", 0xC89>;
 127 def: SysReg<"hpmcounter10h", 0xC8A>;
 128 def: SysReg<"hpmcounter11h", 0xC8B>;
 129 def: SysReg<"hpmcounter12h", 0xC8C>;
 130 def: SysReg<"hpmcounter13h", 0xC8D>;
 131 def: SysReg<"hpmcounter14h", 0xC8E>;
 132 def: SysReg<"hpmcounter15h", 0xC8F>;
 133 def: SysReg<"hpmcounter16h", 0xC90>;
 134 def: SysReg<"hpmcounter17h", 0xC91>;
 135 def: SysReg<"hpmcounter18h", 0xC92>;
 136 def: SysReg<"hpmcounter19h", 0xC93>;
 137 def: SysReg<"hpmcounter20h", 0xC94>;
 138 def: SysReg<"hpmcounter21h", 0xC95>;
 139 def: SysReg<"hpmcounter22h", 0xC96>;
 140 def: SysReg<"hpmcounter23h", 0xC97>;
 141 def: SysReg<"hpmcounter24h", 0xC98>;
 142 def: SysReg<"hpmcounter25h", 0xC99>;
 143 def: SysReg<"hpmcounter26h", 0xC9A>;
 144 def: SysReg<"hpmcounter27h", 0xC9B>;
 145 def: SysReg<"hpmcounter28h", 0xC9C>;
 146 def: SysReg<"hpmcounter29h", 0xC9D>;
 147 def: SysReg<"hpmcounter30h", 0xC9E>;
 148 def: SysReg<"hpmcounter31h", 0xC9F>;
 149 }
 150
 151 //===--------------------------
 152 // Supervisor Trap Setup
 153 //===--------------------------
 154 def : SysReg<"sstatus", 0x100>;
 155 def : SysReg<"sedeleg", 0x102>;
 156 def : SysReg<"sideleg", 0x103>;
 157 def : SysReg<"sie", 0x104>;
 158 def : SysReg<"stvec", 0x105>;
 159 def : SysReg<"scounteren", 0x106>;
 160
 161 //===--------------------------
 162 // Supervisor Trap Handling
 163 //===--------------------------
 164 def : SysReg<"sscratch", 0x140>;
 165 def : SysReg<"sepc", 0x141>;
 166 def : SysReg<"scause", 0x142>;
 167 def : SysReg<"stval", 0x143>;
 168 def : SysReg<"sip", 0x144>;
 169
 170 //===-------------------------------------
 171 // Supervisor Protection and Translation
 172 //===-------------------------------------
 173 def : SysReg<"satp", 0x180>;
 174
 175 //===-----------------------------
 176 // Machine Information Registers
 177 //===-----------------------------
 178
 179 def : SysReg<"mvendorid", 0xF11>;
 180 def : SysReg<"marchid", 0xF12>;
 181 def : SysReg<"mimpid", 0xF13>;
 182 def : SysReg<"mhartid", 0xF14>;
 183
 184 //===-----------------------------
 185 // Machine Trap Setup
 186 //===-----------------------------
 187 def : SysReg<"mstatus", 0x300>;
 188 def : SysReg<"misa", 0x301>;
 189 def : SysReg<"medeleg", 0x302>;
 190 def : SysReg<"mideleg", 0x303>;
 191 def : SysReg<"mie", 0x304>;
 192 def : SysReg<"mtvec", 0x305>;
 193 def : SysReg<"mcounteren", 0x306>;
 194
 195 //===-----------------------------
 196 // Machine Trap Handling
 197 //===-----------------------------
 198 def : SysReg<"mscratch", 0x340>;
 199 def : SysReg<"mepc", 0x341>;
 200 def : SysReg<"mcause", 0x342>;
 201 def : SysReg<"mtval", 0x343>;
 202 def : SysReg<"mip", 0x344>;
 203
 204 //===----------------------------------
 205 // Machine Protection and Translation
 206 //===----------------------------------
 207 def : SysReg<"pmpcfg0", 0x3A0>;
 208 def : SysReg<"pmpcfg2", 0x3A2>;
 209 let isRV32Only = 1 in {
 210 def : SysReg<"pmpcfg1", 0x3A1>;
 211 def : SysReg<"pmpcfg3", 0x3A3>;
 212 }
 213
 214 def : SysReg<"pmpaddr0", 0x3B0>;
 215 def : SysReg<"pmpaddr1", 0x3B1>;
 216 def : SysReg<"pmpaddr2", 0x3B2>;
 217 def : SysReg<"pmpaddr3", 0x3B3>;
 218 def : SysReg<"pmpaddr4", 0x3B4>;
 219 def : SysReg<"pmpaddr5", 0x3B5>;
 220 def : SysReg<"pmpaddr6", 0x3B6>;
 221 def : SysReg<"pmpaddr7", 0x3B7>;
 222 def : SysReg<"pmpaddr8", 0x3B8>;
 223 def : SysReg<"pmpaddr9", 0x3B9>;
 224 def : SysReg<"pmpaddr10", 0x3BA>;
 225 def : SysReg<"pmpaddr11", 0x3BB>;
 226 def : SysReg<"pmpaddr12", 0x3BC>;
 227 def : SysReg<"pmpaddr13", 0x3BD>;
 228 def : SysReg<"pmpaddr14", 0x3BE>;
 229 def : SysReg<"pmpaddr15", 0x3BF>;
 230
 231
 232 //===--------------------------
 233 // Machine Counter and Timers
 234 //===--------------------------
 235 def : SysReg<"mcycle", 0xB00>;
 236 def : SysReg<"minstret", 0xB02>;
 237
 238 def : SysReg<"mhpmcounter3", 0xB03>;
 239 def : SysReg<"mhpmcounter4", 0xB04>;
 240 def : SysReg<"mhpmcounter5", 0xB05>;
 241 def : SysReg<"mhpmcounter6", 0xB06>;
 242 def : SysReg<"mhpmcounter7", 0xB07>;
 243 def : SysReg<"mhpmcounter8", 0xB08>;
 244 def : SysReg<"mhpmcounter9", 0xB09>;
 245 def : SysReg<"mhpmcounter10", 0xB0A>;
 246 def : SysReg<"mhpmcounter11", 0xB0B>;
 247 def : SysReg<"mhpmcounter12", 0xB0C>;
 248 def : SysReg<"mhpmcounter13", 0xB0D>;
 249 def : SysReg<"mhpmcounter14", 0xB0E>;
 250 def : SysReg<"mhpmcounter15", 0xB0F>;
 251 def : SysReg<"mhpmcounter16", 0xB10>;
 252 def : SysReg<"mhpmcounter17", 0xB11>;
 253 def : SysReg<"mhpmcounter18", 0xB12>;
 254 def : SysReg<"mhpmcounter19", 0xB13>;
 255 def : SysReg<"mhpmcounter20", 0xB14>;
 256 def : SysReg<"mhpmcounter21", 0xB15>;
 257 def : SysReg<"mhpmcounter22", 0xB16>;
 258 def : SysReg<"mhpmcounter23", 0xB17>;
 259 def : SysReg<"mhpmcounter24", 0xB18>;
 260 def : SysReg<"mhpmcounter25", 0xB19>;
 261 def : SysReg<"mhpmcounter26", 0xB1A>;
 262 def : SysReg<"mhpmcounter27", 0xB1B>;
 263 def : SysReg<"mhpmcounter28", 0xB1C>;
 264 def : SysReg<"mhpmcounter29", 0xB1D>;
 265 def : SysReg<"mhpmcounter30", 0xB1E>;
 266 def : SysReg<"mhpmcounter31", 0xB1F>;
 267
 268 let isRV32Only = 1 in {
 269 def: SysReg<"mcycleh", 0xB80>;
 270 def: SysReg<"minstreth", 0xB82>;
 271
 272 def: SysReg<"mhpmcounter3h", 0xB83>;
 273 def: SysReg<"mhpmcounter4h", 0xB84>;
 274 def: SysReg<"mhpmcounter5h", 0xB85>;
 275 def: SysReg<"mhpmcounter6h", 0xB86>;
 276 def: SysReg<"mhpmcounter7h", 0xB87>;
 277 def: SysReg<"mhpmcounter8h", 0xB88>;
 278 def: SysReg<"mhpmcounter9h", 0xB89>;
 279 def: SysReg<"mhpmcounter10h", 0xB8A>;
 280 def: SysReg<"mhpmcounter11h", 0xB8B>;
 281 def: SysReg<"mhpmcounter12h", 0xB8C>;
 282 def: SysReg<"mhpmcounter13h", 0xB8D>;
 283 def: SysReg<"mhpmcounter14h", 0xB8E>;
 284 def: SysReg<"mhpmcounter15h", 0xB8F>;
 285 def: SysReg<"mhpmcounter16h", 0xB90>;
 286 def: SysReg<"mhpmcounter17h", 0xB91>;
 287 def: SysReg<"mhpmcounter18h", 0xB92>;
 288 def: SysReg<"mhpmcounter19h", 0xB93>;
 289 def: SysReg<"mhpmcounter20h", 0xB94>;
 290 def: SysReg<"mhpmcounter21h", 0xB95>;
 291 def: SysReg<"mhpmcounter22h", 0xB96>;
 292 def: SysReg<"mhpmcounter23h", 0xB97>;
 293 def: SysReg<"mhpmcounter24h", 0xB98>;
 294 def: SysReg<"mhpmcounter25h", 0xB99>;
 295 def: SysReg<"mhpmcounter26h", 0xB9A>;
 296 def: SysReg<"mhpmcounter27h", 0xB9B>;
 297 def: SysReg<"mhpmcounter28h", 0xB9C>;
 298 def: SysReg<"mhpmcounter29h", 0xB9D>;
 299 def: SysReg<"mhpmcounter30h", 0xB9E>;
 300 def: SysReg<"mhpmcounter31h", 0xB9F>;
 301 }
 302
 303 //===--------------------------
 304 // Machine Counter Setup
 305 //===--------------------------
 306 def : SysReg<"mhpmevent3", 0x323>;
 307 def : SysReg<"mhpmevent4", 0x324>;
 308 def : SysReg<"mhpmevent5", 0x325>;
 309 def : SysReg<"mhpmevent6", 0x326>;
 310 def : SysReg<"mhpmevent7", 0x327>;
 311 def : SysReg<"mhpmevent8", 0x328>;
 312 def : SysReg<"mhpmevent9", 0x329>;
 313 def : SysReg<"mhpmevent10", 0x32A>;
 314 def : SysReg<"mhpmevent11", 0x32B>;
 315 def : SysReg<"mhpmevent12", 0x32C>;
 316 def : SysReg<"mhpmevent13", 0x32D>;
 317 def : SysReg<"mhpmevent14", 0x32E>;
 318 def : SysReg<"mhpmevent15", 0x32F>;
 319 def : SysReg<"mhpmevent16", 0x330>;
 320 def : SysReg<"mhpmevent17", 0x331>;
 321 def : SysReg<"mhpmevent18", 0x332>;
 322 def : SysReg<"mhpmevent19", 0x333>;
 323 def : SysReg<"mhpmevent20", 0x334>;
 324 def : SysReg<"mhpmevent21", 0x335>;
 325 def : SysReg<"mhpmevent22", 0x336>;
 326 def : SysReg<"mhpmevent23", 0x337>;
 327 def : SysReg<"mhpmevent24", 0x338>;
 328 def : SysReg<"mhpmevent25", 0x339>;
 329 def : SysReg<"mhpmevent26", 0x33A>;
 330 def : SysReg<"mhpmevent27", 0x33B>;
 331 def : SysReg<"mhpmevent28", 0x33C>;
 332 def : SysReg<"mhpmevent29", 0x33D>;
 333 def : SysReg<"mhpmevent30", 0x33E>;
 334 def : SysReg<"mhpmevent31", 0x33F>;
 335
 336 //===-----------------------------------------------
 337 // Debug/ Trace Registers (shared with Debug Mode)
 338 //===-----------------------------------------------
 339 def : SysReg<"tselect", 0x7A0>;
 340 def : SysReg<"tdata1", 0x7A1>;
 341 def : SysReg<"tdata2", 0x7A2>;
 342 def : SysReg<"tdata3", 0x7A3>;
 343
 344 //===-----------------------------------------------
 345 // Debug Mode Registers
 346 //===-----------------------------------------------
 347 def : SysReg<"dcsr", 0x7B0>;
 348 def : SysReg<"dpc", 0x7B1>;
 349 def : SysReg<"dscratch", 0x7B2>;