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[ARM] MVE integer min and max
[llvm-complete.git] / lib / Target / X86 / X86InstrInfo.cpp
blob38b66d8c8af9348ea70c7b9c1219c997daf13fd0
1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42
43 using namespace llvm;
44
45 #define DEBUG_TYPE "x86-instr-info"
46
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49
50 static cl::opt<bool>
51 NoFusing("disable-spill-fusing",
52 cl::desc("Disable fusing of spill code into instructions"),
53 cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56 cl::desc("Print instructions that the allocator wants to"
57 " fuse, but the X86 backend currently can't"),
58 cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61 cl::desc("Re-materialize load from stub in PIC mode"),
62 cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65 cl::desc("Clearance between two register writes "
66 "for inserting XOR to avoid partial "
67 "register update"),
68 cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71 cl::desc("How many idle instructions we would like before "
72 "certain undef register reads"),
73 cl::init(128), cl::Hidden);
74
75
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81 : X86::ADJCALLSTACKDOWN32),
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83 : X86::ADJCALLSTACKUP32),
84 X86::CATCHRET,
85 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86 Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88
89 bool
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91 unsigned &SrcReg, unsigned &DstReg,
92 unsigned &SubIdx) const {
93 switch (MI.getOpcode()) {
94 default: break;
95 case X86::MOVSX16rr8:
96 case X86::MOVZX16rr8:
97 case X86::MOVSX32rr8:
98 case X86::MOVZX32rr8:
99 case X86::MOVSX64rr8:
100 if (!Subtarget.is64Bit())
101 // It's not always legal to reference the low 8-bit of the larger
102 // register in 32-bit mode.
103 return false;
104 LLVM_FALLTHROUGH;
105 case X86::MOVSX32rr16:
106 case X86::MOVZX32rr16:
107 case X86::MOVSX64rr16:
108 case X86::MOVSX64rr32: {
109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110 // Be conservative.
111 return false;
112 SrcReg = MI.getOperand(1).getReg();
113 DstReg = MI.getOperand(0).getReg();
114 switch (MI.getOpcode()) {
115 default: llvm_unreachable("Unreachable!");
116 case X86::MOVSX16rr8:
117 case X86::MOVZX16rr8:
118 case X86::MOVSX32rr8:
119 case X86::MOVZX32rr8:
120 case X86::MOVSX64rr8:
121 SubIdx = X86::sub_8bit;
122 break;
123 case X86::MOVSX32rr16:
124 case X86::MOVZX32rr16:
125 case X86::MOVSX64rr16:
126 SubIdx = X86::sub_16bit;
127 break;
128 case X86::MOVSX64rr32:
129 SubIdx = X86::sub_32bit;
130 break;
131 }
132 return true;
133 }
134 }
135 return false;
136 }
137
138 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
139 const MachineFunction *MF = MI.getParent()->getParent();
140 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
141
142 if (isFrameInstr(MI)) {
143 unsigned StackAlign = TFI->getStackAlignment();
144 int SPAdj = alignTo(getFrameSize(MI), StackAlign);
145 SPAdj -= getFrameAdjustment(MI);
146 if (!isFrameSetup(MI))
147 SPAdj = -SPAdj;
148 return SPAdj;
149 }
150
151 // To know whether a call adjusts the stack, we need information
152 // that is bound to the following ADJCALLSTACKUP pseudo.
153 // Look for the next ADJCALLSTACKUP that follows the call.
154 if (MI.isCall()) {
155 const MachineBasicBlock *MBB = MI.getParent();
156 auto I = ++MachineBasicBlock::const_iterator(MI);
157 for (auto E = MBB->end(); I != E; ++I) {
158 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
159 I->isCall())
160 break;
161 }
162
163 // If we could not find a frame destroy opcode, then it has already
164 // been simplified, so we don't care.
165 if (I->getOpcode() != getCallFrameDestroyOpcode())
166 return 0;
167
168 return -(I->getOperand(1).getImm());
169 }
170
171 // Currently handle only PUSHes we can reasonably expect to see
172 // in call sequences
173 switch (MI.getOpcode()) {
174 default:
175 return 0;
176 case X86::PUSH32i8:
177 case X86::PUSH32r:
178 case X86::PUSH32rmm:
179 case X86::PUSH32rmr:
180 case X86::PUSHi32:
181 return 4;
182 case X86::PUSH64i8:
183 case X86::PUSH64r:
184 case X86::PUSH64rmm:
185 case X86::PUSH64rmr:
186 case X86::PUSH64i32:
187 return 8;
188 }
189 }
190
191 /// Return true and the FrameIndex if the specified
192 /// operand and follow operands form a reference to the stack frame.
193 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
194 int &FrameIndex) const {
195 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
196 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
197 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
198 MI.getOperand(Op + X86::AddrDisp).isImm() &&
199 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
200 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
201 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
202 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
203 return true;
204 }
205 return false;
206 }
207
208 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
209 switch (Opcode) {
210 default:
211 return false;
212 case X86::MOV8rm:
213 case X86::KMOVBkm:
214 MemBytes = 1;
215 return true;
216 case X86::MOV16rm:
217 case X86::KMOVWkm:
218 MemBytes = 2;
219 return true;
220 case X86::MOV32rm:
221 case X86::MOVSSrm:
222 case X86::MOVSSrm_alt:
223 case X86::VMOVSSrm:
224 case X86::VMOVSSrm_alt:
225 case X86::VMOVSSZrm:
226 case X86::VMOVSSZrm_alt:
227 case X86::KMOVDkm:
228 MemBytes = 4;
229 return true;
230 case X86::MOV64rm:
231 case X86::LD_Fp64m:
232 case X86::MOVSDrm:
233 case X86::MOVSDrm_alt:
234 case X86::VMOVSDrm:
235 case X86::VMOVSDrm_alt:
236 case X86::VMOVSDZrm:
237 case X86::VMOVSDZrm_alt:
238 case X86::MMX_MOVD64rm:
239 case X86::MMX_MOVQ64rm:
240 case X86::KMOVQkm:
241 MemBytes = 8;
242 return true;
243 case X86::MOVAPSrm:
244 case X86::MOVUPSrm:
245 case X86::MOVAPDrm:
246 case X86::MOVUPDrm:
247 case X86::MOVDQArm:
248 case X86::MOVDQUrm:
249 case X86::VMOVAPSrm:
250 case X86::VMOVUPSrm:
251 case X86::VMOVAPDrm:
252 case X86::VMOVUPDrm:
253 case X86::VMOVDQArm:
254 case X86::VMOVDQUrm:
255 case X86::VMOVAPSZ128rm:
256 case X86::VMOVUPSZ128rm:
257 case X86::VMOVAPSZ128rm_NOVLX:
258 case X86::VMOVUPSZ128rm_NOVLX:
259 case X86::VMOVAPDZ128rm:
260 case X86::VMOVUPDZ128rm:
261 case X86::VMOVDQU8Z128rm:
262 case X86::VMOVDQU16Z128rm:
263 case X86::VMOVDQA32Z128rm:
264 case X86::VMOVDQU32Z128rm:
265 case X86::VMOVDQA64Z128rm:
266 case X86::VMOVDQU64Z128rm:
267 MemBytes = 16;
268 return true;
269 case X86::VMOVAPSYrm:
270 case X86::VMOVUPSYrm:
271 case X86::VMOVAPDYrm:
272 case X86::VMOVUPDYrm:
273 case X86::VMOVDQAYrm:
274 case X86::VMOVDQUYrm:
275 case X86::VMOVAPSZ256rm:
276 case X86::VMOVUPSZ256rm:
277 case X86::VMOVAPSZ256rm_NOVLX:
278 case X86::VMOVUPSZ256rm_NOVLX:
279 case X86::VMOVAPDZ256rm:
280 case X86::VMOVUPDZ256rm:
281 case X86::VMOVDQU8Z256rm:
282 case X86::VMOVDQU16Z256rm:
283 case X86::VMOVDQA32Z256rm:
284 case X86::VMOVDQU32Z256rm:
285 case X86::VMOVDQA64Z256rm:
286 case X86::VMOVDQU64Z256rm:
287 MemBytes = 32;
288 return true;
289 case X86::VMOVAPSZrm:
290 case X86::VMOVUPSZrm:
291 case X86::VMOVAPDZrm:
292 case X86::VMOVUPDZrm:
293 case X86::VMOVDQU8Zrm:
294 case X86::VMOVDQU16Zrm:
295 case X86::VMOVDQA32Zrm:
296 case X86::VMOVDQU32Zrm:
297 case X86::VMOVDQA64Zrm:
298 case X86::VMOVDQU64Zrm:
299 MemBytes = 64;
300 return true;
301 }
302 }
303
304 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
305 switch (Opcode) {
306 default:
307 return false;
308 case X86::MOV8mr:
309 case X86::KMOVBmk:
310 MemBytes = 1;
311 return true;
312 case X86::MOV16mr:
313 case X86::KMOVWmk:
314 MemBytes = 2;
315 return true;
316 case X86::MOV32mr:
317 case X86::MOVSSmr:
318 case X86::VMOVSSmr:
319 case X86::VMOVSSZmr:
320 case X86::KMOVDmk:
321 MemBytes = 4;
322 return true;
323 case X86::MOV64mr:
324 case X86::ST_FpP64m:
325 case X86::MOVSDmr:
326 case X86::VMOVSDmr:
327 case X86::VMOVSDZmr:
328 case X86::MMX_MOVD64mr:
329 case X86::MMX_MOVQ64mr:
330 case X86::MMX_MOVNTQmr:
331 case X86::KMOVQmk:
332 MemBytes = 8;
333 return true;
334 case X86::MOVAPSmr:
335 case X86::MOVUPSmr:
336 case X86::MOVAPDmr:
337 case X86::MOVUPDmr:
338 case X86::MOVDQAmr:
339 case X86::MOVDQUmr:
340 case X86::VMOVAPSmr:
341 case X86::VMOVUPSmr:
342 case X86::VMOVAPDmr:
343 case X86::VMOVUPDmr:
344 case X86::VMOVDQAmr:
345 case X86::VMOVDQUmr:
346 case X86::VMOVUPSZ128mr:
347 case X86::VMOVAPSZ128mr:
348 case X86::VMOVUPSZ128mr_NOVLX:
349 case X86::VMOVAPSZ128mr_NOVLX:
350 case X86::VMOVUPDZ128mr:
351 case X86::VMOVAPDZ128mr:
352 case X86::VMOVDQA32Z128mr:
353 case X86::VMOVDQU32Z128mr:
354 case X86::VMOVDQA64Z128mr:
355 case X86::VMOVDQU64Z128mr:
356 case X86::VMOVDQU8Z128mr:
357 case X86::VMOVDQU16Z128mr:
358 MemBytes = 16;
359 return true;
360 case X86::VMOVUPSYmr:
361 case X86::VMOVAPSYmr:
362 case X86::VMOVUPDYmr:
363 case X86::VMOVAPDYmr:
364 case X86::VMOVDQUYmr:
365 case X86::VMOVDQAYmr:
366 case X86::VMOVUPSZ256mr:
367 case X86::VMOVAPSZ256mr:
368 case X86::VMOVUPSZ256mr_NOVLX:
369 case X86::VMOVAPSZ256mr_NOVLX:
370 case X86::VMOVUPDZ256mr:
371 case X86::VMOVAPDZ256mr:
372 case X86::VMOVDQU8Z256mr:
373 case X86::VMOVDQU16Z256mr:
374 case X86::VMOVDQA32Z256mr:
375 case X86::VMOVDQU32Z256mr:
376 case X86::VMOVDQA64Z256mr:
377 case X86::VMOVDQU64Z256mr:
378 MemBytes = 32;
379 return true;
380 case X86::VMOVUPSZmr:
381 case X86::VMOVAPSZmr:
382 case X86::VMOVUPDZmr:
383 case X86::VMOVAPDZmr:
384 case X86::VMOVDQU8Zmr:
385 case X86::VMOVDQU16Zmr:
386 case X86::VMOVDQA32Zmr:
387 case X86::VMOVDQU32Zmr:
388 case X86::VMOVDQA64Zmr:
389 case X86::VMOVDQU64Zmr:
390 MemBytes = 64;
391 return true;
392 }
393 return false;
394 }
395
396 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
397 int &FrameIndex) const {
398 unsigned Dummy;
399 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
400 }
401
402 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
403 int &FrameIndex,
404 unsigned &MemBytes) const {
405 if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
406 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
407 return MI.getOperand(0).getReg();
408 return 0;
409 }
410
411 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
412 int &FrameIndex) const {
413 unsigned Dummy;
414 if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
415 unsigned Reg;
416 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
417 return Reg;
418 // Check for post-frame index elimination operations
419 SmallVector<const MachineMemOperand *, 1> Accesses;
420 if (hasLoadFromStackSlot(MI, Accesses)) {
421 FrameIndex =
422 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
423 ->getFrameIndex();
424 return 1;
425 }
426 }
427 return 0;
428 }
429
430 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
431 int &FrameIndex) const {
432 unsigned Dummy;
433 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
434 }
435
436 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
437 int &FrameIndex,
438 unsigned &MemBytes) const {
439 if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
440 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
441 isFrameOperand(MI, 0, FrameIndex))
442 return MI.getOperand(X86::AddrNumOperands).getReg();
443 return 0;
444 }
445
446 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
447 int &FrameIndex) const {
448 unsigned Dummy;
449 if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
450 unsigned Reg;
451 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
452 return Reg;
453 // Check for post-frame index elimination operations
454 SmallVector<const MachineMemOperand *, 1> Accesses;
455 if (hasStoreToStackSlot(MI, Accesses)) {
456 FrameIndex =
457 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
458 ->getFrameIndex();
459 return 1;
460 }
461 }
462 return 0;
463 }
464
465 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
466 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
467 // Don't waste compile time scanning use-def chains of physregs.
468 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
469 return false;
470 bool isPICBase = false;
471 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
472 E = MRI.def_instr_end(); I != E; ++I) {
473 MachineInstr *DefMI = &*I;
474 if (DefMI->getOpcode() != X86::MOVPC32r)
475 return false;
476 assert(!isPICBase && "More than one PIC base?");
477 isPICBase = true;
478 }
479 return isPICBase;
480 }
481
482 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
483 AliasAnalysis *AA) const {
484 switch (MI.getOpcode()) {
485 default: break;
486 case X86::MOV8rm:
487 case X86::MOV8rm_NOREX:
488 case X86::MOV16rm:
489 case X86::MOV32rm:
490 case X86::MOV64rm:
491 case X86::MOVSSrm:
492 case X86::MOVSSrm_alt:
493 case X86::MOVSDrm:
494 case X86::MOVSDrm_alt:
495 case X86::MOVAPSrm:
496 case X86::MOVUPSrm:
497 case X86::MOVAPDrm:
498 case X86::MOVUPDrm:
499 case X86::MOVDQArm:
500 case X86::MOVDQUrm:
501 case X86::VMOVSSrm:
502 case X86::VMOVSSrm_alt:
503 case X86::VMOVSDrm:
504 case X86::VMOVSDrm_alt:
505 case X86::VMOVAPSrm:
506 case X86::VMOVUPSrm:
507 case X86::VMOVAPDrm:
508 case X86::VMOVUPDrm:
509 case X86::VMOVDQArm:
510 case X86::VMOVDQUrm:
511 case X86::VMOVAPSYrm:
512 case X86::VMOVUPSYrm:
513 case X86::VMOVAPDYrm:
514 case X86::VMOVUPDYrm:
515 case X86::VMOVDQAYrm:
516 case X86::VMOVDQUYrm:
517 case X86::MMX_MOVD64rm:
518 case X86::MMX_MOVQ64rm:
519 // AVX-512
520 case X86::VMOVSSZrm:
521 case X86::VMOVSSZrm_alt:
522 case X86::VMOVSDZrm:
523 case X86::VMOVSDZrm_alt:
524 case X86::VMOVAPDZ128rm:
525 case X86::VMOVAPDZ256rm:
526 case X86::VMOVAPDZrm:
527 case X86::VMOVAPSZ128rm:
528 case X86::VMOVAPSZ256rm:
529 case X86::VMOVAPSZ128rm_NOVLX:
530 case X86::VMOVAPSZ256rm_NOVLX:
531 case X86::VMOVAPSZrm:
532 case X86::VMOVDQA32Z128rm:
533 case X86::VMOVDQA32Z256rm:
534 case X86::VMOVDQA32Zrm:
535 case X86::VMOVDQA64Z128rm:
536 case X86::VMOVDQA64Z256rm:
537 case X86::VMOVDQA64Zrm:
538 case X86::VMOVDQU16Z128rm:
539 case X86::VMOVDQU16Z256rm:
540 case X86::VMOVDQU16Zrm:
541 case X86::VMOVDQU32Z128rm:
542 case X86::VMOVDQU32Z256rm:
543 case X86::VMOVDQU32Zrm:
544 case X86::VMOVDQU64Z128rm:
545 case X86::VMOVDQU64Z256rm:
546 case X86::VMOVDQU64Zrm:
547 case X86::VMOVDQU8Z128rm:
548 case X86::VMOVDQU8Z256rm:
549 case X86::VMOVDQU8Zrm:
550 case X86::VMOVUPDZ128rm:
551 case X86::VMOVUPDZ256rm:
552 case X86::VMOVUPDZrm:
553 case X86::VMOVUPSZ128rm:
554 case X86::VMOVUPSZ256rm:
555 case X86::VMOVUPSZ128rm_NOVLX:
556 case X86::VMOVUPSZ256rm_NOVLX:
557 case X86::VMOVUPSZrm: {
558 // Loads from constant pools are trivially rematerializable.
559 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
560 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
561 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
562 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
563 MI.isDereferenceableInvariantLoad(AA)) {
564 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
565 if (BaseReg == 0 || BaseReg == X86::RIP)
566 return true;
567 // Allow re-materialization of PIC load.
568 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
569 return false;
570 const MachineFunction &MF = *MI.getParent()->getParent();
571 const MachineRegisterInfo &MRI = MF.getRegInfo();
572 return regIsPICBase(BaseReg, MRI);
573 }
574 return false;
575 }
576
577 case X86::LEA32r:
578 case X86::LEA64r: {
579 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
580 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
581 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
582 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
583 // lea fi#, lea GV, etc. are all rematerializable.
584 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
585 return true;
586 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
587 if (BaseReg == 0)
588 return true;
589 // Allow re-materialization of lea PICBase + x.
590 const MachineFunction &MF = *MI.getParent()->getParent();
591 const MachineRegisterInfo &MRI = MF.getRegInfo();
592 return regIsPICBase(BaseReg, MRI);
593 }
594 return false;
595 }
596 }
597
598 // All other instructions marked M_REMATERIALIZABLE are always trivially
599 // rematerializable.
600 return true;
601 }
602
603 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
604 MachineBasicBlock::iterator I,
605 unsigned DestReg, unsigned SubIdx,
606 const MachineInstr &Orig,
607 const TargetRegisterInfo &TRI) const {
608 bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
609 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
610 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
611 // effects.
612 int Value;
613 switch (Orig.getOpcode()) {
614 case X86::MOV32r0: Value = 0; break;
615 case X86::MOV32r1: Value = 1; break;
616 case X86::MOV32r_1: Value = -1; break;
617 default:
618 llvm_unreachable("Unexpected instruction!");
619 }
620
621 const DebugLoc &DL = Orig.getDebugLoc();
622 BuildMI(MBB, I, DL, get(X86::MOV32ri))
623 .add(Orig.getOperand(0))
624 .addImm(Value);
625 } else {
626 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
627 MBB.insert(I, MI);
628 }
629
630 MachineInstr &NewMI = *std::prev(I);
631 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
632 }
633
634 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
635 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
636 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
637 MachineOperand &MO = MI.getOperand(i);
638 if (MO.isReg() && MO.isDef() &&
639 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
640 return true;
641 }
642 }
643 return false;
644 }
645
646 /// Check whether the shift count for a machine operand is non-zero.
647 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
648 unsigned ShiftAmtOperandIdx) {
649 // The shift count is six bits with the REX.W prefix and five bits without.
650 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
651 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
652 return Imm & ShiftCountMask;
653 }
654
655 /// Check whether the given shift count is appropriate
656 /// can be represented by a LEA instruction.
657 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
658 // Left shift instructions can be transformed into load-effective-address
659 // instructions if we can encode them appropriately.
660 // A LEA instruction utilizes a SIB byte to encode its scale factor.
661 // The SIB.scale field is two bits wide which means that we can encode any
662 // shift amount less than 4.
663 return ShAmt < 4 && ShAmt > 0;
664 }
665
666 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
667 unsigned Opc, bool AllowSP, unsigned &NewSrc,
668 bool &isKill, MachineOperand &ImplicitOp,
669 LiveVariables *LV) const {
670 MachineFunction &MF = *MI.getParent()->getParent();
671 const TargetRegisterClass *RC;
672 if (AllowSP) {
673 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
674 } else {
675 RC = Opc != X86::LEA32r ?
676 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
677 }
678 unsigned SrcReg = Src.getReg();
679
680 // For both LEA64 and LEA32 the register already has essentially the right
681 // type (32-bit or 64-bit) we may just need to forbid SP.
682 if (Opc != X86::LEA64_32r) {
683 NewSrc = SrcReg;
684 isKill = Src.isKill();
685 assert(!Src.isUndef() && "Undef op doesn't need optimization");
686
687 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
688 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
689 return false;
690
691 return true;
692 }
693
694 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
695 // another we need to add 64-bit registers to the final MI.
696 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
697 ImplicitOp = Src;
698 ImplicitOp.setImplicit();
699
700 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
701 isKill = Src.isKill();
702 assert(!Src.isUndef() && "Undef op doesn't need optimization");
703 } else {
704 // Virtual register of the wrong class, we have to create a temporary 64-bit
705 // vreg to feed into the LEA.
706 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
707 MachineInstr *Copy =
708 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
709 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
710 .add(Src);
711
712 // Which is obviously going to be dead after we're done with it.
713 isKill = true;
714
715 if (LV)
716 LV->replaceKillInstruction(SrcReg, MI, *Copy);
717 }
718
719 // We've set all the parameters without issue.
720 return true;
721 }
722
723 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
724 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
725 LiveVariables *LV, bool Is8BitOp) const {
726 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
727 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
728 assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
729 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
730 "Unexpected type for LEA transform");
731
732 // TODO: For a 32-bit target, we need to adjust the LEA variables with
733 // something like this:
734 // Opcode = X86::LEA32r;
735 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
736 // OutRegLEA =
737 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
738 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
739 if (!Subtarget.is64Bit())
740 return nullptr;
741
742 unsigned Opcode = X86::LEA64_32r;
743 unsigned InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
744 unsigned OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
745
746 // Build and insert into an implicit UNDEF value. This is OK because
747 // we will be shifting and then extracting the lower 8/16-bits.
748 // This has the potential to cause partial register stall. e.g.
749 // movw (%rbp,%rcx,2), %dx
750 // leal -65(%rdx), %esi
751 // But testing has shown this *does* help performance in 64-bit mode (at
752 // least on modern x86 machines).
753 MachineBasicBlock::iterator MBBI = MI.getIterator();
754 unsigned Dest = MI.getOperand(0).getReg();
755 unsigned Src = MI.getOperand(1).getReg();
756 bool IsDead = MI.getOperand(0).isDead();
757 bool IsKill = MI.getOperand(1).isKill();
758 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
759 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
760 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
761 MachineInstr *InsMI =
762 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
763 .addReg(InRegLEA, RegState::Define, SubReg)
764 .addReg(Src, getKillRegState(IsKill));
765
766 MachineInstrBuilder MIB =
767 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
768 switch (MIOpc) {
769 default: llvm_unreachable("Unreachable!");
770 case X86::SHL8ri:
771 case X86::SHL16ri: {
772 unsigned ShAmt = MI.getOperand(2).getImm();
773 MIB.addReg(0).addImm(1ULL << ShAmt)
774 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
775 break;
776 }
777 case X86::INC8r:
778 case X86::INC16r:
779 addRegOffset(MIB, InRegLEA, true, 1);
780 break;
781 case X86::DEC8r:
782 case X86::DEC16r:
783 addRegOffset(MIB, InRegLEA, true, -1);
784 break;
785 case X86::ADD8ri:
786 case X86::ADD8ri_DB:
787 case X86::ADD16ri:
788 case X86::ADD16ri8:
789 case X86::ADD16ri_DB:
790 case X86::ADD16ri8_DB:
791 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
792 break;
793 case X86::ADD8rr:
794 case X86::ADD8rr_DB:
795 case X86::ADD16rr:
796 case X86::ADD16rr_DB: {
797 unsigned Src2 = MI.getOperand(2).getReg();
798 bool IsKill2 = MI.getOperand(2).isKill();
799 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
800 unsigned InRegLEA2 = 0;
801 MachineInstr *InsMI2 = nullptr;
802 if (Src == Src2) {
803 // ADD8rr/ADD16rr killed %reg1028, %reg1028
804 // just a single insert_subreg.
805 addRegReg(MIB, InRegLEA, true, InRegLEA, false);
806 } else {
807 if (Subtarget.is64Bit())
808 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
809 else
810 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
811 // Build and insert into an implicit UNDEF value. This is OK because
812 // we will be shifting and then extracting the lower 8/16-bits.
813 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
814 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
815 .addReg(InRegLEA2, RegState::Define, SubReg)
816 .addReg(Src2, getKillRegState(IsKill2));
817 addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
818 }
819 if (LV && IsKill2 && InsMI2)
820 LV->replaceKillInstruction(Src2, MI, *InsMI2);
821 break;
822 }
823 }
824
825 MachineInstr *NewMI = MIB;
826 MachineInstr *ExtMI =
827 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
828 .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
829 .addReg(OutRegLEA, RegState::Kill, SubReg);
830
831 if (LV) {
832 // Update live variables.
833 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
834 LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
835 if (IsKill)
836 LV->replaceKillInstruction(Src, MI, *InsMI);
837 if (IsDead)
838 LV->replaceKillInstruction(Dest, MI, *ExtMI);
839 }
840
841 return ExtMI;
842 }
843
844 /// This method must be implemented by targets that
845 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
846 /// may be able to convert a two-address instruction into a true
847 /// three-address instruction on demand. This allows the X86 target (for
848 /// example) to convert ADD and SHL instructions into LEA instructions if they
849 /// would require register copies due to two-addressness.
850 ///
851 /// This method returns a null pointer if the transformation cannot be
852 /// performed, otherwise it returns the new instruction.
853 ///
854 MachineInstr *
855 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
856 MachineInstr &MI, LiveVariables *LV) const {
857 // The following opcodes also sets the condition code register(s). Only
858 // convert them to equivalent lea if the condition code register def's
859 // are dead!
860 if (hasLiveCondCodeDef(MI))
861 return nullptr;
862
863 MachineFunction &MF = *MI.getParent()->getParent();
864 // All instructions input are two-addr instructions. Get the known operands.
865 const MachineOperand &Dest = MI.getOperand(0);
866 const MachineOperand &Src = MI.getOperand(1);
867
868 // Ideally, operations with undef should be folded before we get here, but we
869 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
870 // Without this, we have to forward undef state to new register operands to
871 // avoid machine verifier errors.
872 if (Src.isUndef())
873 return nullptr;
874 if (MI.getNumOperands() > 2)
875 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
876 return nullptr;
877
878 MachineInstr *NewMI = nullptr;
879 bool Is64Bit = Subtarget.is64Bit();
880
881 bool Is8BitOp = false;
882 unsigned MIOpc = MI.getOpcode();
883 switch (MIOpc) {
884 default: llvm_unreachable("Unreachable!");
885 case X86::SHL64ri: {
886 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
887 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
888 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
889
890 // LEA can't handle RSP.
891 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
892 !MF.getRegInfo().constrainRegClass(Src.getReg(),
893 &X86::GR64_NOSPRegClass))
894 return nullptr;
895
896 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
897 .add(Dest)
898 .addReg(0)
899 .addImm(1ULL << ShAmt)
900 .add(Src)
901 .addImm(0)
902 .addReg(0);
903 break;
904 }
905 case X86::SHL32ri: {
906 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
907 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
908 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
909
910 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
911
912 // LEA can't handle ESP.
913 bool isKill;
914 unsigned SrcReg;
915 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
916 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
917 SrcReg, isKill, ImplicitOp, LV))
918 return nullptr;
919
920 MachineInstrBuilder MIB =
921 BuildMI(MF, MI.getDebugLoc(), get(Opc))
922 .add(Dest)
923 .addReg(0)
924 .addImm(1ULL << ShAmt)
925 .addReg(SrcReg, getKillRegState(isKill))
926 .addImm(0)
927 .addReg(0);
928 if (ImplicitOp.getReg() != 0)
929 MIB.add(ImplicitOp);
930 NewMI = MIB;
931
932 break;
933 }
934 case X86::SHL8ri:
935 Is8BitOp = true;
936 LLVM_FALLTHROUGH;
937 case X86::SHL16ri: {
938 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
939 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
940 if (!isTruncatedShiftCountForLEA(ShAmt))
941 return nullptr;
942 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
943 }
944 case X86::INC64r:
945 case X86::INC32r: {
946 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
947 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
948 (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
949 bool isKill;
950 unsigned SrcReg;
951 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
952 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
953 ImplicitOp, LV))
954 return nullptr;
955
956 MachineInstrBuilder MIB =
957 BuildMI(MF, MI.getDebugLoc(), get(Opc))
958 .add(Dest)
959 .addReg(SrcReg, getKillRegState(isKill));
960 if (ImplicitOp.getReg() != 0)
961 MIB.add(ImplicitOp);
962
963 NewMI = addOffset(MIB, 1);
964 break;
965 }
966 case X86::DEC64r:
967 case X86::DEC32r: {
968 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
969 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
970 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
971
972 bool isKill;
973 unsigned SrcReg;
974 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
975 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
976 ImplicitOp, LV))
977 return nullptr;
978
979 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
980 .add(Dest)
981 .addReg(SrcReg, getKillRegState(isKill));
982 if (ImplicitOp.getReg() != 0)
983 MIB.add(ImplicitOp);
984
985 NewMI = addOffset(MIB, -1);
986
987 break;
988 }
989 case X86::DEC8r:
990 case X86::INC8r:
991 Is8BitOp = true;
992 LLVM_FALLTHROUGH;
993 case X86::DEC16r:
994 case X86::INC16r:
995 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
996 case X86::ADD64rr:
997 case X86::ADD64rr_DB:
998 case X86::ADD32rr:
999 case X86::ADD32rr_DB: {
1000 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1001 unsigned Opc;
1002 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1003 Opc = X86::LEA64r;
1004 else
1005 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1006
1007 bool isKill;
1008 unsigned SrcReg;
1009 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1010 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1011 SrcReg, isKill, ImplicitOp, LV))
1012 return nullptr;
1013
1014 const MachineOperand &Src2 = MI.getOperand(2);
1015 bool isKill2;
1016 unsigned SrcReg2;
1017 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1018 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1019 SrcReg2, isKill2, ImplicitOp2, LV))
1020 return nullptr;
1021
1022 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1023 if (ImplicitOp.getReg() != 0)
1024 MIB.add(ImplicitOp);
1025 if (ImplicitOp2.getReg() != 0)
1026 MIB.add(ImplicitOp2);
1027
1028 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1029 if (LV && Src2.isKill())
1030 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1031 break;
1032 }
1033 case X86::ADD8rr:
1034 case X86::ADD8rr_DB:
1035 Is8BitOp = true;
1036 LLVM_FALLTHROUGH;
1037 case X86::ADD16rr:
1038 case X86::ADD16rr_DB:
1039 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1040 case X86::ADD64ri32:
1041 case X86::ADD64ri8:
1042 case X86::ADD64ri32_DB:
1043 case X86::ADD64ri8_DB:
1044 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1045 NewMI = addOffset(
1046 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1047 MI.getOperand(2));
1048 break;
1049 case X86::ADD32ri:
1050 case X86::ADD32ri8:
1051 case X86::ADD32ri_DB:
1052 case X86::ADD32ri8_DB: {
1053 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1054 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1055
1056 bool isKill;
1057 unsigned SrcReg;
1058 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1059 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1060 SrcReg, isKill, ImplicitOp, LV))
1061 return nullptr;
1062
1063 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1064 .add(Dest)
1065 .addReg(SrcReg, getKillRegState(isKill));
1066 if (ImplicitOp.getReg() != 0)
1067 MIB.add(ImplicitOp);
1068
1069 NewMI = addOffset(MIB, MI.getOperand(2));
1070 break;
1071 }
1072 case X86::ADD8ri:
1073 case X86::ADD8ri_DB:
1074 Is8BitOp = true;
1075 LLVM_FALLTHROUGH;
1076 case X86::ADD16ri:
1077 case X86::ADD16ri8:
1078 case X86::ADD16ri_DB:
1079 case X86::ADD16ri8_DB:
1080 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1081 case X86::VMOVDQU8Z128rmk:
1082 case X86::VMOVDQU8Z256rmk:
1083 case X86::VMOVDQU8Zrmk:
1084 case X86::VMOVDQU16Z128rmk:
1085 case X86::VMOVDQU16Z256rmk:
1086 case X86::VMOVDQU16Zrmk:
1087 case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1088 case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1089 case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
1090 case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1091 case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1092 case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
1093 case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
1094 case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
1095 case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
1096 case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
1097 case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
1098 case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: {
1099 unsigned Opc;
1100 switch (MIOpc) {
1101 default: llvm_unreachable("Unreachable!");
1102 case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
1103 case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
1104 case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
1105 case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1106 case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1107 case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
1108 case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1109 case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1110 case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1111 case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1112 case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1113 case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1114 case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1115 case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1116 case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1117 case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1118 case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1119 case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1120 case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1121 case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1122 case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1123 case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1124 case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1125 case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1126 case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1127 case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1128 case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1129 case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1130 case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1131 case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1132 }
1133
1134 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1135 .add(Dest)
1136 .add(MI.getOperand(2))
1137 .add(Src)
1138 .add(MI.getOperand(3))
1139 .add(MI.getOperand(4))
1140 .add(MI.getOperand(5))
1141 .add(MI.getOperand(6))
1142 .add(MI.getOperand(7));
1143 break;
1144 }
1145 case X86::VMOVDQU8Z128rrk:
1146 case X86::VMOVDQU8Z256rrk:
1147 case X86::VMOVDQU8Zrrk:
1148 case X86::VMOVDQU16Z128rrk:
1149 case X86::VMOVDQU16Z256rrk:
1150 case X86::VMOVDQU16Zrrk:
1151 case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1152 case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1153 case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
1154 case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1155 case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1156 case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
1157 case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
1158 case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
1159 case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
1160 case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
1161 case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
1162 case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
1163 unsigned Opc;
1164 switch (MIOpc) {
1165 default: llvm_unreachable("Unreachable!");
1166 case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
1167 case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
1168 case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
1169 case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1170 case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1171 case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
1172 case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1173 case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1174 case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1175 case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1176 case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1177 case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1178 case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1179 case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1180 case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1181 case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1182 case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1183 case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1184 case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1185 case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1186 case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1187 case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1188 case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1189 case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1190 case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1191 case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1192 case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1193 case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1194 case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1195 case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1196 }
1197
1198 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1199 .add(Dest)
1200 .add(MI.getOperand(2))
1201 .add(Src)
1202 .add(MI.getOperand(3));
1203 break;
1204 }
1205 }
1206
1207 if (!NewMI) return nullptr;
1208
1209 if (LV) { // Update live variables
1210 if (Src.isKill())
1211 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1212 if (Dest.isDead())
1213 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1214 }
1215
1216 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1217 return NewMI;
1218 }
1219
1220 /// This determines which of three possible cases of a three source commute
1221 /// the source indexes correspond to taking into account any mask operands.
1222 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1223 /// possible.
1224 /// Case 0 - Possible to commute the first and second operands.
1225 /// Case 1 - Possible to commute the first and third operands.
1226 /// Case 2 - Possible to commute the second and third operands.
1227 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1228 unsigned SrcOpIdx2) {
1229 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1230 if (SrcOpIdx1 > SrcOpIdx2)
1231 std::swap(SrcOpIdx1, SrcOpIdx2);
1232
1233 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1234 if (X86II::isKMasked(TSFlags)) {
1235 Op2++;
1236 Op3++;
1237 }
1238
1239 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1240 return 0;
1241 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1242 return 1;
1243 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1244 return 2;
1245 llvm_unreachable("Unknown three src commute case.");
1246 }
1247
1248 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1249 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1250 const X86InstrFMA3Group &FMA3Group) const {
1251
1252 unsigned Opc = MI.getOpcode();
1253
1254 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1255 // analysis. The commute optimization is legal only if all users of FMA*_Int
1256 // use only the lowest element of the FMA*_Int instruction. Such analysis are
1257 // not implemented yet. So, just return 0 in that case.
1258 // When such analysis are available this place will be the right place for
1259 // calling it.
1260 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1261 "Intrinsic instructions can't commute operand 1");
1262
1263 // Determine which case this commute is or if it can't be done.
1264 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1265 SrcOpIdx2);
1266 assert(Case < 3 && "Unexpected case number!");
1267
1268 // Define the FMA forms mapping array that helps to map input FMA form
1269 // to output FMA form to preserve the operation semantics after
1270 // commuting the operands.
1271 const unsigned Form132Index = 0;
1272 const unsigned Form213Index = 1;
1273 const unsigned Form231Index = 2;
1274 static const unsigned FormMapping[][3] = {
1275 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1276 // FMA132 A, C, b; ==> FMA231 C, A, b;
1277 // FMA213 B, A, c; ==> FMA213 A, B, c;
1278 // FMA231 C, A, b; ==> FMA132 A, C, b;
1279 { Form231Index, Form213Index, Form132Index },
1280 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1281 // FMA132 A, c, B; ==> FMA132 B, c, A;
1282 // FMA213 B, a, C; ==> FMA231 C, a, B;
1283 // FMA231 C, a, B; ==> FMA213 B, a, C;
1284 { Form132Index, Form231Index, Form213Index },
1285 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1286 // FMA132 a, C, B; ==> FMA213 a, B, C;
1287 // FMA213 b, A, C; ==> FMA132 b, C, A;
1288 // FMA231 c, A, B; ==> FMA231 c, B, A;
1289 { Form213Index, Form132Index, Form231Index }
1290 };
1291
1292 unsigned FMAForms[3];
1293 FMAForms[0] = FMA3Group.get132Opcode();
1294 FMAForms[1] = FMA3Group.get213Opcode();
1295 FMAForms[2] = FMA3Group.get231Opcode();
1296 unsigned FormIndex;
1297 for (FormIndex = 0; FormIndex < 3; FormIndex++)
1298 if (Opc == FMAForms[FormIndex])
1299 break;
1300
1301 // Everything is ready, just adjust the FMA opcode and return it.
1302 FormIndex = FormMapping[Case][FormIndex];
1303 return FMAForms[FormIndex];
1304 }
1305
1306 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1307 unsigned SrcOpIdx2) {
1308 // Determine which case this commute is or if it can't be done.
1309 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1310 SrcOpIdx2);
1311 assert(Case < 3 && "Unexpected case value!");
1312
1313 // For each case we need to swap two pairs of bits in the final immediate.
1314 static const uint8_t SwapMasks[3][4] = {
1315 { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1316 { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1317 { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1318 };
1319
1320 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1321 // Clear out the bits we are swapping.
1322 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1323 SwapMasks[Case][2] | SwapMasks[Case][3]);
1324 // If the immediate had a bit of the pair set, then set the opposite bit.
1325 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1326 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1327 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1328 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1329 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1330 }
1331
1332 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1333 // commuted.
1334 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1335 #define VPERM_CASES(Suffix) \
1336 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
1337 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
1338 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
1339 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
1340 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
1341 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
1342 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
1343 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
1344 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
1345 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
1346 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
1347 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
1348
1349 #define VPERM_CASES_BROADCAST(Suffix) \
1350 VPERM_CASES(Suffix) \
1351 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
1352 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
1353 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
1354 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1355 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1356 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
1357
1358 switch (Opcode) {
1359 default: return false;
1360 VPERM_CASES(B)
1361 VPERM_CASES_BROADCAST(D)
1362 VPERM_CASES_BROADCAST(PD)
1363 VPERM_CASES_BROADCAST(PS)
1364 VPERM_CASES_BROADCAST(Q)
1365 VPERM_CASES(W)
1366 return true;
1367 }
1368 #undef VPERM_CASES_BROADCAST
1369 #undef VPERM_CASES
1370 }
1371
1372 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1373 // from the I opcode to the T opcode and vice versa.
1374 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1375 #define VPERM_CASES(Orig, New) \
1376 case X86::Orig##128rr: return X86::New##128rr; \
1377 case X86::Orig##128rrkz: return X86::New##128rrkz; \
1378 case X86::Orig##128rm: return X86::New##128rm; \
1379 case X86::Orig##128rmkz: return X86::New##128rmkz; \
1380 case X86::Orig##256rr: return X86::New##256rr; \
1381 case X86::Orig##256rrkz: return X86::New##256rrkz; \
1382 case X86::Orig##256rm: return X86::New##256rm; \
1383 case X86::Orig##256rmkz: return X86::New##256rmkz; \
1384 case X86::Orig##rr: return X86::New##rr; \
1385 case X86::Orig##rrkz: return X86::New##rrkz; \
1386 case X86::Orig##rm: return X86::New##rm; \
1387 case X86::Orig##rmkz: return X86::New##rmkz;
1388
1389 #define VPERM_CASES_BROADCAST(Orig, New) \
1390 VPERM_CASES(Orig, New) \
1391 case X86::Orig##128rmb: return X86::New##128rmb; \
1392 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1393 case X86::Orig##256rmb: return X86::New##256rmb; \
1394 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1395 case X86::Orig##rmb: return X86::New##rmb; \
1396 case X86::Orig##rmbkz: return X86::New##rmbkz;
1397
1398 switch (Opcode) {
1399 VPERM_CASES(VPERMI2B, VPERMT2B)
1400 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
1401 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1402 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1403 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
1404 VPERM_CASES(VPERMI2W, VPERMT2W)
1405 VPERM_CASES(VPERMT2B, VPERMI2B)
1406 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
1407 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1408 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1409 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
1410 VPERM_CASES(VPERMT2W, VPERMI2W)
1411 }
1412
1413 llvm_unreachable("Unreachable!");
1414 #undef VPERM_CASES_BROADCAST
1415 #undef VPERM_CASES
1416 }
1417
1418 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1419 unsigned OpIdx1,
1420 unsigned OpIdx2) const {
1421 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1422 if (NewMI)
1423 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1424 return MI;
1425 };
1426
1427 switch (MI.getOpcode()) {
1428 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1429 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1430 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1431 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1432 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1433 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1434 unsigned Opc;
1435 unsigned Size;
1436 switch (MI.getOpcode()) {
1437 default: llvm_unreachable("Unreachable!");
1438 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1439 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1440 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1441 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1442 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1443 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1444 }
1445 unsigned Amt = MI.getOperand(3).getImm();
1446 auto &WorkingMI = cloneIfNew(MI);
1447 WorkingMI.setDesc(get(Opc));
1448 WorkingMI.getOperand(3).setImm(Size - Amt);
1449 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1450 OpIdx1, OpIdx2);
1451 }
1452 case X86::PFSUBrr:
1453 case X86::PFSUBRrr: {
1454 // PFSUB x, y: x = x - y
1455 // PFSUBR x, y: x = y - x
1456 unsigned Opc =
1457 (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1458 auto &WorkingMI = cloneIfNew(MI);
1459 WorkingMI.setDesc(get(Opc));
1460 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1461 OpIdx1, OpIdx2);
1462 }
1463 case X86::BLENDPDrri:
1464 case X86::BLENDPSrri:
1465 case X86::VBLENDPDrri:
1466 case X86::VBLENDPSrri:
1467 // If we're optimizing for size, try to use MOVSD/MOVSS.
1468 if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
1469 unsigned Mask, Opc;
1470 switch (MI.getOpcode()) {
1471 default: llvm_unreachable("Unreachable!");
1472 case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break;
1473 case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break;
1474 case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1475 case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1476 }
1477 if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1478 auto &WorkingMI = cloneIfNew(MI);
1479 WorkingMI.setDesc(get(Opc));
1480 WorkingMI.RemoveOperand(3);
1481 return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1482 /*NewMI=*/false,
1483 OpIdx1, OpIdx2);
1484 }
1485 }
1486 LLVM_FALLTHROUGH;
1487 case X86::PBLENDWrri:
1488 case X86::VBLENDPDYrri:
1489 case X86::VBLENDPSYrri:
1490 case X86::VPBLENDDrri:
1491 case X86::VPBLENDWrri:
1492 case X86::VPBLENDDYrri:
1493 case X86::VPBLENDWYrri:{
1494 int8_t Mask;
1495 switch (MI.getOpcode()) {
1496 default: llvm_unreachable("Unreachable!");
1497 case X86::BLENDPDrri: Mask = (int8_t)0x03; break;
1498 case X86::BLENDPSrri: Mask = (int8_t)0x0F; break;
1499 case X86::PBLENDWrri: Mask = (int8_t)0xFF; break;
1500 case X86::VBLENDPDrri: Mask = (int8_t)0x03; break;
1501 case X86::VBLENDPSrri: Mask = (int8_t)0x0F; break;
1502 case X86::VBLENDPDYrri: Mask = (int8_t)0x0F; break;
1503 case X86::VBLENDPSYrri: Mask = (int8_t)0xFF; break;
1504 case X86::VPBLENDDrri: Mask = (int8_t)0x0F; break;
1505 case X86::VPBLENDWrri: Mask = (int8_t)0xFF; break;
1506 case X86::VPBLENDDYrri: Mask = (int8_t)0xFF; break;
1507 case X86::VPBLENDWYrri: Mask = (int8_t)0xFF; break;
1508 }
1509 // Only the least significant bits of Imm are used.
1510 // Using int8_t to ensure it will be sign extended to the int64_t that
1511 // setImm takes in order to match isel behavior.
1512 int8_t Imm = MI.getOperand(3).getImm() & Mask;
1513 auto &WorkingMI = cloneIfNew(MI);
1514 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1515 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1516 OpIdx1, OpIdx2);
1517 }
1518 case X86::INSERTPSrr:
1519 case X86::VINSERTPSrr:
1520 case X86::VINSERTPSZrr: {
1521 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1522 unsigned ZMask = Imm & 15;
1523 unsigned DstIdx = (Imm >> 4) & 3;
1524 unsigned SrcIdx = (Imm >> 6) & 3;
1525
1526 // We can commute insertps if we zero 2 of the elements, the insertion is
1527 // "inline" and we don't override the insertion with a zero.
1528 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1529 countPopulation(ZMask) == 2) {
1530 unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1531 assert(AltIdx < 4 && "Illegal insertion index");
1532 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1533 auto &WorkingMI = cloneIfNew(MI);
1534 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1535 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1536 OpIdx1, OpIdx2);
1537 }
1538 return nullptr;
1539 }
1540 case X86::MOVSDrr:
1541 case X86::MOVSSrr:
1542 case X86::VMOVSDrr:
1543 case X86::VMOVSSrr:{
1544 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1545 if (Subtarget.hasSSE41()) {
1546 unsigned Mask, Opc;
1547 switch (MI.getOpcode()) {
1548 default: llvm_unreachable("Unreachable!");
1549 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
1550 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
1551 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1552 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1553 }
1554
1555 auto &WorkingMI = cloneIfNew(MI);
1556 WorkingMI.setDesc(get(Opc));
1557 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1558 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1559 OpIdx1, OpIdx2);
1560 }
1561
1562 // Convert to SHUFPD.
1563 assert(MI.getOpcode() == X86::MOVSDrr &&
1564 "Can only commute MOVSDrr without SSE4.1");
1565
1566 auto &WorkingMI = cloneIfNew(MI);
1567 WorkingMI.setDesc(get(X86::SHUFPDrri));
1568 WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
1569 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1570 OpIdx1, OpIdx2);
1571 }
1572 case X86::SHUFPDrri: {
1573 // Commute to MOVSD.
1574 assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
1575 auto &WorkingMI = cloneIfNew(MI);
1576 WorkingMI.setDesc(get(X86::MOVSDrr));
1577 WorkingMI.RemoveOperand(3);
1578 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1579 OpIdx1, OpIdx2);
1580 }
1581 case X86::PCLMULQDQrr:
1582 case X86::VPCLMULQDQrr:
1583 case X86::VPCLMULQDQYrr:
1584 case X86::VPCLMULQDQZrr:
1585 case X86::VPCLMULQDQZ128rr:
1586 case X86::VPCLMULQDQZ256rr: {
1587 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
1588 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
1589 unsigned Imm = MI.getOperand(3).getImm();
1590 unsigned Src1Hi = Imm & 0x01;
1591 unsigned Src2Hi = Imm & 0x10;
1592 auto &WorkingMI = cloneIfNew(MI);
1593 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1594 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1595 OpIdx1, OpIdx2);
1596 }
1597 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
1598 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
1599 case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
1600 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
1601 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
1602 case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
1603 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
1604 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
1605 case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
1606 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
1607 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
1608 case X86::VPCMPWZrri: case X86::VPCMPUWZrri:
1609 case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
1610 case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
1611 case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik:
1612 case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
1613 case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
1614 case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik:
1615 case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
1616 case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
1617 case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik:
1618 case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
1619 case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
1620 case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: {
1621 // Flip comparison mode immediate (if necessary).
1622 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1623 Imm = X86::getSwappedVPCMPImm(Imm);
1624 auto &WorkingMI = cloneIfNew(MI);
1625 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1626 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1627 OpIdx1, OpIdx2);
1628 }
1629 case X86::VPCOMBri: case X86::VPCOMUBri:
1630 case X86::VPCOMDri: case X86::VPCOMUDri:
1631 case X86::VPCOMQri: case X86::VPCOMUQri:
1632 case X86::VPCOMWri: case X86::VPCOMUWri: {
1633 // Flip comparison mode immediate (if necessary).
1634 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1635 Imm = X86::getSwappedVPCOMImm(Imm);
1636 auto &WorkingMI = cloneIfNew(MI);
1637 WorkingMI.getOperand(3).setImm(Imm);
1638 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1639 OpIdx1, OpIdx2);
1640 }
1641 case X86::VPERM2F128rr:
1642 case X86::VPERM2I128rr: {
1643 // Flip permute source immediate.
1644 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
1645 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
1646 int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
1647 auto &WorkingMI = cloneIfNew(MI);
1648 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1649 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1650 OpIdx1, OpIdx2);
1651 }
1652 case X86::MOVHLPSrr:
1653 case X86::UNPCKHPDrr:
1654 case X86::VMOVHLPSrr:
1655 case X86::VUNPCKHPDrr:
1656 case X86::VMOVHLPSZrr:
1657 case X86::VUNPCKHPDZ128rr: {
1658 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
1659
1660 unsigned Opc = MI.getOpcode();
1661 switch (Opc) {
1662 default: llvm_unreachable("Unreachable!");
1663 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
1664 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
1665 case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break;
1666 case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break;
1667 case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break;
1668 case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break;
1669 }
1670 auto &WorkingMI = cloneIfNew(MI);
1671 WorkingMI.setDesc(get(Opc));
1672 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1673 OpIdx1, OpIdx2);
1674 }
1675 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr: {
1676 auto &WorkingMI = cloneIfNew(MI);
1677 unsigned OpNo = MI.getDesc().getNumOperands() - 1;
1678 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
1679 WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
1680 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1681 OpIdx1, OpIdx2);
1682 }
1683 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1684 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1685 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1686 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1687 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1688 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1689 case X86::VPTERNLOGDZrrik:
1690 case X86::VPTERNLOGDZ128rrik:
1691 case X86::VPTERNLOGDZ256rrik:
1692 case X86::VPTERNLOGQZrrik:
1693 case X86::VPTERNLOGQZ128rrik:
1694 case X86::VPTERNLOGQZ256rrik:
1695 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1696 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1697 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1698 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1699 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1700 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1701 case X86::VPTERNLOGDZ128rmbi:
1702 case X86::VPTERNLOGDZ256rmbi:
1703 case X86::VPTERNLOGDZrmbi:
1704 case X86::VPTERNLOGQZ128rmbi:
1705 case X86::VPTERNLOGQZ256rmbi:
1706 case X86::VPTERNLOGQZrmbi:
1707 case X86::VPTERNLOGDZ128rmbikz:
1708 case X86::VPTERNLOGDZ256rmbikz:
1709 case X86::VPTERNLOGDZrmbikz:
1710 case X86::VPTERNLOGQZ128rmbikz:
1711 case X86::VPTERNLOGQZ256rmbikz:
1712 case X86::VPTERNLOGQZrmbikz: {
1713 auto &WorkingMI = cloneIfNew(MI);
1714 commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
1715 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1716 OpIdx1, OpIdx2);
1717 }
1718 default: {
1719 if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
1720 unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
1721 auto &WorkingMI = cloneIfNew(MI);
1722 WorkingMI.setDesc(get(Opc));
1723 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1724 OpIdx1, OpIdx2);
1725 }
1726
1727 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1728 MI.getDesc().TSFlags);
1729 if (FMA3Group) {
1730 unsigned Opc =
1731 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
1732 auto &WorkingMI = cloneIfNew(MI);
1733 WorkingMI.setDesc(get(Opc));
1734 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1735 OpIdx1, OpIdx2);
1736 }
1737
1738 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1739 }
1740 }
1741 }
1742
1743 bool
1744 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
1745 unsigned &SrcOpIdx1,
1746 unsigned &SrcOpIdx2,
1747 bool IsIntrinsic) const {
1748 uint64_t TSFlags = MI.getDesc().TSFlags;
1749
1750 unsigned FirstCommutableVecOp = 1;
1751 unsigned LastCommutableVecOp = 3;
1752 unsigned KMaskOp = -1U;
1753 if (X86II::isKMasked(TSFlags)) {
1754 // For k-zero-masked operations it is Ok to commute the first vector
1755 // operand.
1756 // For regular k-masked operations a conservative choice is done as the
1757 // elements of the first vector operand, for which the corresponding bit
1758 // in the k-mask operand is set to 0, are copied to the result of the
1759 // instruction.
1760 // TODO/FIXME: The commute still may be legal if it is known that the
1761 // k-mask operand is set to either all ones or all zeroes.
1762 // It is also Ok to commute the 1st operand if all users of MI use only
1763 // the elements enabled by the k-mask operand. For example,
1764 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
1765 // : v1[i];
1766 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
1767 // // Ok, to commute v1 in FMADD213PSZrk.
1768
1769 // The k-mask operand has index = 2 for masked and zero-masked operations.
1770 KMaskOp = 2;
1771
1772 // The operand with index = 1 is used as a source for those elements for
1773 // which the corresponding bit in the k-mask is set to 0.
1774 if (X86II::isKMergeMasked(TSFlags))
1775 FirstCommutableVecOp = 3;
1776
1777 LastCommutableVecOp++;
1778 } else if (IsIntrinsic) {
1779 // Commuting the first operand of an intrinsic instruction isn't possible
1780 // unless we can prove that only the lowest element of the result is used.
1781 FirstCommutableVecOp = 2;
1782 }
1783
1784 if (isMem(MI, LastCommutableVecOp))
1785 LastCommutableVecOp--;
1786
1787 // Only the first RegOpsNum operands are commutable.
1788 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
1789 // that the operand is not specified/fixed.
1790 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1791 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
1792 SrcOpIdx1 == KMaskOp))
1793 return false;
1794 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
1795 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
1796 SrcOpIdx2 == KMaskOp))
1797 return false;
1798
1799 // Look for two different register operands assumed to be commutable
1800 // regardless of the FMA opcode. The FMA opcode is adjusted later.
1801 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1802 SrcOpIdx2 == CommuteAnyOperandIndex) {
1803 unsigned CommutableOpIdx2 = SrcOpIdx2;
1804
1805 // At least one of operands to be commuted is not specified and
1806 // this method is free to choose appropriate commutable operands.
1807 if (SrcOpIdx1 == SrcOpIdx2)
1808 // Both of operands are not fixed. By default set one of commutable
1809 // operands to the last register operand of the instruction.
1810 CommutableOpIdx2 = LastCommutableVecOp;
1811 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
1812 // Only one of operands is not fixed.
1813 CommutableOpIdx2 = SrcOpIdx1;
1814
1815 // CommutableOpIdx2 is well defined now. Let's choose another commutable
1816 // operand and assign its index to CommutableOpIdx1.
1817 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1818
1819 unsigned CommutableOpIdx1;
1820 for (CommutableOpIdx1 = LastCommutableVecOp;
1821 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
1822 // Just ignore and skip the k-mask operand.
1823 if (CommutableOpIdx1 == KMaskOp)
1824 continue;
1825
1826 // The commuted operands must have different registers.
1827 // Otherwise, the commute transformation does not change anything and
1828 // is useless then.
1829 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
1830 break;
1831 }
1832
1833 // No appropriate commutable operands were found.
1834 if (CommutableOpIdx1 < FirstCommutableVecOp)
1835 return false;
1836
1837 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
1838 // to return those values.
1839 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1840 CommutableOpIdx1, CommutableOpIdx2))
1841 return false;
1842 }
1843
1844 return true;
1845 }
1846
1847 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
1848 unsigned &SrcOpIdx2) const {
1849 const MCInstrDesc &Desc = MI.getDesc();
1850 if (!Desc.isCommutable())
1851 return false;
1852
1853 switch (MI.getOpcode()) {
1854 case X86::CMPSDrr:
1855 case X86::CMPSSrr:
1856 case X86::CMPPDrri:
1857 case X86::CMPPSrri:
1858 case X86::VCMPSDrr:
1859 case X86::VCMPSSrr:
1860 case X86::VCMPPDrri:
1861 case X86::VCMPPSrri:
1862 case X86::VCMPPDYrri:
1863 case X86::VCMPPSYrri:
1864 case X86::VCMPSDZrr:
1865 case X86::VCMPSSZrr:
1866 case X86::VCMPPDZrri:
1867 case X86::VCMPPSZrri:
1868 case X86::VCMPPDZ128rri:
1869 case X86::VCMPPSZ128rri:
1870 case X86::VCMPPDZ256rri:
1871 case X86::VCMPPSZ256rri:
1872 case X86::VCMPPDZrrik:
1873 case X86::VCMPPSZrrik:
1874 case X86::VCMPPDZ128rrik:
1875 case X86::VCMPPSZ128rrik:
1876 case X86::VCMPPDZ256rrik:
1877 case X86::VCMPPSZ256rrik: {
1878 unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
1879
1880 // Float comparison can be safely commuted for
1881 // Ordered/Unordered/Equal/NotEqual tests
1882 unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
1883 switch (Imm) {
1884 case 0x00: // EQUAL
1885 case 0x03: // UNORDERED
1886 case 0x04: // NOT EQUAL
1887 case 0x07: // ORDERED
1888 // The indices of the commutable operands are 1 and 2 (or 2 and 3
1889 // when masked).
1890 // Assign them to the returned operand indices here.
1891 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
1892 2 + OpOffset);
1893 }
1894 return false;
1895 }
1896 case X86::MOVSSrr:
1897 // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
1898 // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
1899 // AVX implies sse4.1.
1900 if (Subtarget.hasSSE41())
1901 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1902 return false;
1903 case X86::SHUFPDrri:
1904 // We can commute this to MOVSD.
1905 if (MI.getOperand(3).getImm() == 0x02)
1906 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1907 return false;
1908 case X86::MOVHLPSrr:
1909 case X86::UNPCKHPDrr:
1910 case X86::VMOVHLPSrr:
1911 case X86::VUNPCKHPDrr:
1912 case X86::VMOVHLPSZrr:
1913 case X86::VUNPCKHPDZ128rr:
1914 if (Subtarget.hasSSE2())
1915 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1916 return false;
1917 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1918 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1919 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1920 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1921 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1922 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1923 case X86::VPTERNLOGDZrrik:
1924 case X86::VPTERNLOGDZ128rrik:
1925 case X86::VPTERNLOGDZ256rrik:
1926 case X86::VPTERNLOGQZrrik:
1927 case X86::VPTERNLOGQZ128rrik:
1928 case X86::VPTERNLOGQZ256rrik:
1929 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1930 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1931 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1932 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1933 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1934 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1935 case X86::VPTERNLOGDZ128rmbi:
1936 case X86::VPTERNLOGDZ256rmbi:
1937 case X86::VPTERNLOGDZrmbi:
1938 case X86::VPTERNLOGQZ128rmbi:
1939 case X86::VPTERNLOGQZ256rmbi:
1940 case X86::VPTERNLOGQZrmbi:
1941 case X86::VPTERNLOGDZ128rmbikz:
1942 case X86::VPTERNLOGDZ256rmbikz:
1943 case X86::VPTERNLOGDZrmbikz:
1944 case X86::VPTERNLOGQZ128rmbikz:
1945 case X86::VPTERNLOGQZ256rmbikz:
1946 case X86::VPTERNLOGQZrmbikz:
1947 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1948 case X86::VPMADD52HUQZ128r:
1949 case X86::VPMADD52HUQZ128rk:
1950 case X86::VPMADD52HUQZ128rkz:
1951 case X86::VPMADD52HUQZ256r:
1952 case X86::VPMADD52HUQZ256rk:
1953 case X86::VPMADD52HUQZ256rkz:
1954 case X86::VPMADD52HUQZr:
1955 case X86::VPMADD52HUQZrk:
1956 case X86::VPMADD52HUQZrkz:
1957 case X86::VPMADD52LUQZ128r:
1958 case X86::VPMADD52LUQZ128rk:
1959 case X86::VPMADD52LUQZ128rkz:
1960 case X86::VPMADD52LUQZ256r:
1961 case X86::VPMADD52LUQZ256rk:
1962 case X86::VPMADD52LUQZ256rkz:
1963 case X86::VPMADD52LUQZr:
1964 case X86::VPMADD52LUQZrk:
1965 case X86::VPMADD52LUQZrkz: {
1966 unsigned CommutableOpIdx1 = 2;
1967 unsigned CommutableOpIdx2 = 3;
1968 if (X86II::isKMasked(Desc.TSFlags)) {
1969 // Skip the mask register.
1970 ++CommutableOpIdx1;
1971 ++CommutableOpIdx2;
1972 }
1973 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1974 CommutableOpIdx1, CommutableOpIdx2))
1975 return false;
1976 if (!MI.getOperand(SrcOpIdx1).isReg() ||
1977 !MI.getOperand(SrcOpIdx2).isReg())
1978 // No idea.
1979 return false;
1980 return true;
1981 }
1982
1983 default:
1984 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1985 MI.getDesc().TSFlags);
1986 if (FMA3Group)
1987 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
1988 FMA3Group->isIntrinsic());
1989
1990 // Handled masked instructions since we need to skip over the mask input
1991 // and the preserved input.
1992 if (X86II::isKMasked(Desc.TSFlags)) {
1993 // First assume that the first input is the mask operand and skip past it.
1994 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
1995 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
1996 // Check if the first input is tied. If there isn't one then we only
1997 // need to skip the mask operand which we did above.
1998 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
1999 MCOI::TIED_TO) != -1)) {
2000 // If this is zero masking instruction with a tied operand, we need to
2001 // move the first index back to the first input since this must
2002 // be a 3 input instruction and we want the first two non-mask inputs.
2003 // Otherwise this is a 2 input instruction with a preserved input and
2004 // mask, so we need to move the indices to skip one more input.
2005 if (X86II::isKMergeMasked(Desc.TSFlags)) {
2006 ++CommutableOpIdx1;
2007 ++CommutableOpIdx2;
2008 } else {
2009 --CommutableOpIdx1;
2010 }
2011 }
2012
2013 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2014 CommutableOpIdx1, CommutableOpIdx2))
2015 return false;
2016
2017 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2018 !MI.getOperand(SrcOpIdx2).isReg())
2019 // No idea.
2020 return false;
2021 return true;
2022 }
2023
2024 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2025 }
2026 return false;
2027 }
2028
2029 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2030 switch (MI.getOpcode()) {
2031 default: return X86::COND_INVALID;
2032 case X86::JCC_1:
2033 return static_cast<X86::CondCode>(
2034 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2035 }
2036 }
2037
2038 /// Return condition code of a SETCC opcode.
2039 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2040 switch (MI.getOpcode()) {
2041 default: return X86::COND_INVALID;
2042 case X86::SETCCr: case X86::SETCCm:
2043 return static_cast<X86::CondCode>(
2044 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2045 }
2046 }
2047
2048 /// Return condition code of a CMov opcode.
2049 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2050 switch (MI.getOpcode()) {
2051 default: return X86::COND_INVALID;
2052 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2053 case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2054 return static_cast<X86::CondCode>(
2055 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2056 }
2057 }
2058
2059 /// Return the inverse of the specified condition,
2060 /// e.g. turning COND_E to COND_NE.
2061 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2062 switch (CC) {
2063 default: llvm_unreachable("Illegal condition code!");
2064 case X86::COND_E: return X86::COND_NE;
2065 case X86::COND_NE: return X86::COND_E;
2066 case X86::COND_L: return X86::COND_GE;
2067 case X86::COND_LE: return X86::COND_G;
2068 case X86::COND_G: return X86::COND_LE;
2069 case X86::COND_GE: return X86::COND_L;
2070 case X86::COND_B: return X86::COND_AE;
2071 case X86::COND_BE: return X86::COND_A;
2072 case X86::COND_A: return X86::COND_BE;
2073 case X86::COND_AE: return X86::COND_B;
2074 case X86::COND_S: return X86::COND_NS;
2075 case X86::COND_NS: return X86::COND_S;
2076 case X86::COND_P: return X86::COND_NP;
2077 case X86::COND_NP: return X86::COND_P;
2078 case X86::COND_O: return X86::COND_NO;
2079 case X86::COND_NO: return X86::COND_O;
2080 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
2081 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2082 }
2083 }
2084
2085 /// Assuming the flags are set by MI(a,b), return the condition code if we
2086 /// modify the instructions such that flags are set by MI(b,a).
2087 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2088 switch (CC) {
2089 default: return X86::COND_INVALID;
2090 case X86::COND_E: return X86::COND_E;
2091 case X86::COND_NE: return X86::COND_NE;
2092 case X86::COND_L: return X86::COND_G;
2093 case X86::COND_LE: return X86::COND_GE;
2094 case X86::COND_G: return X86::COND_L;
2095 case X86::COND_GE: return X86::COND_LE;
2096 case X86::COND_B: return X86::COND_A;
2097 case X86::COND_BE: return X86::COND_AE;
2098 case X86::COND_A: return X86::COND_B;
2099 case X86::COND_AE: return X86::COND_BE;
2100 }
2101 }
2102
2103 std::pair<X86::CondCode, bool>
2104 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2105 X86::CondCode CC = X86::COND_INVALID;
2106 bool NeedSwap = false;
2107 switch (Predicate) {
2108 default: break;
2109 // Floating-point Predicates
2110 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
2111 case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH;
2112 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
2113 case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH;
2114 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
2115 case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH;
2116 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
2117 case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH;
2118 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
2119 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
2120 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
2121 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
2122 case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH;
2123 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2124
2125 // Integer Predicates
2126 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
2127 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
2128 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
2129 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
2130 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
2131 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
2132 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
2133 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
2134 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
2135 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
2136 }
2137
2138 return std::make_pair(CC, NeedSwap);
2139 }
2140
2141 /// Return a setcc opcode based on whether it has memory operand.
2142 unsigned X86::getSETOpc(bool HasMemoryOperand) {
2143 return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2144 }
2145
2146 /// Return a cmov opcode for the given register size in bytes, and operand type.
2147 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2148 switch(RegBytes) {
2149 default: llvm_unreachable("Illegal register size!");
2150 case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2151 case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2152 case 8: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV64rr;
2153 }
2154 }
2155
2156 /// Get the VPCMP immediate for the given condition.
2157 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2158 switch (CC) {
2159 default: llvm_unreachable("Unexpected SETCC condition");
2160 case ISD::SETNE: return 4;
2161 case ISD::SETEQ: return 0;
2162 case ISD::SETULT:
2163 case ISD::SETLT: return 1;
2164 case ISD::SETUGT:
2165 case ISD::SETGT: return 6;
2166 case ISD::SETUGE:
2167 case ISD::SETGE: return 5;
2168 case ISD::SETULE:
2169 case ISD::SETLE: return 2;
2170 }
2171 }
2172
2173 /// Get the VPCMP immediate if the opcodes are swapped.
2174 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2175 switch (Imm) {
2176 default: llvm_unreachable("Unreachable!");
2177 case 0x01: Imm = 0x06; break; // LT -> NLE
2178 case 0x02: Imm = 0x05; break; // LE -> NLT
2179 case 0x05: Imm = 0x02; break; // NLT -> LE
2180 case 0x06: Imm = 0x01; break; // NLE -> LT
2181 case 0x00: // EQ
2182 case 0x03: // FALSE
2183 case 0x04: // NE
2184 case 0x07: // TRUE
2185 break;
2186 }
2187
2188 return Imm;
2189 }
2190
2191 /// Get the VPCOM immediate if the opcodes are swapped.
2192 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2193 switch (Imm) {
2194 default: llvm_unreachable("Unreachable!");
2195 case 0x00: Imm = 0x02; break; // LT -> GT
2196 case 0x01: Imm = 0x03; break; // LE -> GE
2197 case 0x02: Imm = 0x00; break; // GT -> LT
2198 case 0x03: Imm = 0x01; break; // GE -> LE
2199 case 0x04: // EQ
2200 case 0x05: // NE
2201 case 0x06: // FALSE
2202 case 0x07: // TRUE
2203 break;
2204 }
2205
2206 return Imm;
2207 }
2208
2209 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
2210 if (!MI.isTerminator()) return false;
2211
2212 // Conditional branch is a special case.
2213 if (MI.isBranch() && !MI.isBarrier())
2214 return true;
2215 if (!MI.isPredicable())
2216 return true;
2217 return !isPredicated(MI);
2218 }
2219
2220 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2221 switch (MI.getOpcode()) {
2222 case X86::TCRETURNdi:
2223 case X86::TCRETURNri:
2224 case X86::TCRETURNmi:
2225 case X86::TCRETURNdi64:
2226 case X86::TCRETURNri64:
2227 case X86::TCRETURNmi64:
2228 return true;
2229 default:
2230 return false;
2231 }
2232 }
2233
2234 bool X86InstrInfo::canMakeTailCallConditional(
2235 SmallVectorImpl<MachineOperand> &BranchCond,
2236 const MachineInstr &TailCall) const {
2237 if (TailCall.getOpcode() != X86::TCRETURNdi &&
2238 TailCall.getOpcode() != X86::TCRETURNdi64) {
2239 // Only direct calls can be done with a conditional branch.
2240 return false;
2241 }
2242
2243 const MachineFunction *MF = TailCall.getParent()->getParent();
2244 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2245 // Conditional tail calls confuse the Win64 unwinder.
2246 return false;
2247 }
2248
2249 assert(BranchCond.size() == 1);
2250 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2251 // Can't make a conditional tail call with this condition.
2252 return false;
2253 }
2254
2255 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2256 if (X86FI->getTCReturnAddrDelta() != 0 ||
2257 TailCall.getOperand(1).getImm() != 0) {
2258 // A conditional tail call cannot do any stack adjustment.
2259 return false;
2260 }
2261
2262 return true;
2263 }
2264
2265 void X86InstrInfo::replaceBranchWithTailCall(
2266 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2267 const MachineInstr &TailCall) const {
2268 assert(canMakeTailCallConditional(BranchCond, TailCall));
2269
2270 MachineBasicBlock::iterator I = MBB.end();
2271 while (I != MBB.begin()) {
2272 --I;
2273 if (I->isDebugInstr())
2274 continue;
2275 if (!I->isBranch())
2276 assert(0 && "Can't find the branch to replace!");
2277
2278 X86::CondCode CC = X86::getCondFromBranch(*I);
2279 assert(BranchCond.size() == 1);
2280 if (CC != BranchCond[0].getImm())
2281 continue;
2282
2283 break;
2284 }
2285
2286 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2287 : X86::TCRETURNdi64cc;
2288
2289 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2290 MIB->addOperand(TailCall.getOperand(0)); // Destination.
2291 MIB.addImm(0); // Stack offset (not used).
2292 MIB->addOperand(BranchCond[0]); // Condition.
2293 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2294
2295 // Add implicit uses and defs of all live regs potentially clobbered by the
2296 // call. This way they still appear live across the call.
2297 LivePhysRegs LiveRegs(getRegisterInfo());
2298 LiveRegs.addLiveOuts(MBB);
2299 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2300 LiveRegs.stepForward(*MIB, Clobbers);
2301 for (const auto &C : Clobbers) {
2302 MIB.addReg(C.first, RegState::Implicit);
2303 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2304 }
2305
2306 I->eraseFromParent();
2307 }
2308
2309 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2310 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2311 // fallthrough MBB cannot be identified.
2312 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2313 MachineBasicBlock *TBB) {
2314 // Look for non-EHPad successors other than TBB. If we find exactly one, it
2315 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2316 // and fallthrough MBB. If we find more than one, we cannot identify the
2317 // fallthrough MBB and should return nullptr.
2318 MachineBasicBlock *FallthroughBB = nullptr;
2319 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2320 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2321 continue;
2322 // Return a nullptr if we found more than one fallthrough successor.
2323 if (FallthroughBB && FallthroughBB != TBB)
2324 return nullptr;
2325 FallthroughBB = *SI;
2326 }
2327 return FallthroughBB;
2328 }
2329
2330 bool X86InstrInfo::AnalyzeBranchImpl(
2331 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2332 SmallVectorImpl<MachineOperand> &Cond,
2333 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2334
2335 // Start from the bottom of the block and work up, examining the
2336 // terminator instructions.
2337 MachineBasicBlock::iterator I = MBB.end();
2338 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2339 while (I != MBB.begin()) {
2340 --I;
2341 if (I->isDebugInstr())
2342 continue;
2343
2344 // Working from the bottom, when we see a non-terminator instruction, we're
2345 // done.
2346 if (!isUnpredicatedTerminator(*I))
2347 break;
2348
2349 // A terminator that isn't a branch can't easily be handled by this
2350 // analysis.
2351 if (!I->isBranch())
2352 return true;
2353
2354 // Handle unconditional branches.
2355 if (I->getOpcode() == X86::JMP_1) {
2356 UnCondBrIter = I;
2357
2358 if (!AllowModify) {
2359 TBB = I->getOperand(0).getMBB();
2360 continue;
2361 }
2362
2363 // If the block has any instructions after a JMP, delete them.
2364 while (std::next(I) != MBB.end())
2365 std::next(I)->eraseFromParent();
2366
2367 Cond.clear();
2368 FBB = nullptr;
2369
2370 // Delete the JMP if it's equivalent to a fall-through.
2371 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2372 TBB = nullptr;
2373 I->eraseFromParent();
2374 I = MBB.end();
2375 UnCondBrIter = MBB.end();
2376 continue;
2377 }
2378
2379 // TBB is used to indicate the unconditional destination.
2380 TBB = I->getOperand(0).getMBB();
2381 continue;
2382 }
2383
2384 // Handle conditional branches.
2385 X86::CondCode BranchCode = X86::getCondFromBranch(*I);
2386 if (BranchCode == X86::COND_INVALID)
2387 return true; // Can't handle indirect branch.
2388
2389 // In practice we should never have an undef eflags operand, if we do
2390 // abort here as we are not prepared to preserve the flag.
2391 if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
2392 return true;
2393
2394 // Working from the bottom, handle the first conditional branch.
2395 if (Cond.empty()) {
2396 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2397 if (AllowModify && UnCondBrIter != MBB.end() &&
2398 MBB.isLayoutSuccessor(TargetBB)) {
2399 // If we can modify the code and it ends in something like:
2400 //
2401 // jCC L1
2402 // jmp L2
2403 // L1:
2404 // ...
2405 // L2:
2406 //
2407 // Then we can change this to:
2408 //
2409 // jnCC L2
2410 // L1:
2411 // ...
2412 // L2:
2413 //
2414 // Which is a bit more efficient.
2415 // We conditionally jump to the fall-through block.
2416 BranchCode = GetOppositeBranchCondition(BranchCode);
2417 MachineBasicBlock::iterator OldInst = I;
2418
2419 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2420 .addMBB(UnCondBrIter->getOperand(0).getMBB())
2421 .addImm(BranchCode);
2422 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2423 .addMBB(TargetBB);
2424
2425 OldInst->eraseFromParent();
2426 UnCondBrIter->eraseFromParent();
2427
2428 // Restart the analysis.
2429 UnCondBrIter = MBB.end();
2430 I = MBB.end();
2431 continue;
2432 }
2433
2434 FBB = TBB;
2435 TBB = I->getOperand(0).getMBB();
2436 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2437 CondBranches.push_back(&*I);
2438 continue;
2439 }
2440
2441 // Handle subsequent conditional branches. Only handle the case where all
2442 // conditional branches branch to the same destination and their condition
2443 // opcodes fit one of the special multi-branch idioms.
2444 assert(Cond.size() == 1);
2445 assert(TBB);
2446
2447 // If the conditions are the same, we can leave them alone.
2448 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2449 auto NewTBB = I->getOperand(0).getMBB();
2450 if (OldBranchCode == BranchCode && TBB == NewTBB)
2451 continue;
2452
2453 // If they differ, see if they fit one of the known patterns. Theoretically,
2454 // we could handle more patterns here, but we shouldn't expect to see them
2455 // if instruction selection has done a reasonable job.
2456 if (TBB == NewTBB &&
2457 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
2458 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
2459 BranchCode = X86::COND_NE_OR_P;
2460 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
2461 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
2462 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
2463 return true;
2464
2465 // X86::COND_E_AND_NP usually has two different branch destinations.
2466 //
2467 // JP B1
2468 // JE B2
2469 // JMP B1
2470 // B1:
2471 // B2:
2472 //
2473 // Here this condition branches to B2 only if NP && E. It has another
2474 // equivalent form:
2475 //
2476 // JNE B1
2477 // JNP B2
2478 // JMP B1
2479 // B1:
2480 // B2:
2481 //
2482 // Similarly it branches to B2 only if E && NP. That is why this condition
2483 // is named with COND_E_AND_NP.
2484 BranchCode = X86::COND_E_AND_NP;
2485 } else
2486 return true;
2487
2488 // Update the MachineOperand.
2489 Cond[0].setImm(BranchCode);
2490 CondBranches.push_back(&*I);
2491 }
2492
2493 return false;
2494 }
2495
2496 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
2497 MachineBasicBlock *&TBB,
2498 MachineBasicBlock *&FBB,
2499 SmallVectorImpl<MachineOperand> &Cond,
2500 bool AllowModify) const {
2501 SmallVector<MachineInstr *, 4> CondBranches;
2502 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
2503 }
2504
2505 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
2506 MachineBranchPredicate &MBP,
2507 bool AllowModify) const {
2508 using namespace std::placeholders;
2509
2510 SmallVector<MachineOperand, 4> Cond;
2511 SmallVector<MachineInstr *, 4> CondBranches;
2512 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
2513 AllowModify))
2514 return true;
2515
2516 if (Cond.size() != 1)
2517 return true;
2518
2519 assert(MBP.TrueDest && "expected!");
2520
2521 if (!MBP.FalseDest)
2522 MBP.FalseDest = MBB.getNextNode();
2523
2524 const TargetRegisterInfo *TRI = &getRegisterInfo();
2525
2526 MachineInstr *ConditionDef = nullptr;
2527 bool SingleUseCondition = true;
2528
2529 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
2530 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2531 ConditionDef = &*I;
2532 break;
2533 }
2534
2535 if (I->readsRegister(X86::EFLAGS, TRI))
2536 SingleUseCondition = false;
2537 }
2538
2539 if (!ConditionDef)
2540 return true;
2541
2542 if (SingleUseCondition) {
2543 for (auto *Succ : MBB.successors())
2544 if (Succ->isLiveIn(X86::EFLAGS))
2545 SingleUseCondition = false;
2546 }
2547
2548 MBP.ConditionDef = ConditionDef;
2549 MBP.SingleUseCondition = SingleUseCondition;
2550
2551 // Currently we only recognize the simple pattern:
2552 //
2553 // test %reg, %reg
2554 // je %label
2555 //
2556 const unsigned TestOpcode =
2557 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
2558
2559 if (ConditionDef->getOpcode() == TestOpcode &&
2560 ConditionDef->getNumOperands() == 3 &&
2561 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2562 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
2563 MBP.LHS = ConditionDef->getOperand(0);
2564 MBP.RHS = MachineOperand::CreateImm(0);
2565 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
2566 ? MachineBranchPredicate::PRED_NE
2567 : MachineBranchPredicate::PRED_EQ;
2568 return false;
2569 }
2570
2571 return true;
2572 }
2573
2574 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
2575 int *BytesRemoved) const {
2576 assert(!BytesRemoved && "code size not handled");
2577
2578 MachineBasicBlock::iterator I = MBB.end();
2579 unsigned Count = 0;
2580
2581 while (I != MBB.begin()) {
2582 --I;
2583 if (I->isDebugInstr())
2584 continue;
2585 if (I->getOpcode() != X86::JMP_1 &&
2586 X86::getCondFromBranch(*I) == X86::COND_INVALID)
2587 break;
2588 // Remove the branch.
2589 I->eraseFromParent();
2590 I = MBB.end();
2591 ++Count;
2592 }
2593
2594 return Count;
2595 }
2596
2597 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
2598 MachineBasicBlock *TBB,
2599 MachineBasicBlock *FBB,
2600 ArrayRef<MachineOperand> Cond,
2601 const DebugLoc &DL,
2602 int *BytesAdded) const {
2603 // Shouldn't be a fall through.
2604 assert(TBB && "insertBranch must not be told to insert a fallthrough");
2605 assert((Cond.size() == 1 || Cond.size() == 0) &&
2606 "X86 branch conditions have one component!");
2607 assert(!BytesAdded && "code size not handled");
2608
2609 if (Cond.empty()) {
2610 // Unconditional branch?
2611 assert(!FBB && "Unconditional branch with multiple successors!");
2612 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2613 return 1;
2614 }
2615
2616 // If FBB is null, it is implied to be a fall-through block.
2617 bool FallThru = FBB == nullptr;
2618
2619 // Conditional branch.
2620 unsigned Count = 0;
2621 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2622 switch (CC) {
2623 case X86::COND_NE_OR_P:
2624 // Synthesize NE_OR_P with two branches.
2625 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
2626 ++Count;
2627 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
2628 ++Count;
2629 break;
2630 case X86::COND_E_AND_NP:
2631 // Use the next block of MBB as FBB if it is null.
2632 if (FBB == nullptr) {
2633 FBB = getFallThroughMBB(&MBB, TBB);
2634 assert(FBB && "MBB cannot be the last block in function when the false "
2635 "body is a fall-through.");
2636 }
2637 // Synthesize COND_E_AND_NP with two branches.
2638 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
2639 ++Count;
2640 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
2641 ++Count;
2642 break;
2643 default: {
2644 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
2645 ++Count;
2646 }
2647 }
2648 if (!FallThru) {
2649 // Two-way Conditional branch. Insert the second branch.
2650 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2651 ++Count;
2652 }
2653 return Count;
2654 }
2655
2656 bool X86InstrInfo::
2657 canInsertSelect(const MachineBasicBlock &MBB,
2658 ArrayRef<MachineOperand> Cond,
2659 unsigned TrueReg, unsigned FalseReg,
2660 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2661 // Not all subtargets have cmov instructions.
2662 if (!Subtarget.hasCMov())
2663 return false;
2664 if (Cond.size() != 1)
2665 return false;
2666 // We cannot do the composite conditions, at least not in SSA form.
2667 if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
2668 return false;
2669
2670 // Check register classes.
2671 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2672 const TargetRegisterClass *RC =
2673 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2674 if (!RC)
2675 return false;
2676
2677 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2678 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2679 X86::GR32RegClass.hasSubClassEq(RC) ||
2680 X86::GR64RegClass.hasSubClassEq(RC)) {
2681 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2682 // Bridge. Probably Ivy Bridge as well.
2683 CondCycles = 2;
2684 TrueCycles = 2;
2685 FalseCycles = 2;
2686 return true;
2687 }
2688
2689 // Can't do vectors.
2690 return false;
2691 }
2692
2693 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2694 MachineBasicBlock::iterator I,
2695 const DebugLoc &DL, unsigned DstReg,
2696 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2697 unsigned FalseReg) const {
2698 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2699 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
2700 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
2701 assert(Cond.size() == 1 && "Invalid Cond array");
2702 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
2703 false /*HasMemoryOperand*/);
2704 BuildMI(MBB, I, DL, get(Opc), DstReg)
2705 .addReg(FalseReg)
2706 .addReg(TrueReg)
2707 .addImm(Cond[0].getImm());
2708 }
2709
2710 /// Test if the given register is a physical h register.
2711 static bool isHReg(unsigned Reg) {
2712 return X86::GR8_ABCD_HRegClass.contains(Reg);
2713 }
2714
2715 // Try and copy between VR128/VR64 and GR64 registers.
2716 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2717 const X86Subtarget &Subtarget) {
2718 bool HasAVX = Subtarget.hasAVX();
2719 bool HasAVX512 = Subtarget.hasAVX512();
2720
2721 // SrcReg(MaskReg) -> DestReg(GR64)
2722 // SrcReg(MaskReg) -> DestReg(GR32)
2723
2724 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2725 if (X86::VK16RegClass.contains(SrcReg)) {
2726 if (X86::GR64RegClass.contains(DestReg)) {
2727 assert(Subtarget.hasBWI());
2728 return X86::KMOVQrk;
2729 }
2730 if (X86::GR32RegClass.contains(DestReg))
2731 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
2732 }
2733
2734 // SrcReg(GR64) -> DestReg(MaskReg)
2735 // SrcReg(GR32) -> DestReg(MaskReg)
2736
2737 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2738 if (X86::VK16RegClass.contains(DestReg)) {
2739 if (X86::GR64RegClass.contains(SrcReg)) {
2740 assert(Subtarget.hasBWI());
2741 return X86::KMOVQkr;
2742 }
2743 if (X86::GR32RegClass.contains(SrcReg))
2744 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
2745 }
2746
2747
2748 // SrcReg(VR128) -> DestReg(GR64)
2749 // SrcReg(VR64) -> DestReg(GR64)
2750 // SrcReg(GR64) -> DestReg(VR128)
2751 // SrcReg(GR64) -> DestReg(VR64)
2752
2753 if (X86::GR64RegClass.contains(DestReg)) {
2754 if (X86::VR128XRegClass.contains(SrcReg))
2755 // Copy from a VR128 register to a GR64 register.
2756 return HasAVX512 ? X86::VMOVPQIto64Zrr :
2757 HasAVX ? X86::VMOVPQIto64rr :
2758 X86::MOVPQIto64rr;
2759 if (X86::VR64RegClass.contains(SrcReg))
2760 // Copy from a VR64 register to a GR64 register.
2761 return X86::MMX_MOVD64from64rr;
2762 } else if (X86::GR64RegClass.contains(SrcReg)) {
2763 // Copy from a GR64 register to a VR128 register.
2764 if (X86::VR128XRegClass.contains(DestReg))
2765 return HasAVX512 ? X86::VMOV64toPQIZrr :
2766 HasAVX ? X86::VMOV64toPQIrr :
2767 X86::MOV64toPQIrr;
2768 // Copy from a GR64 register to a VR64 register.
2769 if (X86::VR64RegClass.contains(DestReg))
2770 return X86::MMX_MOVD64to64rr;
2771 }
2772
2773 // SrcReg(VR128) -> DestReg(GR32)
2774 // SrcReg(GR32) -> DestReg(VR128)
2775
2776 if (X86::GR32RegClass.contains(DestReg) &&
2777 X86::VR128XRegClass.contains(SrcReg))
2778 // Copy from a VR128 register to a GR32 register.
2779 return HasAVX512 ? X86::VMOVPDI2DIZrr :
2780 HasAVX ? X86::VMOVPDI2DIrr :
2781 X86::MOVPDI2DIrr;
2782
2783 if (X86::VR128XRegClass.contains(DestReg) &&
2784 X86::GR32RegClass.contains(SrcReg))
2785 // Copy from a VR128 register to a VR128 register.
2786 return HasAVX512 ? X86::VMOVDI2PDIZrr :
2787 HasAVX ? X86::VMOVDI2PDIrr :
2788 X86::MOVDI2PDIrr;
2789 return 0;
2790 }
2791
2792 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2793 MachineBasicBlock::iterator MI,
2794 const DebugLoc &DL, unsigned DestReg,
2795 unsigned SrcReg, bool KillSrc) const {
2796 // First deal with the normal symmetric copies.
2797 bool HasAVX = Subtarget.hasAVX();
2798 bool HasVLX = Subtarget.hasVLX();
2799 unsigned Opc = 0;
2800 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2801 Opc = X86::MOV64rr;
2802 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2803 Opc = X86::MOV32rr;
2804 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2805 Opc = X86::MOV16rr;
2806 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2807 // Copying to or from a physical H register on x86-64 requires a NOREX
2808 // move. Otherwise use a normal move.
2809 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2810 Subtarget.is64Bit()) {
2811 Opc = X86::MOV8rr_NOREX;
2812 // Both operands must be encodable without an REX prefix.
2813 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2814 "8-bit H register can not be copied outside GR8_NOREX");
2815 } else
2816 Opc = X86::MOV8rr;
2817 }
2818 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2819 Opc = X86::MMX_MOVQ64rr;
2820 else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
2821 if (HasVLX)
2822 Opc = X86::VMOVAPSZ128rr;
2823 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2824 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2825 else {
2826 // If this an extended register and we don't have VLX we need to use a
2827 // 512-bit move.
2828 Opc = X86::VMOVAPSZrr;
2829 const TargetRegisterInfo *TRI = &getRegisterInfo();
2830 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
2831 &X86::VR512RegClass);
2832 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
2833 &X86::VR512RegClass);
2834 }
2835 } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
2836 if (HasVLX)
2837 Opc = X86::VMOVAPSZ256rr;
2838 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2839 Opc = X86::VMOVAPSYrr;
2840 else {
2841 // If this an extended register and we don't have VLX we need to use a
2842 // 512-bit move.
2843 Opc = X86::VMOVAPSZrr;
2844 const TargetRegisterInfo *TRI = &getRegisterInfo();
2845 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
2846 &X86::VR512RegClass);
2847 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
2848 &X86::VR512RegClass);
2849 }
2850 } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
2851 Opc = X86::VMOVAPSZrr;
2852 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2853 else if (X86::VK16RegClass.contains(DestReg, SrcReg))
2854 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
2855 if (!Opc)
2856 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
2857
2858 if (Opc) {
2859 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2860 .addReg(SrcReg, getKillRegState(KillSrc));
2861 return;
2862 }
2863
2864 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
2865 // FIXME: We use a fatal error here because historically LLVM has tried
2866 // lower some of these physreg copies and we want to ensure we get
2867 // reasonable bug reports if someone encounters a case no other testing
2868 // found. This path should be removed after the LLVM 7 release.
2869 report_fatal_error("Unable to copy EFLAGS physical register!");
2870 }
2871
2872 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
2873 << RI.getName(DestReg) << '\n');
2874 report_fatal_error("Cannot emit physreg copy instruction");
2875 }
2876
2877 bool X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
2878 const MachineOperand *&Src,
2879 const MachineOperand *&Dest) const {
2880 if (MI.isMoveReg()) {
2881 Dest = &MI.getOperand(0);
2882 Src = &MI.getOperand(1);
2883 return true;
2884 }
2885 return false;
2886 }
2887
2888 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2889 const TargetRegisterClass *RC,
2890 bool isStackAligned,
2891 const X86Subtarget &STI,
2892 bool load) {
2893 bool HasAVX = STI.hasAVX();
2894 bool HasAVX512 = STI.hasAVX512();
2895 bool HasVLX = STI.hasVLX();
2896
2897 switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
2898 default:
2899 llvm_unreachable("Unknown spill size");
2900 case 1:
2901 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2902 if (STI.is64Bit())
2903 // Copying to or from a physical H register on x86-64 requires a NOREX
2904 // move. Otherwise use a normal move.
2905 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2906 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2907 return load ? X86::MOV8rm : X86::MOV8mr;
2908 case 2:
2909 if (X86::VK16RegClass.hasSubClassEq(RC))
2910 return load ? X86::KMOVWkm : X86::KMOVWmk;
2911 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2912 return load ? X86::MOV16rm : X86::MOV16mr;
2913 case 4:
2914 if (X86::GR32RegClass.hasSubClassEq(RC))
2915 return load ? X86::MOV32rm : X86::MOV32mr;
2916 if (X86::FR32XRegClass.hasSubClassEq(RC))
2917 return load ?
2918 (HasAVX512 ? X86::VMOVSSZrm_alt :
2919 HasAVX ? X86::VMOVSSrm_alt :
2920 X86::MOVSSrm_alt) :
2921 (HasAVX512 ? X86::VMOVSSZmr :
2922 HasAVX ? X86::VMOVSSmr :
2923 X86::MOVSSmr);
2924 if (X86::RFP32RegClass.hasSubClassEq(RC))
2925 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2926 if (X86::VK32RegClass.hasSubClassEq(RC)) {
2927 assert(STI.hasBWI() && "KMOVD requires BWI");
2928 return load ? X86::KMOVDkm : X86::KMOVDmk;
2929 }
2930 // All of these mask pair classes have the same spill size, the same kind
2931 // of kmov instructions can be used with all of them.
2932 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
2933 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
2934 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
2935 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
2936 X86::VK16PAIRRegClass.hasSubClassEq(RC))
2937 return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
2938 llvm_unreachable("Unknown 4-byte regclass");
2939 case 8:
2940 if (X86::GR64RegClass.hasSubClassEq(RC))
2941 return load ? X86::MOV64rm : X86::MOV64mr;
2942 if (X86::FR64XRegClass.hasSubClassEq(RC))
2943 return load ?
2944 (HasAVX512 ? X86::VMOVSDZrm_alt :
2945 HasAVX ? X86::VMOVSDrm_alt :
2946 X86::MOVSDrm_alt) :
2947 (HasAVX512 ? X86::VMOVSDZmr :
2948 HasAVX ? X86::VMOVSDmr :
2949 X86::MOVSDmr);
2950 if (X86::VR64RegClass.hasSubClassEq(RC))
2951 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2952 if (X86::RFP64RegClass.hasSubClassEq(RC))
2953 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2954 if (X86::VK64RegClass.hasSubClassEq(RC)) {
2955 assert(STI.hasBWI() && "KMOVQ requires BWI");
2956 return load ? X86::KMOVQkm : X86::KMOVQmk;
2957 }
2958 llvm_unreachable("Unknown 8-byte regclass");
2959 case 10:
2960 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2961 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2962 case 16: {
2963 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
2964 // If stack is realigned we can use aligned stores.
2965 if (isStackAligned)
2966 return load ?
2967 (HasVLX ? X86::VMOVAPSZ128rm :
2968 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
2969 HasAVX ? X86::VMOVAPSrm :
2970 X86::MOVAPSrm):
2971 (HasVLX ? X86::VMOVAPSZ128mr :
2972 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
2973 HasAVX ? X86::VMOVAPSmr :
2974 X86::MOVAPSmr);
2975 else
2976 return load ?
2977 (HasVLX ? X86::VMOVUPSZ128rm :
2978 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
2979 HasAVX ? X86::VMOVUPSrm :
2980 X86::MOVUPSrm):
2981 (HasVLX ? X86::VMOVUPSZ128mr :
2982 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
2983 HasAVX ? X86::VMOVUPSmr :
2984 X86::MOVUPSmr);
2985 }
2986 if (X86::BNDRRegClass.hasSubClassEq(RC)) {
2987 if (STI.is64Bit())
2988 return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
2989 else
2990 return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
2991 }
2992 llvm_unreachable("Unknown 16-byte regclass");
2993 }
2994 case 32:
2995 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2996 // If stack is realigned we can use aligned stores.
2997 if (isStackAligned)
2998 return load ?
2999 (HasVLX ? X86::VMOVAPSZ256rm :
3000 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3001 X86::VMOVAPSYrm) :
3002 (HasVLX ? X86::VMOVAPSZ256mr :
3003 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3004 X86::VMOVAPSYmr);
3005 else
3006 return load ?
3007 (HasVLX ? X86::VMOVUPSZ256rm :
3008 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3009 X86::VMOVUPSYrm) :
3010 (HasVLX ? X86::VMOVUPSZ256mr :
3011 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3012 X86::VMOVUPSYmr);
3013 case 64:
3014 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3015 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3016 if (isStackAligned)
3017 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3018 else
3019 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3020 }
3021 }
3022
3023 bool X86InstrInfo::getMemOperandWithOffset(
3024 const MachineInstr &MemOp, const MachineOperand *&BaseOp, int64_t &Offset,
3025 const TargetRegisterInfo *TRI) const {
3026 const MCInstrDesc &Desc = MemOp.getDesc();
3027 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3028 if (MemRefBegin < 0)
3029 return false;
3030
3031 MemRefBegin += X86II::getOperandBias(Desc);
3032
3033 BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3034 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3035 return false;
3036
3037 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3038 return false;
3039
3040 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3041 X86::NoRegister)
3042 return false;
3043
3044 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3045
3046 // Displacement can be symbolic
3047 if (!DispMO.isImm())
3048 return false;
3049
3050 Offset = DispMO.getImm();
3051
3052 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
3053 "operands of type register.");
3054 return true;
3055 }
3056
3057 static unsigned getStoreRegOpcode(unsigned SrcReg,
3058 const TargetRegisterClass *RC,
3059 bool isStackAligned,
3060 const X86Subtarget &STI) {
3061 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3062 }
3063
3064
3065 static unsigned getLoadRegOpcode(unsigned DestReg,
3066 const TargetRegisterClass *RC,
3067 bool isStackAligned,
3068 const X86Subtarget &STI) {
3069 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3070 }
3071
3072 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3073 MachineBasicBlock::iterator MI,
3074 unsigned SrcReg, bool isKill, int FrameIdx,
3075 const TargetRegisterClass *RC,
3076 const TargetRegisterInfo *TRI) const {
3077 const MachineFunction &MF = *MBB.getParent();
3078 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3079 "Stack slot too small for store");
3080 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3081 bool isAligned =
3082 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3083 RI.canRealignStack(MF);
3084 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3085 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3086 .addReg(SrcReg, getKillRegState(isKill));
3087 }
3088
3089 void X86InstrInfo::storeRegToAddr(
3090 MachineFunction &MF, unsigned SrcReg, bool isKill,
3091 SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3092 ArrayRef<MachineMemOperand *> MMOs,
3093 SmallVectorImpl<MachineInstr *> &NewMIs) const {
3094 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3095 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3096 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3097 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3098 DebugLoc DL;
3099 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3100 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3101 MIB.add(Addr[i]);
3102 MIB.addReg(SrcReg, getKillRegState(isKill));
3103 MIB.setMemRefs(MMOs);
3104 NewMIs.push_back(MIB);
3105 }
3106
3107
3108 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3109 MachineBasicBlock::iterator MI,
3110 unsigned DestReg, int FrameIdx,
3111 const TargetRegisterClass *RC,
3112 const TargetRegisterInfo *TRI) const {
3113 const MachineFunction &MF = *MBB.getParent();
3114 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3115 bool isAligned =
3116 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3117 RI.canRealignStack(MF);
3118 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3119 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3120 }
3121
3122 void X86InstrInfo::loadRegFromAddr(
3123 MachineFunction &MF, unsigned DestReg,
3124 SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3125 ArrayRef<MachineMemOperand *> MMOs,
3126 SmallVectorImpl<MachineInstr *> &NewMIs) const {
3127 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3128 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3129 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3130 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3131 DebugLoc DL;
3132 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3133 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3134 MIB.add(Addr[i]);
3135 MIB.setMemRefs(MMOs);
3136 NewMIs.push_back(MIB);
3137 }
3138
3139 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
3140 unsigned &SrcReg2, int &CmpMask,
3141 int &CmpValue) const {
3142 switch (MI.getOpcode()) {
3143 default: break;
3144 case X86::CMP64ri32:
3145 case X86::CMP64ri8:
3146 case X86::CMP32ri:
3147 case X86::CMP32ri8:
3148 case X86::CMP16ri:
3149 case X86::CMP16ri8:
3150 case X86::CMP8ri:
3151 SrcReg = MI.getOperand(0).getReg();
3152 SrcReg2 = 0;
3153 if (MI.getOperand(1).isImm()) {
3154 CmpMask = ~0;
3155 CmpValue = MI.getOperand(1).getImm();
3156 } else {
3157 CmpMask = CmpValue = 0;
3158 }
3159 return true;
3160 // A SUB can be used to perform comparison.
3161 case X86::SUB64rm:
3162 case X86::SUB32rm:
3163 case X86::SUB16rm:
3164 case X86::SUB8rm:
3165 SrcReg = MI.getOperand(1).getReg();
3166 SrcReg2 = 0;
3167 CmpMask = 0;
3168 CmpValue = 0;
3169 return true;
3170 case X86::SUB64rr:
3171 case X86::SUB32rr:
3172 case X86::SUB16rr:
3173 case X86::SUB8rr:
3174 SrcReg = MI.getOperand(1).getReg();
3175 SrcReg2 = MI.getOperand(2).getReg();
3176 CmpMask = 0;
3177 CmpValue = 0;
3178 return true;
3179 case X86::SUB64ri32:
3180 case X86::SUB64ri8:
3181 case X86::SUB32ri:
3182 case X86::SUB32ri8:
3183 case X86::SUB16ri:
3184 case X86::SUB16ri8:
3185 case X86::SUB8ri:
3186 SrcReg = MI.getOperand(1).getReg();
3187 SrcReg2 = 0;
3188 if (MI.getOperand(2).isImm()) {
3189 CmpMask = ~0;
3190 CmpValue = MI.getOperand(2).getImm();
3191 } else {
3192 CmpMask = CmpValue = 0;
3193 }
3194 return true;
3195 case X86::CMP64rr:
3196 case X86::CMP32rr:
3197 case X86::CMP16rr:
3198 case X86::CMP8rr:
3199 SrcReg = MI.getOperand(0).getReg();
3200 SrcReg2 = MI.getOperand(1).getReg();
3201 CmpMask = 0;
3202 CmpValue = 0;
3203 return true;
3204 case X86::TEST8rr:
3205 case X86::TEST16rr:
3206 case X86::TEST32rr:
3207 case X86::TEST64rr:
3208 SrcReg = MI.getOperand(0).getReg();
3209 if (MI.getOperand(1).getReg() != SrcReg)
3210 return false;
3211 // Compare against zero.
3212 SrcReg2 = 0;
3213 CmpMask = ~0;
3214 CmpValue = 0;
3215 return true;
3216 }
3217 return false;
3218 }
3219
3220 /// Check whether the first instruction, whose only
3221 /// purpose is to update flags, can be made redundant.
3222 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3223 /// This function can be extended later on.
3224 /// SrcReg, SrcRegs: register operands for FlagI.
3225 /// ImmValue: immediate for FlagI if it takes an immediate.
3226 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3227 unsigned SrcReg, unsigned SrcReg2,
3228 int ImmMask, int ImmValue,
3229 const MachineInstr &OI) {
3230 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3231 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3232 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3233 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3234 ((OI.getOperand(1).getReg() == SrcReg &&
3235 OI.getOperand(2).getReg() == SrcReg2) ||
3236 (OI.getOperand(1).getReg() == SrcReg2 &&
3237 OI.getOperand(2).getReg() == SrcReg)))
3238 return true;
3239
3240 if (ImmMask != 0 &&
3241 ((FlagI.getOpcode() == X86::CMP64ri32 &&
3242 OI.getOpcode() == X86::SUB64ri32) ||
3243 (FlagI.getOpcode() == X86::CMP64ri8 &&
3244 OI.getOpcode() == X86::SUB64ri8) ||
3245 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3246 (FlagI.getOpcode() == X86::CMP32ri8 &&
3247 OI.getOpcode() == X86::SUB32ri8) ||
3248 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3249 (FlagI.getOpcode() == X86::CMP16ri8 &&
3250 OI.getOpcode() == X86::SUB16ri8) ||
3251 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3252 OI.getOperand(1).getReg() == SrcReg &&
3253 OI.getOperand(2).getImm() == ImmValue)
3254 return true;
3255 return false;
3256 }
3257
3258 /// Check whether the definition can be converted
3259 /// to remove a comparison against zero.
3260 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3261 NoSignFlag = false;
3262
3263 switch (MI.getOpcode()) {
3264 default: return false;
3265
3266 // The shift instructions only modify ZF if their shift count is non-zero.
3267 // N.B.: The processor truncates the shift count depending on the encoding.
3268 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3269 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3270 return getTruncatedShiftCount(MI, 2) != 0;
3271
3272 // Some left shift instructions can be turned into LEA instructions but only
3273 // if their flags aren't used. Avoid transforming such instructions.
3274 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3275 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3276 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3277 return ShAmt != 0;
3278 }
3279
3280 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3281 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3282 return getTruncatedShiftCount(MI, 3) != 0;
3283
3284 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3285 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3286 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3287 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3288 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3289 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3290 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3291 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3292 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3293 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3294 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3295 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3296 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3297 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3298 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3299 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3300 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3301 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3302 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3303 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3304 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3305 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3306 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3307 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3308 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3309 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3310 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3311 case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3312 case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
3313 case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
3314 case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
3315 case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
3316 case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3317 case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
3318 case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
3319 case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
3320 case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
3321 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3322 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3323 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3324 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3325 case X86::ANDN32rr: case X86::ANDN32rm:
3326 case X86::ANDN64rr: case X86::ANDN64rm:
3327 case X86::BLSI32rr: case X86::BLSI32rm:
3328 case X86::BLSI64rr: case X86::BLSI64rm:
3329 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3330 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3331 case X86::BLSR32rr: case X86::BLSR32rm:
3332 case X86::BLSR64rr: case X86::BLSR64rm:
3333 case X86::BZHI32rr: case X86::BZHI32rm:
3334 case X86::BZHI64rr: case X86::BZHI64rm:
3335 case X86::LZCNT16rr: case X86::LZCNT16rm:
3336 case X86::LZCNT32rr: case X86::LZCNT32rm:
3337 case X86::LZCNT64rr: case X86::LZCNT64rm:
3338 case X86::POPCNT16rr:case X86::POPCNT16rm:
3339 case X86::POPCNT32rr:case X86::POPCNT32rm:
3340 case X86::POPCNT64rr:case X86::POPCNT64rm:
3341 case X86::TZCNT16rr: case X86::TZCNT16rm:
3342 case X86::TZCNT32rr: case X86::TZCNT32rm:
3343 case X86::TZCNT64rr: case X86::TZCNT64rm:
3344 case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3345 case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3346 case X86::BLCI32rr: case X86::BLCI32rm:
3347 case X86::BLCI64rr: case X86::BLCI64rm:
3348 case X86::BLCIC32rr: case X86::BLCIC32rm:
3349 case X86::BLCIC64rr: case X86::BLCIC64rm:
3350 case X86::BLCMSK32rr: case X86::BLCMSK32rm:
3351 case X86::BLCMSK64rr: case X86::BLCMSK64rm:
3352 case X86::BLCS32rr: case X86::BLCS32rm:
3353 case X86::BLCS64rr: case X86::BLCS64rm:
3354 case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3355 case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3356 case X86::BLSIC32rr: case X86::BLSIC32rm:
3357 case X86::BLSIC64rr: case X86::BLSIC64rm:
3358 case X86::T1MSKC32rr: case X86::T1MSKC32rm:
3359 case X86::T1MSKC64rr: case X86::T1MSKC64rm:
3360 case X86::TZMSK32rr: case X86::TZMSK32rm:
3361 case X86::TZMSK64rr: case X86::TZMSK64rm:
3362 return true;
3363 case X86::BEXTR32rr: case X86::BEXTR64rr:
3364 case X86::BEXTR32rm: case X86::BEXTR64rm:
3365 case X86::BEXTRI32ri: case X86::BEXTRI32mi:
3366 case X86::BEXTRI64ri: case X86::BEXTRI64mi:
3367 // BEXTR doesn't update the sign flag so we can't use it.
3368 NoSignFlag = true;
3369 return true;
3370 }
3371 }
3372
3373 /// Check whether the use can be converted to remove a comparison against zero.
3374 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
3375 switch (MI.getOpcode()) {
3376 default: return X86::COND_INVALID;
3377 case X86::NEG8r:
3378 case X86::NEG16r:
3379 case X86::NEG32r:
3380 case X86::NEG64r:
3381 return X86::COND_AE;
3382 case X86::LZCNT16rr:
3383 case X86::LZCNT32rr:
3384 case X86::LZCNT64rr:
3385 return X86::COND_B;
3386 case X86::POPCNT16rr:
3387 case X86::POPCNT32rr:
3388 case X86::POPCNT64rr:
3389 return X86::COND_E;
3390 case X86::TZCNT16rr:
3391 case X86::TZCNT32rr:
3392 case X86::TZCNT64rr:
3393 return X86::COND_B;
3394 case X86::BSF16rr:
3395 case X86::BSF32rr:
3396 case X86::BSF64rr:
3397 case X86::BSR16rr:
3398 case X86::BSR32rr:
3399 case X86::BSR64rr:
3400 return X86::COND_E;
3401 case X86::BLSI32rr:
3402 case X86::BLSI64rr:
3403 return X86::COND_AE;
3404 case X86::BLSR32rr:
3405 case X86::BLSR64rr:
3406 case X86::BLSMSK32rr:
3407 case X86::BLSMSK64rr:
3408 return X86::COND_B;
3409 // TODO: TBM instructions.
3410 }
3411 }
3412
3413 /// Check if there exists an earlier instruction that
3414 /// operates on the same source operands and sets flags in the same way as
3415 /// Compare; remove Compare if possible.
3416 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
3417 unsigned SrcReg2, int CmpMask,
3418 int CmpValue,
3419 const MachineRegisterInfo *MRI) const {
3420 // Check whether we can replace SUB with CMP.
3421 switch (CmpInstr.getOpcode()) {
3422 default: break;
3423 case X86::SUB64ri32:
3424 case X86::SUB64ri8:
3425 case X86::SUB32ri:
3426 case X86::SUB32ri8:
3427 case X86::SUB16ri:
3428 case X86::SUB16ri8:
3429 case X86::SUB8ri:
3430 case X86::SUB64rm:
3431 case X86::SUB32rm:
3432 case X86::SUB16rm:
3433 case X86::SUB8rm:
3434 case X86::SUB64rr:
3435 case X86::SUB32rr:
3436 case X86::SUB16rr:
3437 case X86::SUB8rr: {
3438 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3439 return false;
3440 // There is no use of the destination register, we can replace SUB with CMP.
3441 unsigned NewOpcode = 0;
3442 switch (CmpInstr.getOpcode()) {
3443 default: llvm_unreachable("Unreachable!");
3444 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3445 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3446 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3447 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3448 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3449 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3450 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3451 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3452 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3453 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3454 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3455 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3456 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3457 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3458 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3459 }
3460 CmpInstr.setDesc(get(NewOpcode));
3461 CmpInstr.RemoveOperand(0);
3462 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3463 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3464 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3465 return false;
3466 }
3467 }
3468
3469 // Get the unique definition of SrcReg.
3470 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3471 if (!MI) return false;
3472
3473 // CmpInstr is the first instruction of the BB.
3474 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3475
3476 // If we are comparing against zero, check whether we can use MI to update
3477 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3478 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
3479 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
3480 return false;
3481
3482 // If we have a use of the source register between the def and our compare
3483 // instruction we can eliminate the compare iff the use sets EFLAGS in the
3484 // right way.
3485 bool ShouldUpdateCC = false;
3486 bool NoSignFlag = false;
3487 X86::CondCode NewCC = X86::COND_INVALID;
3488 if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
3489 // Scan forward from the use until we hit the use we're looking for or the
3490 // compare instruction.
3491 for (MachineBasicBlock::iterator J = MI;; ++J) {
3492 // Do we have a convertible instruction?
3493 NewCC = isUseDefConvertible(*J);
3494 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3495 J->getOperand(1).getReg() == SrcReg) {
3496 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3497 ShouldUpdateCC = true; // Update CC later on.
3498 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3499 // with the new def.
3500 Def = J;
3501 MI = &*Def;
3502 break;
3503 }
3504
3505 if (J == I)
3506 return false;
3507 }
3508 }
3509
3510 // We are searching for an earlier instruction that can make CmpInstr
3511 // redundant and that instruction will be saved in Sub.
3512 MachineInstr *Sub = nullptr;
3513 const TargetRegisterInfo *TRI = &getRegisterInfo();
3514
3515 // We iterate backward, starting from the instruction before CmpInstr and
3516 // stop when reaching the definition of a source register or done with the BB.
3517 // RI points to the instruction before CmpInstr.
3518 // If the definition is in this basic block, RE points to the definition;
3519 // otherwise, RE is the rend of the basic block.
3520 MachineBasicBlock::reverse_iterator
3521 RI = ++I.getReverse(),
3522 RE = CmpInstr.getParent() == MI->getParent()
3523 ? Def.getReverse() /* points to MI */
3524 : CmpInstr.getParent()->rend();
3525 MachineInstr *Movr0Inst = nullptr;
3526 for (; RI != RE; ++RI) {
3527 MachineInstr &Instr = *RI;
3528 // Check whether CmpInstr can be made redundant by the current instruction.
3529 if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
3530 CmpValue, Instr)) {
3531 Sub = &Instr;
3532 break;
3533 }
3534
3535 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3536 Instr.readsRegister(X86::EFLAGS, TRI)) {
3537 // This instruction modifies or uses EFLAGS.
3538
3539 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3540 // They are safe to move up, if the definition to EFLAGS is dead and
3541 // earlier instructions do not read or write EFLAGS.
3542 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
3543 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
3544 Movr0Inst = &Instr;
3545 continue;
3546 }
3547
3548 // We can't remove CmpInstr.
3549 return false;
3550 }
3551 }
3552
3553 // Return false if no candidates exist.
3554 if (!IsCmpZero && !Sub)
3555 return false;
3556
3557 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3558 Sub->getOperand(2).getReg() == SrcReg);
3559
3560 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3561 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3562 // If we are done with the basic block, we need to check whether EFLAGS is
3563 // live-out.
3564 bool IsSafe = false;
3565 SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
3566 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3567 for (++I; I != E; ++I) {
3568 const MachineInstr &Instr = *I;
3569 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3570 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3571 // We should check the usage if this instruction uses and updates EFLAGS.
3572 if (!UseEFLAGS && ModifyEFLAGS) {
3573 // It is safe to remove CmpInstr if EFLAGS is updated again.
3574 IsSafe = true;
3575 break;
3576 }
3577 if (!UseEFLAGS && !ModifyEFLAGS)
3578 continue;
3579
3580 // EFLAGS is used by this instruction.
3581 X86::CondCode OldCC = X86::COND_INVALID;
3582 if (IsCmpZero || IsSwapped) {
3583 // We decode the condition code from opcode.
3584 if (Instr.isBranch())
3585 OldCC = X86::getCondFromBranch(Instr);
3586 else {
3587 OldCC = X86::getCondFromSETCC(Instr);
3588 if (OldCC == X86::COND_INVALID)
3589 OldCC = X86::getCondFromCMov(Instr);
3590 }
3591 if (OldCC == X86::COND_INVALID) return false;
3592 }
3593 X86::CondCode ReplacementCC = X86::COND_INVALID;
3594 if (IsCmpZero) {
3595 switch (OldCC) {
3596 default: break;
3597 case X86::COND_A: case X86::COND_AE:
3598 case X86::COND_B: case X86::COND_BE:
3599 case X86::COND_G: case X86::COND_GE:
3600 case X86::COND_L: case X86::COND_LE:
3601 case X86::COND_O: case X86::COND_NO:
3602 // CF and OF are used, we can't perform this optimization.
3603 return false;
3604 case X86::COND_S: case X86::COND_NS:
3605 // If SF is used, but the instruction doesn't update the SF, then we
3606 // can't do the optimization.
3607 if (NoSignFlag)
3608 return false;
3609 break;
3610 }
3611
3612 // If we're updating the condition code check if we have to reverse the
3613 // condition.
3614 if (ShouldUpdateCC)
3615 switch (OldCC) {
3616 default:
3617 return false;
3618 case X86::COND_E:
3619 ReplacementCC = NewCC;
3620 break;
3621 case X86::COND_NE:
3622 ReplacementCC = GetOppositeBranchCondition(NewCC);
3623 break;
3624 }
3625 } else if (IsSwapped) {
3626 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3627 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3628 // We swap the condition code and synthesize the new opcode.
3629 ReplacementCC = getSwappedCondition(OldCC);
3630 if (ReplacementCC == X86::COND_INVALID) return false;
3631 }
3632
3633 if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
3634 // Push the MachineInstr to OpsToUpdate.
3635 // If it is safe to remove CmpInstr, the condition code of these
3636 // instructions will be modified.
3637 OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
3638 }
3639 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3640 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3641 IsSafe = true;
3642 break;
3643 }
3644 }
3645
3646 // If EFLAGS is not killed nor re-defined, we should check whether it is
3647 // live-out. If it is live-out, do not optimize.
3648 if ((IsCmpZero || IsSwapped) && !IsSafe) {
3649 MachineBasicBlock *MBB = CmpInstr.getParent();
3650 for (MachineBasicBlock *Successor : MBB->successors())
3651 if (Successor->isLiveIn(X86::EFLAGS))
3652 return false;
3653 }
3654
3655 // The instruction to be updated is either Sub or MI.
3656 Sub = IsCmpZero ? MI : Sub;
3657 // Move Movr0Inst to the appropriate place before Sub.
3658 if (Movr0Inst) {
3659 // Look backwards until we find a def that doesn't use the current EFLAGS.
3660 Def = Sub;
3661 MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
3662 InsertE = Sub->getParent()->rend();
3663 for (; InsertI != InsertE; ++InsertI) {
3664 MachineInstr *Instr = &*InsertI;
3665 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3666 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3667 Sub->getParent()->remove(Movr0Inst);
3668 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3669 Movr0Inst);
3670 break;
3671 }
3672 }
3673 if (InsertI == InsertE)
3674 return false;
3675 }
3676
3677 // Make sure Sub instruction defines EFLAGS and mark the def live.
3678 MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
3679 assert(FlagDef && "Unable to locate a def EFLAGS operand");
3680 FlagDef->setIsDead(false);
3681
3682 CmpInstr.eraseFromParent();
3683
3684 // Modify the condition code of instructions in OpsToUpdate.
3685 for (auto &Op : OpsToUpdate) {
3686 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
3687 .setImm(Op.second);
3688 }
3689 return true;
3690 }
3691
3692 /// Try to remove the load by folding it to a register
3693 /// operand at the use. We fold the load instructions if load defines a virtual
3694 /// register, the virtual register is used once in the same BB, and the
3695 /// instructions in-between do not load or store, and have no side effects.
3696 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
3697 const MachineRegisterInfo *MRI,
3698 unsigned &FoldAsLoadDefReg,
3699 MachineInstr *&DefMI) const {
3700 // Check whether we can move DefMI here.
3701 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3702 assert(DefMI);
3703 bool SawStore = false;
3704 if (!DefMI->isSafeToMove(nullptr, SawStore))
3705 return nullptr;
3706
3707 // Collect information about virtual register operands of MI.
3708 SmallVector<unsigned, 1> SrcOperandIds;
3709 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3710 MachineOperand &MO = MI.getOperand(i);
3711 if (!MO.isReg())
3712 continue;
3713 unsigned Reg = MO.getReg();
3714 if (Reg != FoldAsLoadDefReg)
3715 continue;
3716 // Do not fold if we have a subreg use or a def.
3717 if (MO.getSubReg() || MO.isDef())
3718 return nullptr;
3719 SrcOperandIds.push_back(i);
3720 }
3721 if (SrcOperandIds.empty())
3722 return nullptr;
3723
3724 // Check whether we can fold the def into SrcOperandId.
3725 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
3726 FoldAsLoadDefReg = 0;
3727 return FoldMI;
3728 }
3729
3730 return nullptr;
3731 }
3732
3733 /// Expand a single-def pseudo instruction to a two-addr
3734 /// instruction with two undef reads of the register being defined.
3735 /// This is used for mapping:
3736 /// %xmm4 = V_SET0
3737 /// to:
3738 /// %xmm4 = PXORrr undef %xmm4, undef %xmm4
3739 ///
3740 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3741 const MCInstrDesc &Desc) {
3742 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3743 unsigned Reg = MIB->getOperand(0).getReg();
3744 MIB->setDesc(Desc);
3745
3746 // MachineInstr::addOperand() will insert explicit operands before any
3747 // implicit operands.
3748 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3749 // But we don't trust that.
3750 assert(MIB->getOperand(1).getReg() == Reg &&
3751 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3752 return true;
3753 }
3754
3755 /// Expand a single-def pseudo instruction to a two-addr
3756 /// instruction with two %k0 reads.
3757 /// This is used for mapping:
3758 /// %k4 = K_SET1
3759 /// to:
3760 /// %k4 = KXNORrr %k0, %k0
3761 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
3762 const MCInstrDesc &Desc, unsigned Reg) {
3763 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3764 MIB->setDesc(Desc);
3765 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3766 return true;
3767 }
3768
3769 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
3770 bool MinusOne) {
3771 MachineBasicBlock &MBB = *MIB->getParent();
3772 DebugLoc DL = MIB->getDebugLoc();
3773 unsigned Reg = MIB->getOperand(0).getReg();
3774
3775 // Insert the XOR.
3776 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3777 .addReg(Reg, RegState::Undef)
3778 .addReg(Reg, RegState::Undef);
3779
3780 // Turn the pseudo into an INC or DEC.
3781 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3782 MIB.addReg(Reg);
3783
3784 return true;
3785 }
3786
3787 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
3788 const TargetInstrInfo &TII,
3789 const X86Subtarget &Subtarget) {
3790 MachineBasicBlock &MBB = *MIB->getParent();
3791 DebugLoc DL = MIB->getDebugLoc();
3792 int64_t Imm = MIB->getOperand(1).getImm();
3793 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
3794 MachineBasicBlock::iterator I = MIB.getInstr();
3795
3796 int StackAdjustment;
3797
3798 if (Subtarget.is64Bit()) {
3799 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
3800 MIB->getOpcode() == X86::MOV32ImmSExti8);
3801
3802 // Can't use push/pop lowering if the function might write to the red zone.
3803 X86MachineFunctionInfo *X86FI =
3804 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
3805 if (X86FI->getUsesRedZone()) {
3806 MIB->setDesc(TII.get(MIB->getOpcode() ==
3807 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
3808 return true;
3809 }
3810
3811 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
3812 // widen the register if necessary.
3813 StackAdjustment = 8;
3814 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3815 MIB->setDesc(TII.get(X86::POP64r));
3816 MIB->getOperand(0)
3817 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
3818 } else {
3819 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
3820 StackAdjustment = 4;
3821 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
3822 MIB->setDesc(TII.get(X86::POP32r));
3823 }
3824
3825 // Build CFI if necessary.
3826 MachineFunction &MF = *MBB.getParent();
3827 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
3828 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3829 bool NeedsDwarfCFI =
3830 !IsWin64Prologue &&
3831 (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry());
3832 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
3833 if (EmitCFI) {
3834 TFL->BuildCFI(MBB, I, DL,
3835 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
3836 TFL->BuildCFI(MBB, std::next(I), DL,
3837 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
3838 }
3839
3840 return true;
3841 }
3842
3843 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
3844 // code sequence is needed for other targets.
3845 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
3846 const TargetInstrInfo &TII) {
3847 MachineBasicBlock &MBB = *MIB->getParent();
3848 DebugLoc DL = MIB->getDebugLoc();
3849 unsigned Reg = MIB->getOperand(0).getReg();
3850 const GlobalValue *GV =
3851 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
3852 auto Flags = MachineMemOperand::MOLoad |
3853 MachineMemOperand::MODereferenceable |
3854 MachineMemOperand::MOInvariant;
3855 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
3856 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
3857 MachineBasicBlock::iterator I = MIB.getInstr();
3858
3859 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
3860 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
3861 .addMemOperand(MMO);
3862 MIB->setDebugLoc(DL);
3863 MIB->setDesc(TII.get(X86::MOV64rm));
3864 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
3865 }
3866
3867 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
3868 MachineBasicBlock &MBB = *MIB->getParent();
3869 MachineFunction &MF = *MBB.getParent();
3870 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
3871 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
3872 unsigned XorOp =
3873 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
3874 MIB->setDesc(TII.get(XorOp));
3875 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
3876 return true;
3877 }
3878
3879 // This is used to handle spills for 128/256-bit registers when we have AVX512,
3880 // but not VLX. If it uses an extended register we need to use an instruction
3881 // that loads the lower 128/256-bit, but is available with only AVX512F.
3882 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
3883 const TargetRegisterInfo *TRI,
3884 const MCInstrDesc &LoadDesc,
3885 const MCInstrDesc &BroadcastDesc,
3886 unsigned SubIdx) {
3887 unsigned DestReg = MIB->getOperand(0).getReg();
3888 // Check if DestReg is XMM16-31 or YMM16-31.
3889 if (TRI->getEncodingValue(DestReg) < 16) {
3890 // We can use a normal VEX encoded load.
3891 MIB->setDesc(LoadDesc);
3892 } else {
3893 // Use a 128/256-bit VBROADCAST instruction.
3894 MIB->setDesc(BroadcastDesc);
3895 // Change the destination to a 512-bit register.
3896 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
3897 MIB->getOperand(0).setReg(DestReg);
3898 }
3899 return true;
3900 }
3901
3902 // This is used to handle spills for 128/256-bit registers when we have AVX512,
3903 // but not VLX. If it uses an extended register we need to use an instruction
3904 // that stores the lower 128/256-bit, but is available with only AVX512F.
3905 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
3906 const TargetRegisterInfo *TRI,
3907 const MCInstrDesc &StoreDesc,
3908 const MCInstrDesc &ExtractDesc,
3909 unsigned SubIdx) {
3910 unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
3911 // Check if DestReg is XMM16-31 or YMM16-31.
3912 if (TRI->getEncodingValue(SrcReg) < 16) {
3913 // We can use a normal VEX encoded store.
3914 MIB->setDesc(StoreDesc);
3915 } else {
3916 // Use a VEXTRACTF instruction.
3917 MIB->setDesc(ExtractDesc);
3918 // Change the destination to a 512-bit register.
3919 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
3920 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
3921 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
3922 }
3923
3924 return true;
3925 }
3926
3927 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
3928 MIB->setDesc(Desc);
3929 int64_t ShiftAmt = MIB->getOperand(2).getImm();
3930 // Temporarily remove the immediate so we can add another source register.
3931 MIB->RemoveOperand(2);
3932 // Add the register. Don't copy the kill flag if there is one.
3933 MIB.addReg(MIB->getOperand(1).getReg(),
3934 getUndefRegState(MIB->getOperand(1).isUndef()));
3935 // Add back the immediate.
3936 MIB.addImm(ShiftAmt);
3937 return true;
3938 }
3939
3940 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
3941 bool HasAVX = Subtarget.hasAVX();
3942 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
3943 switch (MI.getOpcode()) {
3944 case X86::MOV32r0:
3945 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
3946 case X86::MOV32r1:
3947 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
3948 case X86::MOV32r_1:
3949 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
3950 case X86::MOV32ImmSExti8:
3951 case X86::MOV64ImmSExti8:
3952 return ExpandMOVImmSExti8(MIB, *this, Subtarget);
3953 case X86::SETB_C8r:
3954 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
3955 case X86::SETB_C16r:
3956 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
3957 case X86::SETB_C32r:
3958 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
3959 case X86::SETB_C64r:
3960 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
3961 case X86::MMX_SET0:
3962 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
3963 case X86::V_SET0:
3964 case X86::FsFLD0SS:
3965 case X86::FsFLD0SD:
3966 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
3967 case X86::AVX_SET0: {
3968 assert(HasAVX && "AVX not supported");
3969 const TargetRegisterInfo *TRI = &getRegisterInfo();
3970 unsigned SrcReg = MIB->getOperand(0).getReg();
3971 unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
3972 MIB->getOperand(0).setReg(XReg);
3973 Expand2AddrUndef(MIB, get(X86::VXORPSrr));
3974 MIB.addReg(SrcReg, RegState::ImplicitDefine);
3975 return true;
3976 }
3977 case X86::AVX512_128_SET0:
3978 case X86::AVX512_FsFLD0SS:
3979 case X86::AVX512_FsFLD0SD: {
3980 bool HasVLX = Subtarget.hasVLX();
3981 unsigned SrcReg = MIB->getOperand(0).getReg();
3982 const TargetRegisterInfo *TRI = &getRegisterInfo();
3983 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
3984 return Expand2AddrUndef(MIB,
3985 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
3986 // Extended register without VLX. Use a larger XOR.
3987 SrcReg =
3988 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
3989 MIB->getOperand(0).setReg(SrcReg);
3990 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
3991 }
3992 case X86::AVX512_256_SET0:
3993 case X86::AVX512_512_SET0: {
3994 bool HasVLX = Subtarget.hasVLX();
3995 unsigned SrcReg = MIB->getOperand(0).getReg();
3996 const TargetRegisterInfo *TRI = &getRegisterInfo();
3997 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
3998 unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
3999 MIB->getOperand(0).setReg(XReg);
4000 Expand2AddrUndef(MIB,
4001 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4002 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4003 return true;
4004 }
4005 if (MI.getOpcode() == X86::AVX512_256_SET0) {
4006 // No VLX so we must reference a zmm.
4007 unsigned ZReg =
4008 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4009 MIB->getOperand(0).setReg(ZReg);
4010 }
4011 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4012 }
4013 case X86::V_SETALLONES:
4014 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4015 case X86::AVX2_SETALLONES:
4016 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4017 case X86::AVX1_SETALLONES: {
4018 unsigned Reg = MIB->getOperand(0).getReg();
4019 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4020 MIB->setDesc(get(X86::VCMPPSYrri));
4021 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4022 return true;
4023 }
4024 case X86::AVX512_512_SETALLONES: {
4025 unsigned Reg = MIB->getOperand(0).getReg();
4026 MIB->setDesc(get(X86::VPTERNLOGDZrri));
4027 // VPTERNLOGD needs 3 register inputs and an immediate.
4028 // 0xff will return 1s for any input.
4029 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4030 .addReg(Reg, RegState::Undef).addImm(0xff);
4031 return true;
4032 }
4033 case X86::AVX512_512_SEXT_MASK_32:
4034 case X86::AVX512_512_SEXT_MASK_64: {
4035 unsigned Reg = MIB->getOperand(0).getReg();
4036 unsigned MaskReg = MIB->getOperand(1).getReg();
4037 unsigned MaskState = getRegState(MIB->getOperand(1));
4038 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4039 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4040 MI.RemoveOperand(1);
4041 MIB->setDesc(get(Opc));
4042 // VPTERNLOG needs 3 register inputs and an immediate.
4043 // 0xff will return 1s for any input.
4044 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4045 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4046 return true;
4047 }
4048 case X86::VMOVAPSZ128rm_NOVLX:
4049 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4050 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4051 case X86::VMOVUPSZ128rm_NOVLX:
4052 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4053 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4054 case X86::VMOVAPSZ256rm_NOVLX:
4055 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4056 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4057 case X86::VMOVUPSZ256rm_NOVLX:
4058 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4059 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4060 case X86::VMOVAPSZ128mr_NOVLX:
4061 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4062 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4063 case X86::VMOVUPSZ128mr_NOVLX:
4064 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4065 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4066 case X86::VMOVAPSZ256mr_NOVLX:
4067 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4068 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4069 case X86::VMOVUPSZ256mr_NOVLX:
4070 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4071 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4072 case X86::MOV32ri64: {
4073 unsigned Reg = MIB->getOperand(0).getReg();
4074 unsigned Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4075 MI.setDesc(get(X86::MOV32ri));
4076 MIB->getOperand(0).setReg(Reg32);
4077 MIB.addReg(Reg, RegState::ImplicitDefine);
4078 return true;
4079 }
4080
4081 // KNL does not recognize dependency-breaking idioms for mask registers,
4082 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4083 // Using %k0 as the undef input register is a performance heuristic based
4084 // on the assumption that %k0 is used less frequently than the other mask
4085 // registers, since it is not usable as a write mask.
4086 // FIXME: A more advanced approach would be to choose the best input mask
4087 // register based on context.
4088 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4089 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4090 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4091 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4092 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4093 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4094 case TargetOpcode::LOAD_STACK_GUARD:
4095 expandLoadStackGuard(MIB, *this);
4096 return true;
4097 case X86::XOR64_FP:
4098 case X86::XOR32_FP:
4099 return expandXorFP(MIB, *this);
4100 case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4101 case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4102 case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4103 case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4104 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4105 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4106 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4107 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4108 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4109 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4110 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4111 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4112 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4113 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4114 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
4115 }
4116 return false;
4117 }
4118
4119 /// Return true for all instructions that only update
4120 /// the first 32 or 64-bits of the destination register and leave the rest
4121 /// unmodified. This can be used to avoid folding loads if the instructions
4122 /// only update part of the destination register, and the non-updated part is
4123 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4124 /// instructions breaks the partial register dependency and it can improve
4125 /// performance. e.g.:
4126 ///
4127 /// movss (%rdi), %xmm0
4128 /// cvtss2sd %xmm0, %xmm0
4129 ///
4130 /// Instead of
4131 /// cvtss2sd (%rdi), %xmm0
4132 ///
4133 /// FIXME: This should be turned into a TSFlags.
4134 ///
4135 static bool hasPartialRegUpdate(unsigned Opcode,
4136 const X86Subtarget &Subtarget,
4137 bool ForLoadFold = false) {
4138 switch (Opcode) {
4139 case X86::CVTSI2SSrr:
4140 case X86::CVTSI2SSrm:
4141 case X86::CVTSI642SSrr:
4142 case X86::CVTSI642SSrm:
4143 case X86::CVTSI2SDrr:
4144 case X86::CVTSI2SDrm:
4145 case X86::CVTSI642SDrr:
4146 case X86::CVTSI642SDrm:
4147 // Load folding won't effect the undef register update since the input is
4148 // a GPR.
4149 return !ForLoadFold;
4150 case X86::CVTSD2SSrr:
4151 case X86::CVTSD2SSrm:
4152 case X86::CVTSS2SDrr:
4153 case X86::CVTSS2SDrm:
4154 case X86::MOVHPDrm:
4155 case X86::MOVHPSrm:
4156 case X86::MOVLPDrm:
4157 case X86::MOVLPSrm:
4158 case X86::RCPSSr:
4159 case X86::RCPSSm:
4160 case X86::RCPSSr_Int:
4161 case X86::RCPSSm_Int:
4162 case X86::ROUNDSDr:
4163 case X86::ROUNDSDm:
4164 case X86::ROUNDSSr:
4165 case X86::ROUNDSSm:
4166 case X86::RSQRTSSr:
4167 case X86::RSQRTSSm:
4168 case X86::RSQRTSSr_Int:
4169 case X86::RSQRTSSm_Int:
4170 case X86::SQRTSSr:
4171 case X86::SQRTSSm:
4172 case X86::SQRTSSr_Int:
4173 case X86::SQRTSSm_Int:
4174 case X86::SQRTSDr:
4175 case X86::SQRTSDm:
4176 case X86::SQRTSDr_Int:
4177 case X86::SQRTSDm_Int:
4178 return true;
4179 // GPR
4180 case X86::POPCNT32rm:
4181 case X86::POPCNT32rr:
4182 case X86::POPCNT64rm:
4183 case X86::POPCNT64rr:
4184 return Subtarget.hasPOPCNTFalseDeps();
4185 case X86::LZCNT32rm:
4186 case X86::LZCNT32rr:
4187 case X86::LZCNT64rm:
4188 case X86::LZCNT64rr:
4189 case X86::TZCNT32rm:
4190 case X86::TZCNT32rr:
4191 case X86::TZCNT64rm:
4192 case X86::TZCNT64rr:
4193 return Subtarget.hasLZCNTFalseDeps();
4194 }
4195
4196 return false;
4197 }
4198
4199 /// Inform the BreakFalseDeps pass how many idle
4200 /// instructions we would like before a partial register update.
4201 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4202 const MachineInstr &MI, unsigned OpNum,
4203 const TargetRegisterInfo *TRI) const {
4204 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4205 return 0;
4206
4207 // If MI is marked as reading Reg, the partial register update is wanted.
4208 const MachineOperand &MO = MI.getOperand(0);
4209 unsigned Reg = MO.getReg();
4210 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4211 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4212 return 0;
4213 } else {
4214 if (MI.readsRegister(Reg, TRI))
4215 return 0;
4216 }
4217
4218 // If any instructions in the clearance range are reading Reg, insert a
4219 // dependency breaking instruction, which is inexpensive and is likely to
4220 // be hidden in other instruction's cycles.
4221 return PartialRegUpdateClearance;
4222 }
4223
4224 // Return true for any instruction the copies the high bits of the first source
4225 // operand into the unused high bits of the destination operand.
4226 static bool hasUndefRegUpdate(unsigned Opcode, bool ForLoadFold = false) {
4227 switch (Opcode) {
4228 case X86::VCVTSI2SSrr:
4229 case X86::VCVTSI2SSrm:
4230 case X86::VCVTSI2SSrr_Int:
4231 case X86::VCVTSI2SSrm_Int:
4232 case X86::VCVTSI642SSrr:
4233 case X86::VCVTSI642SSrm:
4234 case X86::VCVTSI642SSrr_Int:
4235 case X86::VCVTSI642SSrm_Int:
4236 case X86::VCVTSI2SDrr:
4237 case X86::VCVTSI2SDrm:
4238 case X86::VCVTSI2SDrr_Int:
4239 case X86::VCVTSI2SDrm_Int:
4240 case X86::VCVTSI642SDrr:
4241 case X86::VCVTSI642SDrm:
4242 case X86::VCVTSI642SDrr_Int:
4243 case X86::VCVTSI642SDrm_Int:
4244 // AVX-512
4245 case X86::VCVTSI2SSZrr:
4246 case X86::VCVTSI2SSZrm:
4247 case X86::VCVTSI2SSZrr_Int:
4248 case X86::VCVTSI2SSZrrb_Int:
4249 case X86::VCVTSI2SSZrm_Int:
4250 case X86::VCVTSI642SSZrr:
4251 case X86::VCVTSI642SSZrm:
4252 case X86::VCVTSI642SSZrr_Int:
4253 case X86::VCVTSI642SSZrrb_Int:
4254 case X86::VCVTSI642SSZrm_Int:
4255 case X86::VCVTSI2SDZrr:
4256 case X86::VCVTSI2SDZrm:
4257 case X86::VCVTSI2SDZrr_Int:
4258 case X86::VCVTSI2SDZrm_Int:
4259 case X86::VCVTSI642SDZrr:
4260 case X86::VCVTSI642SDZrm:
4261 case X86::VCVTSI642SDZrr_Int:
4262 case X86::VCVTSI642SDZrrb_Int:
4263 case X86::VCVTSI642SDZrm_Int:
4264 case X86::VCVTUSI2SSZrr:
4265 case X86::VCVTUSI2SSZrm:
4266 case X86::VCVTUSI2SSZrr_Int:
4267 case X86::VCVTUSI2SSZrrb_Int:
4268 case X86::VCVTUSI2SSZrm_Int:
4269 case X86::VCVTUSI642SSZrr:
4270 case X86::VCVTUSI642SSZrm:
4271 case X86::VCVTUSI642SSZrr_Int:
4272 case X86::VCVTUSI642SSZrrb_Int:
4273 case X86::VCVTUSI642SSZrm_Int:
4274 case X86::VCVTUSI2SDZrr:
4275 case X86::VCVTUSI2SDZrm:
4276 case X86::VCVTUSI2SDZrr_Int:
4277 case X86::VCVTUSI2SDZrm_Int:
4278 case X86::VCVTUSI642SDZrr:
4279 case X86::VCVTUSI642SDZrm:
4280 case X86::VCVTUSI642SDZrr_Int:
4281 case X86::VCVTUSI642SDZrrb_Int:
4282 case X86::VCVTUSI642SDZrm_Int:
4283 // Load folding won't effect the undef register update since the input is
4284 // a GPR.
4285 return !ForLoadFold;
4286 case X86::VCVTSD2SSrr:
4287 case X86::VCVTSD2SSrm:
4288 case X86::VCVTSD2SSrr_Int:
4289 case X86::VCVTSD2SSrm_Int:
4290 case X86::VCVTSS2SDrr:
4291 case X86::VCVTSS2SDrm:
4292 case X86::VCVTSS2SDrr_Int:
4293 case X86::VCVTSS2SDrm_Int:
4294 case X86::VRCPSSr:
4295 case X86::VRCPSSr_Int:
4296 case X86::VRCPSSm:
4297 case X86::VRCPSSm_Int:
4298 case X86::VROUNDSDr:
4299 case X86::VROUNDSDm:
4300 case X86::VROUNDSDr_Int:
4301 case X86::VROUNDSDm_Int:
4302 case X86::VROUNDSSr:
4303 case X86::VROUNDSSm:
4304 case X86::VROUNDSSr_Int:
4305 case X86::VROUNDSSm_Int:
4306 case X86::VRSQRTSSr:
4307 case X86::VRSQRTSSr_Int:
4308 case X86::VRSQRTSSm:
4309 case X86::VRSQRTSSm_Int:
4310 case X86::VSQRTSSr:
4311 case X86::VSQRTSSr_Int:
4312 case X86::VSQRTSSm:
4313 case X86::VSQRTSSm_Int:
4314 case X86::VSQRTSDr:
4315 case X86::VSQRTSDr_Int:
4316 case X86::VSQRTSDm:
4317 case X86::VSQRTSDm_Int:
4318 // AVX-512
4319 case X86::VCVTSD2SSZrr:
4320 case X86::VCVTSD2SSZrr_Int:
4321 case X86::VCVTSD2SSZrrb_Int:
4322 case X86::VCVTSD2SSZrm:
4323 case X86::VCVTSD2SSZrm_Int:
4324 case X86::VCVTSS2SDZrr:
4325 case X86::VCVTSS2SDZrr_Int:
4326 case X86::VCVTSS2SDZrrb_Int:
4327 case X86::VCVTSS2SDZrm:
4328 case X86::VCVTSS2SDZrm_Int:
4329 case X86::VGETEXPSDZr:
4330 case X86::VGETEXPSDZrb:
4331 case X86::VGETEXPSDZm:
4332 case X86::VGETEXPSSZr:
4333 case X86::VGETEXPSSZrb:
4334 case X86::VGETEXPSSZm:
4335 case X86::VGETMANTSDZrri:
4336 case X86::VGETMANTSDZrrib:
4337 case X86::VGETMANTSDZrmi:
4338 case X86::VGETMANTSSZrri:
4339 case X86::VGETMANTSSZrrib:
4340 case X86::VGETMANTSSZrmi:
4341 case X86::VRNDSCALESDZr:
4342 case X86::VRNDSCALESDZr_Int:
4343 case X86::VRNDSCALESDZrb_Int:
4344 case X86::VRNDSCALESDZm:
4345 case X86::VRNDSCALESDZm_Int:
4346 case X86::VRNDSCALESSZr:
4347 case X86::VRNDSCALESSZr_Int:
4348 case X86::VRNDSCALESSZrb_Int:
4349 case X86::VRNDSCALESSZm:
4350 case X86::VRNDSCALESSZm_Int:
4351 case X86::VRCP14SDZrr:
4352 case X86::VRCP14SDZrm:
4353 case X86::VRCP14SSZrr:
4354 case X86::VRCP14SSZrm:
4355 case X86::VRCP28SDZr:
4356 case X86::VRCP28SDZrb:
4357 case X86::VRCP28SDZm:
4358 case X86::VRCP28SSZr:
4359 case X86::VRCP28SSZrb:
4360 case X86::VRCP28SSZm:
4361 case X86::VREDUCESSZrmi:
4362 case X86::VREDUCESSZrri:
4363 case X86::VREDUCESSZrrib:
4364 case X86::VRSQRT14SDZrr:
4365 case X86::VRSQRT14SDZrm:
4366 case X86::VRSQRT14SSZrr:
4367 case X86::VRSQRT14SSZrm:
4368 case X86::VRSQRT28SDZr:
4369 case X86::VRSQRT28SDZrb:
4370 case X86::VRSQRT28SDZm:
4371 case X86::VRSQRT28SSZr:
4372 case X86::VRSQRT28SSZrb:
4373 case X86::VRSQRT28SSZm:
4374 case X86::VSQRTSSZr:
4375 case X86::VSQRTSSZr_Int:
4376 case X86::VSQRTSSZrb_Int:
4377 case X86::VSQRTSSZm:
4378 case X86::VSQRTSSZm_Int:
4379 case X86::VSQRTSDZr:
4380 case X86::VSQRTSDZr_Int:
4381 case X86::VSQRTSDZrb_Int:
4382 case X86::VSQRTSDZm:
4383 case X86::VSQRTSDZm_Int:
4384 return true;
4385 }
4386
4387 return false;
4388 }
4389
4390 /// Inform the BreakFalseDeps pass how many idle instructions we would like
4391 /// before certain undef register reads.
4392 ///
4393 /// This catches the VCVTSI2SD family of instructions:
4394 ///
4395 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
4396 ///
4397 /// We should to be careful *not* to catch VXOR idioms which are presumably
4398 /// handled specially in the pipeline:
4399 ///
4400 /// vxorps undef %xmm1, undef %xmm1, %xmm1
4401 ///
4402 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4403 /// high bits that are passed-through are not live.
4404 unsigned
4405 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
4406 const TargetRegisterInfo *TRI) const {
4407 if (!hasUndefRegUpdate(MI.getOpcode()))
4408 return 0;
4409
4410 // Set the OpNum parameter to the first source operand.
4411 OpNum = 1;
4412
4413 const MachineOperand &MO = MI.getOperand(OpNum);
4414 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4415 return UndefRegClearance;
4416 }
4417 return 0;
4418 }
4419
4420 void X86InstrInfo::breakPartialRegDependency(
4421 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4422 unsigned Reg = MI.getOperand(OpNum).getReg();
4423 // If MI kills this register, the false dependence is already broken.
4424 if (MI.killsRegister(Reg, TRI))
4425 return;
4426
4427 if (X86::VR128RegClass.contains(Reg)) {
4428 // These instructions are all floating point domain, so xorps is the best
4429 // choice.
4430 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
4431 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4432 .addReg(Reg, RegState::Undef)
4433 .addReg(Reg, RegState::Undef);
4434 MI.addRegisterKilled(Reg, TRI, true);
4435 } else if (X86::VR256RegClass.contains(Reg)) {
4436 // Use vxorps to clear the full ymm register.
4437 // It wants to read and write the xmm sub-register.
4438 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4439 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4440 .addReg(XReg, RegState::Undef)
4441 .addReg(XReg, RegState::Undef)
4442 .addReg(Reg, RegState::ImplicitDefine);
4443 MI.addRegisterKilled(Reg, TRI, true);
4444 } else if (X86::GR64RegClass.contains(Reg)) {
4445 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
4446 // as well.
4447 unsigned XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4448 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4449 .addReg(XReg, RegState::Undef)
4450 .addReg(XReg, RegState::Undef)
4451 .addReg(Reg, RegState::ImplicitDefine);
4452 MI.addRegisterKilled(Reg, TRI, true);
4453 } else if (X86::GR32RegClass.contains(Reg)) {
4454 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4455 .addReg(Reg, RegState::Undef)
4456 .addReg(Reg, RegState::Undef);
4457 MI.addRegisterKilled(Reg, TRI, true);
4458 }
4459 }
4460
4461 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
4462 int PtrOffset = 0) {
4463 unsigned NumAddrOps = MOs.size();
4464
4465 if (NumAddrOps < 4) {
4466 // FrameIndex only - add an immediate offset (whether its zero or not).
4467 for (unsigned i = 0; i != NumAddrOps; ++i)
4468 MIB.add(MOs[i]);
4469 addOffset(MIB, PtrOffset);
4470 } else {
4471 // General Memory Addressing - we need to add any offset to an existing
4472 // offset.
4473 assert(MOs.size() == 5 && "Unexpected memory operand list length");
4474 for (unsigned i = 0; i != NumAddrOps; ++i) {
4475 const MachineOperand &MO = MOs[i];
4476 if (i == 3 && PtrOffset != 0) {
4477 MIB.addDisp(MO, PtrOffset);
4478 } else {
4479 MIB.add(MO);
4480 }
4481 }
4482 }
4483 }
4484
4485 static void updateOperandRegConstraints(MachineFunction &MF,
4486 MachineInstr &NewMI,
4487 const TargetInstrInfo &TII) {
4488 MachineRegisterInfo &MRI = MF.getRegInfo();
4489 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4490
4491 for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
4492 MachineOperand &MO = NewMI.getOperand(Idx);
4493 // We only need to update constraints on virtual register operands.
4494 if (!MO.isReg())
4495 continue;
4496 unsigned Reg = MO.getReg();
4497 if (!TRI.isVirtualRegister(Reg))
4498 continue;
4499
4500 auto *NewRC = MRI.constrainRegClass(
4501 Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
4502 if (!NewRC) {
4503 LLVM_DEBUG(
4504 dbgs() << "WARNING: Unable to update register constraint for operand "
4505 << Idx << " of instruction:\n";
4506 NewMI.dump(); dbgs() << "\n");
4507 }
4508 }
4509 }
4510
4511 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4512 ArrayRef<MachineOperand> MOs,
4513 MachineBasicBlock::iterator InsertPt,
4514 MachineInstr &MI,
4515 const TargetInstrInfo &TII) {
4516 // Create the base instruction with the memory operand as the first part.
4517 // Omit the implicit operands, something BuildMI can't do.
4518 MachineInstr *NewMI =
4519 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4520 MachineInstrBuilder MIB(MF, NewMI);
4521 addOperands(MIB, MOs);
4522
4523 // Loop over the rest of the ri operands, converting them over.
4524 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
4525 for (unsigned i = 0; i != NumOps; ++i) {
4526 MachineOperand &MO = MI.getOperand(i + 2);
4527 MIB.add(MO);
4528 }
4529 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
4530 MachineOperand &MO = MI.getOperand(i);
4531 MIB.add(MO);
4532 }
4533
4534 updateOperandRegConstraints(MF, *NewMI, TII);
4535
4536 MachineBasicBlock *MBB = InsertPt->getParent();
4537 MBB->insert(InsertPt, NewMI);
4538
4539 return MIB;
4540 }
4541
4542 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4543 unsigned OpNo, ArrayRef<MachineOperand> MOs,
4544 MachineBasicBlock::iterator InsertPt,
4545 MachineInstr &MI, const TargetInstrInfo &TII,
4546 int PtrOffset = 0) {
4547 // Omit the implicit operands, something BuildMI can't do.
4548 MachineInstr *NewMI =
4549 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4550 MachineInstrBuilder MIB(MF, NewMI);
4551
4552 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4553 MachineOperand &MO = MI.getOperand(i);
4554 if (i == OpNo) {
4555 assert(MO.isReg() && "Expected to fold into reg operand!");
4556 addOperands(MIB, MOs, PtrOffset);
4557 } else {
4558 MIB.add(MO);
4559 }
4560 }
4561
4562 updateOperandRegConstraints(MF, *NewMI, TII);
4563
4564 MachineBasicBlock *MBB = InsertPt->getParent();
4565 MBB->insert(InsertPt, NewMI);
4566
4567 return MIB;
4568 }
4569
4570 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4571 ArrayRef<MachineOperand> MOs,
4572 MachineBasicBlock::iterator InsertPt,
4573 MachineInstr &MI) {
4574 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4575 MI.getDebugLoc(), TII.get(Opcode));
4576 addOperands(MIB, MOs);
4577 return MIB.addImm(0);
4578 }
4579
4580 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
4581 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4582 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4583 unsigned Size, unsigned Align) const {
4584 switch (MI.getOpcode()) {
4585 case X86::INSERTPSrr:
4586 case X86::VINSERTPSrr:
4587 case X86::VINSERTPSZrr:
4588 // Attempt to convert the load of inserted vector into a fold load
4589 // of a single float.
4590 if (OpNum == 2) {
4591 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4592 unsigned ZMask = Imm & 15;
4593 unsigned DstIdx = (Imm >> 4) & 3;
4594 unsigned SrcIdx = (Imm >> 6) & 3;
4595
4596 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4597 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4598 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4599 if ((Size == 0 || Size >= 16) && RCSize >= 16 && 4 <= Align) {
4600 int PtrOffset = SrcIdx * 4;
4601 unsigned NewImm = (DstIdx << 4) | ZMask;
4602 unsigned NewOpCode =
4603 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
4604 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
4605 X86::INSERTPSrm;
4606 MachineInstr *NewMI =
4607 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
4608 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4609 return NewMI;
4610 }
4611 }
4612 break;
4613 case X86::MOVHLPSrr:
4614 case X86::VMOVHLPSrr:
4615 case X86::VMOVHLPSZrr:
4616 // Move the upper 64-bits of the second operand to the lower 64-bits.
4617 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
4618 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
4619 if (OpNum == 2) {
4620 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4621 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4622 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4623 if ((Size == 0 || Size >= 16) && RCSize >= 16 && 8 <= Align) {
4624 unsigned NewOpCode =
4625 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
4626 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
4627 X86::MOVLPSrm;
4628 MachineInstr *NewMI =
4629 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
4630 return NewMI;
4631 }
4632 }
4633 break;
4634 case X86::UNPCKLPDrr:
4635 // If we won't be able to fold this to the memory form of UNPCKL, use
4636 // MOVHPD instead. Done as custom because we can't have this in the load
4637 // table twice.
4638 if (OpNum == 2) {
4639 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4640 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4641 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4642 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Align < 16) {
4643 MachineInstr *NewMI =
4644 FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this, 8);
4645 return NewMI;
4646 }
4647 }
4648 break;
4649 }
4650
4651 return nullptr;
4652 }
4653
4654 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
4655 MachineInstr &MI) {
4656 if (!hasUndefRegUpdate(MI.getOpcode(), /*ForLoadFold*/true) ||
4657 !MI.getOperand(1).isReg())
4658 return false;
4659
4660 // The are two cases we need to handle depending on where in the pipeline
4661 // the folding attempt is being made.
4662 // -Register has the undef flag set.
4663 // -Register is produced by the IMPLICIT_DEF instruction.
4664
4665 if (MI.getOperand(1).isUndef())
4666 return true;
4667
4668 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4669 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4670 return VRegDef && VRegDef->isImplicitDef();
4671 }
4672
4673
4674 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4675 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4676 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4677 unsigned Size, unsigned Align, bool AllowCommute) const {
4678 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
4679 bool isTwoAddrFold = false;
4680
4681 // For CPUs that favor the register form of a call or push,
4682 // do not fold loads into calls or pushes, unless optimizing for size
4683 // aggressively.
4684 if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
4685 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
4686 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
4687 MI.getOpcode() == X86::PUSH64r))
4688 return nullptr;
4689
4690 // Avoid partial and undef register update stalls unless optimizing for size.
4691 if (!MF.getFunction().hasOptSize() &&
4692 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4693 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4694 return nullptr;
4695
4696 unsigned NumOps = MI.getDesc().getNumOperands();
4697 bool isTwoAddr =
4698 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4699
4700 // FIXME: AsmPrinter doesn't know how to handle
4701 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4702 if (MI.getOpcode() == X86::ADD32ri &&
4703 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4704 return nullptr;
4705
4706 // GOTTPOFF relocation loads can only be folded into add instructions.
4707 // FIXME: Need to exclude other relocations that only support specific
4708 // instructions.
4709 if (MOs.size() == X86::AddrNumOperands &&
4710 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
4711 MI.getOpcode() != X86::ADD64rr)
4712 return nullptr;
4713
4714 MachineInstr *NewMI = nullptr;
4715
4716 // Attempt to fold any custom cases we have.
4717 if (MachineInstr *CustomMI =
4718 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
4719 return CustomMI;
4720
4721 const X86MemoryFoldTableEntry *I = nullptr;
4722
4723 // Folding a memory location into the two-address part of a two-address
4724 // instruction is different than folding it other places. It requires
4725 // replacing the *two* registers with the memory location.
4726 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4727 MI.getOperand(1).isReg() &&
4728 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4729 I = lookupTwoAddrFoldTable(MI.getOpcode());
4730 isTwoAddrFold = true;
4731 } else {
4732 if (OpNum == 0) {
4733 if (MI.getOpcode() == X86::MOV32r0) {
4734 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4735 if (NewMI)
4736 return NewMI;
4737 }
4738 }
4739
4740 I = lookupFoldTable(MI.getOpcode(), OpNum);
4741 }
4742
4743 if (I != nullptr) {
4744 unsigned Opcode = I->DstOp;
4745 unsigned MinAlign = (I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4746 if (Align < MinAlign)
4747 return nullptr;
4748 bool NarrowToMOV32rm = false;
4749 if (Size) {
4750 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4751 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
4752 &RI, MF);
4753 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4754 if (Size < RCSize) {
4755 // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
4756 // Check if it's safe to fold the load. If the size of the object is
4757 // narrower than the load width, then it's not.
4758 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4759 return nullptr;
4760 // If this is a 64-bit load, but the spill slot is 32, then we can do
4761 // a 32-bit load which is implicitly zero-extended. This likely is
4762 // due to live interval analysis remat'ing a load from stack slot.
4763 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4764 return nullptr;
4765 Opcode = X86::MOV32rm;
4766 NarrowToMOV32rm = true;
4767 }
4768 }
4769
4770 if (isTwoAddrFold)
4771 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4772 else
4773 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4774
4775 if (NarrowToMOV32rm) {
4776 // If this is the special case where we use a MOV32rm to load a 32-bit
4777 // value and zero-extend the top bits. Change the destination register
4778 // to a 32-bit one.
4779 unsigned DstReg = NewMI->getOperand(0).getReg();
4780 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4781 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4782 else
4783 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4784 }
4785 return NewMI;
4786 }
4787
4788 // If the instruction and target operand are commutable, commute the
4789 // instruction and try again.
4790 if (AllowCommute) {
4791 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
4792 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4793 bool HasDef = MI.getDesc().getNumDefs();
4794 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
4795 Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4796 Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
4797 bool Tied1 =
4798 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4799 bool Tied2 =
4800 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4801
4802 // If either of the commutable operands are tied to the destination
4803 // then we can not commute + fold.
4804 if ((HasDef && Reg0 == Reg1 && Tied1) ||
4805 (HasDef && Reg0 == Reg2 && Tied2))
4806 return nullptr;
4807
4808 MachineInstr *CommutedMI =
4809 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4810 if (!CommutedMI) {
4811 // Unable to commute.
4812 return nullptr;
4813 }
4814 if (CommutedMI != &MI) {
4815 // New instruction. We can't fold from this.
4816 CommutedMI->eraseFromParent();
4817 return nullptr;
4818 }
4819
4820 // Attempt to fold with the commuted version of the instruction.
4821 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
4822 Size, Align, /*AllowCommute=*/false);
4823 if (NewMI)
4824 return NewMI;
4825
4826 // Folding failed again - undo the commute before returning.
4827 MachineInstr *UncommutedMI =
4828 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4829 if (!UncommutedMI) {
4830 // Unable to commute.
4831 return nullptr;
4832 }
4833 if (UncommutedMI != &MI) {
4834 // New instruction. It doesn't need to be kept.
4835 UncommutedMI->eraseFromParent();
4836 return nullptr;
4837 }
4838
4839 // Return here to prevent duplicate fuse failure report.
4840 return nullptr;
4841 }
4842 }
4843
4844 // No fusion
4845 if (PrintFailedFusing && !MI.isCopy())
4846 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
4847 return nullptr;
4848 }
4849
4850 MachineInstr *
4851 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
4852 ArrayRef<unsigned> Ops,
4853 MachineBasicBlock::iterator InsertPt,
4854 int FrameIndex, LiveIntervals *LIS,
4855 VirtRegMap *VRM) const {
4856 // Check switch flag
4857 if (NoFusing)
4858 return nullptr;
4859
4860 // Avoid partial and undef register update stalls unless optimizing for size.
4861 if (!MF.getFunction().hasOptSize() &&
4862 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4863 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4864 return nullptr;
4865
4866 // Don't fold subreg spills, or reloads that use a high subreg.
4867 for (auto Op : Ops) {
4868 MachineOperand &MO = MI.getOperand(Op);
4869 auto SubReg = MO.getSubReg();
4870 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
4871 return nullptr;
4872 }
4873
4874 const MachineFrameInfo &MFI = MF.getFrameInfo();
4875 unsigned Size = MFI.getObjectSize(FrameIndex);
4876 unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
4877 // If the function stack isn't realigned we don't want to fold instructions
4878 // that need increased alignment.
4879 if (!RI.needsStackRealignment(MF))
4880 Alignment =
4881 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
4882 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4883 unsigned NewOpc = 0;
4884 unsigned RCSize = 0;
4885 switch (MI.getOpcode()) {
4886 default: return nullptr;
4887 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
4888 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4889 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4890 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4891 }
4892 // Check if it's safe to fold the load. If the size of the object is
4893 // narrower than the load width, then it's not.
4894 if (Size < RCSize)
4895 return nullptr;
4896 // Change to CMPXXri r, 0 first.
4897 MI.setDesc(get(NewOpc));
4898 MI.getOperand(1).ChangeToImmediate(0);
4899 } else if (Ops.size() != 1)
4900 return nullptr;
4901
4902 return foldMemoryOperandImpl(MF, MI, Ops[0],
4903 MachineOperand::CreateFI(FrameIndex), InsertPt,
4904 Size, Alignment, /*AllowCommute=*/true);
4905 }
4906
4907 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
4908 /// because the latter uses contents that wouldn't be defined in the folded
4909 /// version. For instance, this transformation isn't legal:
4910 /// movss (%rdi), %xmm0
4911 /// addps %xmm0, %xmm0
4912 /// ->
4913 /// addps (%rdi), %xmm0
4914 ///
4915 /// But this one is:
4916 /// movss (%rdi), %xmm0
4917 /// addss %xmm0, %xmm0
4918 /// ->
4919 /// addss (%rdi), %xmm0
4920 ///
4921 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
4922 const MachineInstr &UserMI,
4923 const MachineFunction &MF) {
4924 unsigned Opc = LoadMI.getOpcode();
4925 unsigned UserOpc = UserMI.getOpcode();
4926 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4927 const TargetRegisterClass *RC =
4928 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
4929 unsigned RegSize = TRI.getRegSizeInBits(*RC);
4930
4931 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
4932 Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
4933 Opc == X86::VMOVSSZrm_alt) &&
4934 RegSize > 32) {
4935 // These instructions only load 32 bits, we can't fold them if the
4936 // destination register is wider than 32 bits (4 bytes), and its user
4937 // instruction isn't scalar (SS).
4938 switch (UserOpc) {
4939 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
4940 case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
4941 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
4942 case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
4943 case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
4944 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
4945 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
4946 case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
4947 case X86::VCMPSSZrr_Intk:
4948 case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
4949 case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
4950 case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
4951 case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
4952 case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
4953 case X86::VFMADDSS4rr_Int: case X86::VFNMADDSS4rr_Int:
4954 case X86::VFMSUBSS4rr_Int: case X86::VFNMSUBSS4rr_Int:
4955 case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
4956 case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
4957 case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
4958 case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
4959 case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
4960 case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
4961 case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
4962 case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
4963 case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
4964 case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
4965 case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
4966 case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
4967 case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
4968 case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
4969 case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
4970 case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
4971 case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
4972 case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
4973 case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
4974 case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
4975 case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
4976 case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
4977 case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
4978 case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
4979 return false;
4980 default:
4981 return true;
4982 }
4983 }
4984
4985 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
4986 Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
4987 Opc == X86::VMOVSDZrm_alt) &&
4988 RegSize > 64) {
4989 // These instructions only load 64 bits, we can't fold them if the
4990 // destination register is wider than 64 bits (8 bytes), and its user
4991 // instruction isn't scalar (SD).
4992 switch (UserOpc) {
4993 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
4994 case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
4995 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
4996 case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
4997 case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
4998 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
4999 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5000 case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5001 case X86::VCMPSDZrr_Intk:
5002 case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5003 case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5004 case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5005 case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5006 case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5007 case X86::VFMADDSD4rr_Int: case X86::VFNMADDSD4rr_Int:
5008 case X86::VFMSUBSD4rr_Int: case X86::VFNMSUBSD4rr_Int:
5009 case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
5010 case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
5011 case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
5012 case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
5013 case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
5014 case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
5015 case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5016 case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5017 case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5018 case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5019 case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5020 case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5021 case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5022 case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5023 case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5024 case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5025 case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5026 case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5027 case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5028 case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5029 case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5030 case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5031 case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5032 case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5033 return false;
5034 default:
5035 return true;
5036 }
5037 }
5038
5039 return false;
5040 }
5041
5042 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5043 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5044 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5045 LiveIntervals *LIS) const {
5046
5047 // TODO: Support the case where LoadMI loads a wide register, but MI
5048 // only uses a subreg.
5049 for (auto Op : Ops) {
5050 if (MI.getOperand(Op).getSubReg())
5051 return nullptr;
5052 }
5053
5054 // If loading from a FrameIndex, fold directly from the FrameIndex.
5055 unsigned NumOps = LoadMI.getDesc().getNumOperands();
5056 int FrameIndex;
5057 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5058 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5059 return nullptr;
5060 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5061 }
5062
5063 // Check switch flag
5064 if (NoFusing) return nullptr;
5065
5066 // Avoid partial and undef register update stalls unless optimizing for size.
5067 if (!MF.getFunction().hasOptSize() &&
5068 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5069 shouldPreventUndefRegUpdateMemFold(MF, MI)))
5070 return nullptr;
5071
5072 // Determine the alignment of the load.
5073 unsigned Alignment = 0;
5074 if (LoadMI.hasOneMemOperand())
5075 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
5076 else
5077 switch (LoadMI.getOpcode()) {
5078 case X86::AVX512_512_SET0:
5079 case X86::AVX512_512_SETALLONES:
5080 Alignment = 64;
5081 break;
5082 case X86::AVX2_SETALLONES:
5083 case X86::AVX1_SETALLONES:
5084 case X86::AVX_SET0:
5085 case X86::AVX512_256_SET0:
5086 Alignment = 32;
5087 break;
5088 case X86::V_SET0:
5089 case X86::V_SETALLONES:
5090 case X86::AVX512_128_SET0:
5091 Alignment = 16;
5092 break;
5093 case X86::MMX_SET0:
5094 case X86::FsFLD0SD:
5095 case X86::AVX512_FsFLD0SD:
5096 Alignment = 8;
5097 break;
5098 case X86::FsFLD0SS:
5099 case X86::AVX512_FsFLD0SS:
5100 Alignment = 4;
5101 break;
5102 default:
5103 return nullptr;
5104 }
5105 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5106 unsigned NewOpc = 0;
5107 switch (MI.getOpcode()) {
5108 default: return nullptr;
5109 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
5110 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5111 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5112 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5113 }
5114 // Change to CMPXXri r, 0 first.
5115 MI.setDesc(get(NewOpc));
5116 MI.getOperand(1).ChangeToImmediate(0);
5117 } else if (Ops.size() != 1)
5118 return nullptr;
5119
5120 // Make sure the subregisters match.
5121 // Otherwise we risk changing the size of the load.
5122 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5123 return nullptr;
5124
5125 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5126 switch (LoadMI.getOpcode()) {
5127 case X86::MMX_SET0:
5128 case X86::V_SET0:
5129 case X86::V_SETALLONES:
5130 case X86::AVX2_SETALLONES:
5131 case X86::AVX1_SETALLONES:
5132 case X86::AVX_SET0:
5133 case X86::AVX512_128_SET0:
5134 case X86::AVX512_256_SET0:
5135 case X86::AVX512_512_SET0:
5136 case X86::AVX512_512_SETALLONES:
5137 case X86::FsFLD0SD:
5138 case X86::AVX512_FsFLD0SD:
5139 case X86::FsFLD0SS:
5140 case X86::AVX512_FsFLD0SS: {
5141 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5142 // Create a constant-pool entry and operands to load from it.
5143
5144 // Medium and large mode can't fold loads this way.
5145 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5146 MF.getTarget().getCodeModel() != CodeModel::Kernel)
5147 return nullptr;
5148
5149 // x86-32 PIC requires a PIC base register for constant pools.
5150 unsigned PICBase = 0;
5151 if (MF.getTarget().isPositionIndependent()) {
5152 if (Subtarget.is64Bit())
5153 PICBase = X86::RIP;
5154 else
5155 // FIXME: PICBase = getGlobalBaseReg(&MF);
5156 // This doesn't work for several reasons.
5157 // 1. GlobalBaseReg may have been spilled.
5158 // 2. It may not be live at MI.
5159 return nullptr;
5160 }
5161
5162 // Create a constant-pool entry.
5163 MachineConstantPool &MCP = *MF.getConstantPool();
5164 Type *Ty;
5165 unsigned Opc = LoadMI.getOpcode();
5166 if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5167 Ty = Type::getFloatTy(MF.getFunction().getContext());
5168 else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5169 Ty = Type::getDoubleTy(MF.getFunction().getContext());
5170 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5171 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);
5172 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5173 Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5174 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8);
5175 else if (Opc == X86::MMX_SET0)
5176 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 2);
5177 else
5178 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4);
5179
5180 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5181 Opc == X86::AVX512_512_SETALLONES ||
5182 Opc == X86::AVX1_SETALLONES);
5183 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5184 Constant::getNullValue(Ty);
5185 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5186
5187 // Create operands to load from the constant pool entry.
5188 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5189 MOs.push_back(MachineOperand::CreateImm(1));
5190 MOs.push_back(MachineOperand::CreateReg(0, false));
5191 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5192 MOs.push_back(MachineOperand::CreateReg(0, false));
5193 break;
5194 }
5195 default: {
5196 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5197 return nullptr;
5198
5199 // Folding a normal load. Just copy the load's address operands.
5200 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5201 LoadMI.operands_begin() + NumOps);
5202 break;
5203 }
5204 }
5205 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5206 /*Size=*/0, Alignment, /*AllowCommute=*/true);
5207 }
5208
5209 static SmallVector<MachineMemOperand *, 2>
5210 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5211 SmallVector<MachineMemOperand *, 2> LoadMMOs;
5212
5213 for (MachineMemOperand *MMO : MMOs) {
5214 if (!MMO->isLoad())
5215 continue;
5216
5217 if (!MMO->isStore()) {
5218 // Reuse the MMO.
5219 LoadMMOs.push_back(MMO);
5220 } else {
5221 // Clone the MMO and unset the store flag.
5222 LoadMMOs.push_back(MF.getMachineMemOperand(
5223 MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
5224 }
5225 }
5226
5227 return LoadMMOs;
5228 }
5229
5230 static SmallVector<MachineMemOperand *, 2>
5231 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5232 SmallVector<MachineMemOperand *, 2> StoreMMOs;
5233
5234 for (MachineMemOperand *MMO : MMOs) {
5235 if (!MMO->isStore())
5236 continue;
5237
5238 if (!MMO->isLoad()) {
5239 // Reuse the MMO.
5240 StoreMMOs.push_back(MMO);
5241 } else {
5242 // Clone the MMO and unset the load flag.
5243 StoreMMOs.push_back(MF.getMachineMemOperand(
5244 MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
5245 }
5246 }
5247
5248 return StoreMMOs;
5249 }
5250
5251 bool X86InstrInfo::unfoldMemoryOperand(
5252 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
5253 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
5254 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
5255 if (I == nullptr)
5256 return false;
5257 unsigned Opc = I->DstOp;
5258 unsigned Index = I->Flags & TB_INDEX_MASK;
5259 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5260 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5261 if (UnfoldLoad && !FoldedLoad)
5262 return false;
5263 UnfoldLoad &= FoldedLoad;
5264 if (UnfoldStore && !FoldedStore)
5265 return false;
5266 UnfoldStore &= FoldedStore;
5267
5268 const MCInstrDesc &MCID = get(Opc);
5269 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5270 // TODO: Check if 32-byte or greater accesses are slow too?
5271 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
5272 Subtarget.isUnalignedMem16Slow())
5273 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5274 // conservatively assume the address is unaligned. That's bad for
5275 // performance.
5276 return false;
5277 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5278 SmallVector<MachineOperand,2> BeforeOps;
5279 SmallVector<MachineOperand,2> AfterOps;
5280 SmallVector<MachineOperand,4> ImpOps;
5281 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5282 MachineOperand &Op = MI.getOperand(i);
5283 if (i >= Index && i < Index + X86::AddrNumOperands)
5284 AddrOps.push_back(Op);
5285 else if (Op.isReg() && Op.isImplicit())
5286 ImpOps.push_back(Op);
5287 else if (i < Index)
5288 BeforeOps.push_back(Op);
5289 else if (i > Index)
5290 AfterOps.push_back(Op);
5291 }
5292
5293 // Emit the load instruction.
5294 if (UnfoldLoad) {
5295 auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
5296 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs, NewMIs);
5297 if (UnfoldStore) {
5298 // Address operands cannot be marked isKill.
5299 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5300 MachineOperand &MO = NewMIs[0]->getOperand(i);
5301 if (MO.isReg())
5302 MO.setIsKill(false);
5303 }
5304 }
5305 }
5306
5307 // Emit the data processing instruction.
5308 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
5309 MachineInstrBuilder MIB(MF, DataMI);
5310
5311 if (FoldedStore)
5312 MIB.addReg(Reg, RegState::Define);
5313 for (MachineOperand &BeforeOp : BeforeOps)
5314 MIB.add(BeforeOp);
5315 if (FoldedLoad)
5316 MIB.addReg(Reg);
5317 for (MachineOperand &AfterOp : AfterOps)
5318 MIB.add(AfterOp);
5319 for (MachineOperand &ImpOp : ImpOps) {
5320 MIB.addReg(ImpOp.getReg(),
5321 getDefRegState(ImpOp.isDef()) |
5322 RegState::Implicit |
5323 getKillRegState(ImpOp.isKill()) |
5324 getDeadRegState(ImpOp.isDead()) |
5325 getUndefRegState(ImpOp.isUndef()));
5326 }
5327 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5328 switch (DataMI->getOpcode()) {
5329 default: break;
5330 case X86::CMP64ri32:
5331 case X86::CMP64ri8:
5332 case X86::CMP32ri:
5333 case X86::CMP32ri8:
5334 case X86::CMP16ri:
5335 case X86::CMP16ri8:
5336 case X86::CMP8ri: {
5337 MachineOperand &MO0 = DataMI->getOperand(0);
5338 MachineOperand &MO1 = DataMI->getOperand(1);
5339 if (MO1.getImm() == 0) {
5340 unsigned NewOpc;
5341 switch (DataMI->getOpcode()) {
5342 default: llvm_unreachable("Unreachable!");
5343 case X86::CMP64ri8:
5344 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5345 case X86::CMP32ri8:
5346 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
5347 case X86::CMP16ri8:
5348 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5349 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5350 }
5351 DataMI->setDesc(get(NewOpc));
5352 MO1.ChangeToRegister(MO0.getReg(), false);
5353 }
5354 }
5355 }
5356 NewMIs.push_back(DataMI);
5357
5358 // Emit the store instruction.
5359 if (UnfoldStore) {
5360 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5361 auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
5362 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs, NewMIs);
5363 }
5364
5365 return true;
5366 }
5367
5368 bool
5369 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5370 SmallVectorImpl<SDNode*> &NewNodes) const {
5371 if (!N->isMachineOpcode())
5372 return false;
5373
5374 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
5375 if (I == nullptr)
5376 return false;
5377 unsigned Opc = I->DstOp;
5378 unsigned Index = I->Flags & TB_INDEX_MASK;
5379 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5380 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5381 const MCInstrDesc &MCID = get(Opc);
5382 MachineFunction &MF = DAG.getMachineFunction();
5383 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5384 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5385 unsigned NumDefs = MCID.NumDefs;
5386 std::vector<SDValue> AddrOps;
5387 std::vector<SDValue> BeforeOps;
5388 std::vector<SDValue> AfterOps;
5389 SDLoc dl(N);
5390 unsigned NumOps = N->getNumOperands();
5391 for (unsigned i = 0; i != NumOps-1; ++i) {
5392 SDValue Op = N->getOperand(i);
5393 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5394 AddrOps.push_back(Op);
5395 else if (i < Index-NumDefs)
5396 BeforeOps.push_back(Op);
5397 else if (i > Index-NumDefs)
5398 AfterOps.push_back(Op);
5399 }
5400 SDValue Chain = N->getOperand(NumOps-1);
5401 AddrOps.push_back(Chain);
5402
5403 // Emit the load instruction.
5404 SDNode *Load = nullptr;
5405 if (FoldedLoad) {
5406 EVT VT = *TRI.legalclasstypes_begin(*RC);
5407 auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5408 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5409 Subtarget.isUnalignedMem16Slow())
5410 // Do not introduce a slow unaligned load.
5411 return false;
5412 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5413 // memory access is slow above.
5414 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5415 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5416 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5417 VT, MVT::Other, AddrOps);
5418 NewNodes.push_back(Load);
5419
5420 // Preserve memory reference information.
5421 DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
5422 }
5423
5424 // Emit the data processing instruction.
5425 std::vector<EVT> VTs;
5426 const TargetRegisterClass *DstRC = nullptr;
5427 if (MCID.getNumDefs() > 0) {
5428 DstRC = getRegClass(MCID, 0, &RI, MF);
5429 VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
5430 }
5431 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5432 EVT VT = N->getValueType(i);
5433 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5434 VTs.push_back(VT);
5435 }
5436 if (Load)
5437 BeforeOps.push_back(SDValue(Load, 0));
5438 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5439 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5440 switch (Opc) {
5441 default: break;
5442 case X86::CMP64ri32:
5443 case X86::CMP64ri8:
5444 case X86::CMP32ri:
5445 case X86::CMP32ri8:
5446 case X86::CMP16ri:
5447 case X86::CMP16ri8:
5448 case X86::CMP8ri:
5449 if (isNullConstant(BeforeOps[1])) {
5450 switch (Opc) {
5451 default: llvm_unreachable("Unreachable!");
5452 case X86::CMP64ri8:
5453 case X86::CMP64ri32: Opc = X86::TEST64rr; break;
5454 case X86::CMP32ri8:
5455 case X86::CMP32ri: Opc = X86::TEST32rr; break;
5456 case X86::CMP16ri8:
5457 case X86::CMP16ri: Opc = X86::TEST16rr; break;
5458 case X86::CMP8ri: Opc = X86::TEST8rr; break;
5459 }
5460 BeforeOps[1] = BeforeOps[0];
5461 }
5462 }
5463 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5464 NewNodes.push_back(NewNode);
5465
5466 // Emit the store instruction.
5467 if (FoldedStore) {
5468 AddrOps.pop_back();
5469 AddrOps.push_back(SDValue(NewNode, 0));
5470 AddrOps.push_back(Chain);
5471 auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5472 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5473 Subtarget.isUnalignedMem16Slow())
5474 // Do not introduce a slow unaligned store.
5475 return false;
5476 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5477 // memory access is slow above.
5478 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5479 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5480 SDNode *Store =
5481 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5482 dl, MVT::Other, AddrOps);
5483 NewNodes.push_back(Store);
5484
5485 // Preserve memory reference information.
5486 DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
5487 }
5488
5489 return true;
5490 }
5491
5492 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5493 bool UnfoldLoad, bool UnfoldStore,
5494 unsigned *LoadRegIndex) const {
5495 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
5496 if (I == nullptr)
5497 return 0;
5498 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5499 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5500 if (UnfoldLoad && !FoldedLoad)
5501 return 0;
5502 if (UnfoldStore && !FoldedStore)
5503 return 0;
5504 if (LoadRegIndex)
5505 *LoadRegIndex = I->Flags & TB_INDEX_MASK;
5506 return I->DstOp;
5507 }
5508
5509 bool
5510 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5511 int64_t &Offset1, int64_t &Offset2) const {
5512 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5513 return false;
5514 unsigned Opc1 = Load1->getMachineOpcode();
5515 unsigned Opc2 = Load2->getMachineOpcode();
5516 switch (Opc1) {
5517 default: return false;
5518 case X86::MOV8rm:
5519 case X86::MOV16rm:
5520 case X86::MOV32rm:
5521 case X86::MOV64rm:
5522 case X86::LD_Fp32m:
5523 case X86::LD_Fp64m:
5524 case X86::LD_Fp80m:
5525 case X86::MOVSSrm:
5526 case X86::MOVSSrm_alt:
5527 case X86::MOVSDrm:
5528 case X86::MOVSDrm_alt:
5529 case X86::MMX_MOVD64rm:
5530 case X86::MMX_MOVQ64rm:
5531 case X86::MOVAPSrm:
5532 case X86::MOVUPSrm:
5533 case X86::MOVAPDrm:
5534 case X86::MOVUPDrm:
5535 case X86::MOVDQArm:
5536 case X86::MOVDQUrm:
5537 // AVX load instructions
5538 case X86::VMOVSSrm:
5539 case X86::VMOVSSrm_alt:
5540 case X86::VMOVSDrm:
5541 case X86::VMOVSDrm_alt:
5542 case X86::VMOVAPSrm:
5543 case X86::VMOVUPSrm:
5544 case X86::VMOVAPDrm:
5545 case X86::VMOVUPDrm:
5546 case X86::VMOVDQArm:
5547 case X86::VMOVDQUrm:
5548 case X86::VMOVAPSYrm:
5549 case X86::VMOVUPSYrm:
5550 case X86::VMOVAPDYrm:
5551 case X86::VMOVUPDYrm:
5552 case X86::VMOVDQAYrm:
5553 case X86::VMOVDQUYrm:
5554 // AVX512 load instructions
5555 case X86::VMOVSSZrm:
5556 case X86::VMOVSSZrm_alt:
5557 case X86::VMOVSDZrm:
5558 case X86::VMOVSDZrm_alt:
5559 case X86::VMOVAPSZ128rm:
5560 case X86::VMOVUPSZ128rm:
5561 case X86::VMOVAPSZ128rm_NOVLX:
5562 case X86::VMOVUPSZ128rm_NOVLX:
5563 case X86::VMOVAPDZ128rm:
5564 case X86::VMOVUPDZ128rm:
5565 case X86::VMOVDQU8Z128rm:
5566 case X86::VMOVDQU16Z128rm:
5567 case X86::VMOVDQA32Z128rm:
5568 case X86::VMOVDQU32Z128rm:
5569 case X86::VMOVDQA64Z128rm:
5570 case X86::VMOVDQU64Z128rm:
5571 case X86::VMOVAPSZ256rm:
5572 case X86::VMOVUPSZ256rm:
5573 case X86::VMOVAPSZ256rm_NOVLX:
5574 case X86::VMOVUPSZ256rm_NOVLX:
5575 case X86::VMOVAPDZ256rm:
5576 case X86::VMOVUPDZ256rm:
5577 case X86::VMOVDQU8Z256rm:
5578 case X86::VMOVDQU16Z256rm:
5579 case X86::VMOVDQA32Z256rm:
5580 case X86::VMOVDQU32Z256rm:
5581 case X86::VMOVDQA64Z256rm:
5582 case X86::VMOVDQU64Z256rm:
5583 case X86::VMOVAPSZrm:
5584 case X86::VMOVUPSZrm:
5585 case X86::VMOVAPDZrm:
5586 case X86::VMOVUPDZrm:
5587 case X86::VMOVDQU8Zrm:
5588 case X86::VMOVDQU16Zrm:
5589 case X86::VMOVDQA32Zrm:
5590 case X86::VMOVDQU32Zrm:
5591 case X86::VMOVDQA64Zrm:
5592 case X86::VMOVDQU64Zrm:
5593 case X86::KMOVBkm:
5594 case X86::KMOVWkm:
5595 case X86::KMOVDkm:
5596 case X86::KMOVQkm:
5597 break;
5598 }
5599 switch (Opc2) {
5600 default: return false;
5601 case X86::MOV8rm:
5602 case X86::MOV16rm:
5603 case X86::MOV32rm:
5604 case X86::MOV64rm:
5605 case X86::LD_Fp32m:
5606 case X86::LD_Fp64m:
5607 case X86::LD_Fp80m:
5608 case X86::MOVSSrm:
5609 case X86::MOVSSrm_alt:
5610 case X86::MOVSDrm:
5611 case X86::MOVSDrm_alt:
5612 case X86::MMX_MOVD64rm:
5613 case X86::MMX_MOVQ64rm:
5614 case X86::MOVAPSrm:
5615 case X86::MOVUPSrm:
5616 case X86::MOVAPDrm:
5617 case X86::MOVUPDrm:
5618 case X86::MOVDQArm:
5619 case X86::MOVDQUrm:
5620 // AVX load instructions
5621 case X86::VMOVSSrm:
5622 case X86::VMOVSSrm_alt:
5623 case X86::VMOVSDrm:
5624 case X86::VMOVSDrm_alt:
5625 case X86::VMOVAPSrm:
5626 case X86::VMOVUPSrm:
5627 case X86::VMOVAPDrm:
5628 case X86::VMOVUPDrm:
5629 case X86::VMOVDQArm:
5630 case X86::VMOVDQUrm:
5631 case X86::VMOVAPSYrm:
5632 case X86::VMOVUPSYrm:
5633 case X86::VMOVAPDYrm:
5634 case X86::VMOVUPDYrm:
5635 case X86::VMOVDQAYrm:
5636 case X86::VMOVDQUYrm:
5637 // AVX512 load instructions
5638 case X86::VMOVSSZrm:
5639 case X86::VMOVSSZrm_alt:
5640 case X86::VMOVSDZrm:
5641 case X86::VMOVSDZrm_alt:
5642 case X86::VMOVAPSZ128rm:
5643 case X86::VMOVUPSZ128rm:
5644 case X86::VMOVAPSZ128rm_NOVLX:
5645 case X86::VMOVUPSZ128rm_NOVLX:
5646 case X86::VMOVAPDZ128rm:
5647 case X86::VMOVUPDZ128rm:
5648 case X86::VMOVDQU8Z128rm:
5649 case X86::VMOVDQU16Z128rm:
5650 case X86::VMOVDQA32Z128rm:
5651 case X86::VMOVDQU32Z128rm:
5652 case X86::VMOVDQA64Z128rm:
5653 case X86::VMOVDQU64Z128rm:
5654 case X86::VMOVAPSZ256rm:
5655 case X86::VMOVUPSZ256rm:
5656 case X86::VMOVAPSZ256rm_NOVLX:
5657 case X86::VMOVUPSZ256rm_NOVLX:
5658 case X86::VMOVAPDZ256rm:
5659 case X86::VMOVUPDZ256rm:
5660 case X86::VMOVDQU8Z256rm:
5661 case X86::VMOVDQU16Z256rm:
5662 case X86::VMOVDQA32Z256rm:
5663 case X86::VMOVDQU32Z256rm:
5664 case X86::VMOVDQA64Z256rm:
5665 case X86::VMOVDQU64Z256rm:
5666 case X86::VMOVAPSZrm:
5667 case X86::VMOVUPSZrm:
5668 case X86::VMOVAPDZrm:
5669 case X86::VMOVUPDZrm:
5670 case X86::VMOVDQU8Zrm:
5671 case X86::VMOVDQU16Zrm:
5672 case X86::VMOVDQA32Zrm:
5673 case X86::VMOVDQU32Zrm:
5674 case X86::VMOVDQA64Zrm:
5675 case X86::VMOVDQU64Zrm:
5676 case X86::KMOVBkm:
5677 case X86::KMOVWkm:
5678 case X86::KMOVDkm:
5679 case X86::KMOVQkm:
5680 break;
5681 }
5682
5683 // Lambda to check if both the loads have the same value for an operand index.
5684 auto HasSameOp = [&](int I) {
5685 return Load1->getOperand(I) == Load2->getOperand(I);
5686 };
5687
5688 // All operands except the displacement should match.
5689 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
5690 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
5691 return false;
5692
5693 // Chain Operand must be the same.
5694 if (!HasSameOp(5))
5695 return false;
5696
5697 // Now let's examine if the displacements are constants.
5698 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
5699 auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
5700 if (!Disp1 || !Disp2)
5701 return false;
5702
5703 Offset1 = Disp1->getSExtValue();
5704 Offset2 = Disp2->getSExtValue();
5705 return true;
5706 }
5707
5708 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5709 int64_t Offset1, int64_t Offset2,
5710 unsigned NumLoads) const {
5711 assert(Offset2 > Offset1);
5712 if ((Offset2 - Offset1) / 8 > 64)
5713 return false;
5714
5715 unsigned Opc1 = Load1->getMachineOpcode();
5716 unsigned Opc2 = Load2->getMachineOpcode();
5717 if (Opc1 != Opc2)
5718 return false; // FIXME: overly conservative?
5719
5720 switch (Opc1) {
5721 default: break;
5722 case X86::LD_Fp32m:
5723 case X86::LD_Fp64m:
5724 case X86::LD_Fp80m:
5725 case X86::MMX_MOVD64rm:
5726 case X86::MMX_MOVQ64rm:
5727 return false;
5728 }
5729
5730 EVT VT = Load1->getValueType(0);
5731 switch (VT.getSimpleVT().SimpleTy) {
5732 default:
5733 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5734 // have 16 of them to play with.
5735 if (Subtarget.is64Bit()) {
5736 if (NumLoads >= 3)
5737 return false;
5738 } else if (NumLoads) {
5739 return false;
5740 }
5741 break;
5742 case MVT::i8:
5743 case MVT::i16:
5744 case MVT::i32:
5745 case MVT::i64:
5746 case MVT::f32:
5747 case MVT::f64:
5748 if (NumLoads)
5749 return false;
5750 break;
5751 }
5752
5753 return true;
5754 }
5755
5756 bool X86InstrInfo::
5757 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5758 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5759 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5760 Cond[0].setImm(GetOppositeBranchCondition(CC));
5761 return false;
5762 }
5763
5764 bool X86InstrInfo::
5765 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5766 // FIXME: Return false for x87 stack register classes for now. We can't
5767 // allow any loads of these registers before FpGet_ST0_80.
5768 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
5769 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
5770 RC == &X86::RFP80RegClass);
5771 }
5772
5773 /// Return a virtual register initialized with the
5774 /// the global base register value. Output instructions required to
5775 /// initialize the register in the function entry block, if necessary.
5776 ///
5777 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5778 ///
5779 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5780 assert((!Subtarget.is64Bit() ||
5781 MF->getTarget().getCodeModel() == CodeModel::Medium ||
5782 MF->getTarget().getCodeModel() == CodeModel::Large) &&
5783 "X86-64 PIC uses RIP relative addressing");
5784
5785 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5786 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5787 if (GlobalBaseReg != 0)
5788 return GlobalBaseReg;
5789
5790 // Create the register. The code to initialize it is inserted
5791 // later, by the CGBR pass (below).
5792 MachineRegisterInfo &RegInfo = MF->getRegInfo();
5793 GlobalBaseReg = RegInfo.createVirtualRegister(
5794 Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
5795 X86FI->setGlobalBaseReg(GlobalBaseReg);
5796 return GlobalBaseReg;
5797 }
5798
5799 // These are the replaceable SSE instructions. Some of these have Int variants
5800 // that we don't include here. We don't want to replace instructions selected
5801 // by intrinsics.
5802 static const uint16_t ReplaceableInstrs[][3] = {
5803 //PackedSingle PackedDouble PackedInt
5804 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5805 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5806 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5807 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5808 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5809 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
5810 { X86::MOVSDmr, X86::MOVSDmr, X86::MOVPQI2QImr },
5811 { X86::MOVSSmr, X86::MOVSSmr, X86::MOVPDI2DImr },
5812 { X86::MOVSDrm, X86::MOVSDrm, X86::MOVQI2PQIrm },
5813 { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
5814 { X86::MOVSSrm, X86::MOVSSrm, X86::MOVDI2PDIrm },
5815 { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
5816 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5817 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5818 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5819 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5820 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5821 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5822 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5823 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5824 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
5825 { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
5826 { X86::MOVLHPSrr, X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
5827 { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
5828 { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
5829 { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
5830 { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
5831 { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
5832 { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
5833 { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
5834 { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
5835 // AVX 128-bit support
5836 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5837 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5838 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5839 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5840 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5841 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
5842 { X86::VMOVSDmr, X86::VMOVSDmr, X86::VMOVPQI2QImr },
5843 { X86::VMOVSSmr, X86::VMOVSSmr, X86::VMOVPDI2DImr },
5844 { X86::VMOVSDrm, X86::VMOVSDrm, X86::VMOVQI2PQIrm },
5845 { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
5846 { X86::VMOVSSrm, X86::VMOVSSrm, X86::VMOVDI2PDIrm },
5847 { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
5848 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5849 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5850 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5851 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5852 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5853 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5854 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
5855 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5856 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
5857 { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
5858 { X86::VMOVLHPSrr, X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
5859 { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
5860 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
5861 { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
5862 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
5863 { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
5864 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
5865 { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
5866 { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
5867 // AVX 256-bit support
5868 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5869 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5870 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5871 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5872 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
5873 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
5874 { X86::VPERMPSYrm, X86::VPERMPSYrm, X86::VPERMDYrm },
5875 { X86::VPERMPSYrr, X86::VPERMPSYrr, X86::VPERMDYrr },
5876 { X86::VPERMPDYmi, X86::VPERMPDYmi, X86::VPERMQYmi },
5877 { X86::VPERMPDYri, X86::VPERMPDYri, X86::VPERMQYri },
5878 // AVX512 support
5879 { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr },
5880 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
5881 { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
5882 { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr },
5883 { X86::VMOVSDZmr, X86::VMOVSDZmr, X86::VMOVPQI2QIZmr },
5884 { X86::VMOVSSZmr, X86::VMOVSSZmr, X86::VMOVPDI2DIZmr },
5885 { X86::VMOVSDZrm, X86::VMOVSDZrm, X86::VMOVQI2PQIZrm },
5886 { X86::VMOVSDZrm_alt, X86::VMOVSDZrm_alt, X86::VMOVQI2PQIZrm },
5887 { X86::VMOVSSZrm, X86::VMOVSSZrm, X86::VMOVDI2PDIZrm },
5888 { X86::VMOVSSZrm_alt, X86::VMOVSSZrm_alt, X86::VMOVDI2PDIZrm },
5889 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
5890 { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
5891 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
5892 { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
5893 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZr, X86::VPBROADCASTDZr },
5894 { X86::VBROADCASTSSZm, X86::VBROADCASTSSZm, X86::VPBROADCASTDZm },
5895 { X86::VMOVDDUPZ128rr, X86::VMOVDDUPZ128rr, X86::VPBROADCASTQZ128r },
5896 { X86::VMOVDDUPZ128rm, X86::VMOVDDUPZ128rm, X86::VPBROADCASTQZ128m },
5897 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
5898 { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
5899 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZr, X86::VPBROADCASTQZr },
5900 { X86::VBROADCASTSDZm, X86::VBROADCASTSDZm, X86::VPBROADCASTQZm },
5901 { X86::VINSERTF32x4Zrr, X86::VINSERTF32x4Zrr, X86::VINSERTI32x4Zrr },
5902 { X86::VINSERTF32x4Zrm, X86::VINSERTF32x4Zrm, X86::VINSERTI32x4Zrm },
5903 { X86::VINSERTF32x8Zrr, X86::VINSERTF32x8Zrr, X86::VINSERTI32x8Zrr },
5904 { X86::VINSERTF32x8Zrm, X86::VINSERTF32x8Zrm, X86::VINSERTI32x8Zrm },
5905 { X86::VINSERTF64x2Zrr, X86::VINSERTF64x2Zrr, X86::VINSERTI64x2Zrr },
5906 { X86::VINSERTF64x2Zrm, X86::VINSERTF64x2Zrm, X86::VINSERTI64x2Zrm },
5907 { X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrr, X86::VINSERTI64x4Zrr },
5908 { X86::VINSERTF64x4Zrm, X86::VINSERTF64x4Zrm, X86::VINSERTI64x4Zrm },
5909 { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
5910 { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
5911 { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
5912 { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
5913 { X86::VEXTRACTF32x4Zrr, X86::VEXTRACTF32x4Zrr, X86::VEXTRACTI32x4Zrr },
5914 { X86::VEXTRACTF32x4Zmr, X86::VEXTRACTF32x4Zmr, X86::VEXTRACTI32x4Zmr },
5915 { X86::VEXTRACTF32x8Zrr, X86::VEXTRACTF32x8Zrr, X86::VEXTRACTI32x8Zrr },
5916 { X86::VEXTRACTF32x8Zmr, X86::VEXTRACTF32x8Zmr, X86::VEXTRACTI32x8Zmr },
5917 { X86::VEXTRACTF64x2Zrr, X86::VEXTRACTF64x2Zrr, X86::VEXTRACTI64x2Zrr },
5918 { X86::VEXTRACTF64x2Zmr, X86::VEXTRACTF64x2Zmr, X86::VEXTRACTI64x2Zmr },
5919 { X86::VEXTRACTF64x4Zrr, X86::VEXTRACTF64x4Zrr, X86::VEXTRACTI64x4Zrr },
5920 { X86::VEXTRACTF64x4Zmr, X86::VEXTRACTF64x4Zmr, X86::VEXTRACTI64x4Zmr },
5921 { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
5922 { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
5923 { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
5924 { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
5925 { X86::VPERMILPSmi, X86::VPERMILPSmi, X86::VPSHUFDmi },
5926 { X86::VPERMILPSri, X86::VPERMILPSri, X86::VPSHUFDri },
5927 { X86::VPERMILPSZ128mi, X86::VPERMILPSZ128mi, X86::VPSHUFDZ128mi },
5928 { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128ri, X86::VPSHUFDZ128ri },
5929 { X86::VPERMILPSZ256mi, X86::VPERMILPSZ256mi, X86::VPSHUFDZ256mi },
5930 { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256ri, X86::VPSHUFDZ256ri },
5931 { X86::VPERMILPSZmi, X86::VPERMILPSZmi, X86::VPSHUFDZmi },
5932 { X86::VPERMILPSZri, X86::VPERMILPSZri, X86::VPSHUFDZri },
5933 { X86::VPERMPSZ256rm, X86::VPERMPSZ256rm, X86::VPERMDZ256rm },
5934 { X86::VPERMPSZ256rr, X86::VPERMPSZ256rr, X86::VPERMDZ256rr },
5935 { X86::VPERMPDZ256mi, X86::VPERMPDZ256mi, X86::VPERMQZ256mi },
5936 { X86::VPERMPDZ256ri, X86::VPERMPDZ256ri, X86::VPERMQZ256ri },
5937 { X86::VPERMPDZ256rm, X86::VPERMPDZ256rm, X86::VPERMQZ256rm },
5938 { X86::VPERMPDZ256rr, X86::VPERMPDZ256rr, X86::VPERMQZ256rr },
5939 { X86::VPERMPSZrm, X86::VPERMPSZrm, X86::VPERMDZrm },
5940 { X86::VPERMPSZrr, X86::VPERMPSZrr, X86::VPERMDZrr },
5941 { X86::VPERMPDZmi, X86::VPERMPDZmi, X86::VPERMQZmi },
5942 { X86::VPERMPDZri, X86::VPERMPDZri, X86::VPERMQZri },
5943 { X86::VPERMPDZrm, X86::VPERMPDZrm, X86::VPERMQZrm },
5944 { X86::VPERMPDZrr, X86::VPERMPDZrr, X86::VPERMQZrr },
5945 { X86::VUNPCKLPDZ256rm, X86::VUNPCKLPDZ256rm, X86::VPUNPCKLQDQZ256rm },
5946 { X86::VUNPCKLPDZ256rr, X86::VUNPCKLPDZ256rr, X86::VPUNPCKLQDQZ256rr },
5947 { X86::VUNPCKHPDZ256rm, X86::VUNPCKHPDZ256rm, X86::VPUNPCKHQDQZ256rm },
5948 { X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rr, X86::VPUNPCKHQDQZ256rr },
5949 { X86::VUNPCKLPSZ256rm, X86::VUNPCKLPSZ256rm, X86::VPUNPCKLDQZ256rm },
5950 { X86::VUNPCKLPSZ256rr, X86::VUNPCKLPSZ256rr, X86::VPUNPCKLDQZ256rr },
5951 { X86::VUNPCKHPSZ256rm, X86::VUNPCKHPSZ256rm, X86::VPUNPCKHDQZ256rm },
5952 { X86::VUNPCKHPSZ256rr, X86::VUNPCKHPSZ256rr, X86::VPUNPCKHDQZ256rr },
5953 { X86::VUNPCKLPDZ128rm, X86::VUNPCKLPDZ128rm, X86::VPUNPCKLQDQZ128rm },
5954 { X86::VMOVLHPSZrr, X86::VUNPCKLPDZ128rr, X86::VPUNPCKLQDQZ128rr },
5955 { X86::VUNPCKHPDZ128rm, X86::VUNPCKHPDZ128rm, X86::VPUNPCKHQDQZ128rm },
5956 { X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rr, X86::VPUNPCKHQDQZ128rr },
5957 { X86::VUNPCKLPSZ128rm, X86::VUNPCKLPSZ128rm, X86::VPUNPCKLDQZ128rm },
5958 { X86::VUNPCKLPSZ128rr, X86::VUNPCKLPSZ128rr, X86::VPUNPCKLDQZ128rr },
5959 { X86::VUNPCKHPSZ128rm, X86::VUNPCKHPSZ128rm, X86::VPUNPCKHDQZ128rm },
5960 { X86::VUNPCKHPSZ128rr, X86::VUNPCKHPSZ128rr, X86::VPUNPCKHDQZ128rr },
5961 { X86::VUNPCKLPDZrm, X86::VUNPCKLPDZrm, X86::VPUNPCKLQDQZrm },
5962 { X86::VUNPCKLPDZrr, X86::VUNPCKLPDZrr, X86::VPUNPCKLQDQZrr },
5963 { X86::VUNPCKHPDZrm, X86::VUNPCKHPDZrm, X86::VPUNPCKHQDQZrm },
5964 { X86::VUNPCKHPDZrr, X86::VUNPCKHPDZrr, X86::VPUNPCKHQDQZrr },
5965 { X86::VUNPCKLPSZrm, X86::VUNPCKLPSZrm, X86::VPUNPCKLDQZrm },
5966 { X86::VUNPCKLPSZrr, X86::VUNPCKLPSZrr, X86::VPUNPCKLDQZrr },
5967 { X86::VUNPCKHPSZrm, X86::VUNPCKHPSZrm, X86::VPUNPCKHDQZrm },
5968 { X86::VUNPCKHPSZrr, X86::VUNPCKHPSZrr, X86::VPUNPCKHDQZrr },
5969 { X86::VEXTRACTPSZmr, X86::VEXTRACTPSZmr, X86::VPEXTRDZmr },
5970 { X86::VEXTRACTPSZrr, X86::VEXTRACTPSZrr, X86::VPEXTRDZrr },
5971 };
5972
5973 static const uint16_t ReplaceableInstrsAVX2[][3] = {
5974 //PackedSingle PackedDouble PackedInt
5975 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
5976 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
5977 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
5978 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
5979 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
5980 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
5981 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
5982 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
5983 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
5984 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
5985 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5986 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5987 { X86::VMOVDDUPrm, X86::VMOVDDUPrm, X86::VPBROADCASTQrm},
5988 { X86::VMOVDDUPrr, X86::VMOVDDUPrr, X86::VPBROADCASTQrr},
5989 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5990 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5991 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5992 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
5993 { X86::VBROADCASTF128, X86::VBROADCASTF128, X86::VBROADCASTI128 },
5994 { X86::VBLENDPSYrri, X86::VBLENDPSYrri, X86::VPBLENDDYrri },
5995 { X86::VBLENDPSYrmi, X86::VBLENDPSYrmi, X86::VPBLENDDYrmi },
5996 { X86::VPERMILPSYmi, X86::VPERMILPSYmi, X86::VPSHUFDYmi },
5997 { X86::VPERMILPSYri, X86::VPERMILPSYri, X86::VPSHUFDYri },
5998 { X86::VUNPCKLPDYrm, X86::VUNPCKLPDYrm, X86::VPUNPCKLQDQYrm },
5999 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrr, X86::VPUNPCKLQDQYrr },
6000 { X86::VUNPCKHPDYrm, X86::VUNPCKHPDYrm, X86::VPUNPCKHQDQYrm },
6001 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrr, X86::VPUNPCKHQDQYrr },
6002 { X86::VUNPCKLPSYrm, X86::VUNPCKLPSYrm, X86::VPUNPCKLDQYrm },
6003 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrr, X86::VPUNPCKLDQYrr },
6004 { X86::VUNPCKHPSYrm, X86::VUNPCKHPSYrm, X86::VPUNPCKHDQYrm },
6005 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrr, X86::VPUNPCKHDQYrr },
6006 };
6007
6008 static const uint16_t ReplaceableInstrsFP[][3] = {
6009 //PackedSingle PackedDouble
6010 { X86::MOVLPSrm, X86::MOVLPDrm, X86::INSTRUCTION_LIST_END },
6011 { X86::MOVHPSrm, X86::MOVHPDrm, X86::INSTRUCTION_LIST_END },
6012 { X86::MOVHPSmr, X86::MOVHPDmr, X86::INSTRUCTION_LIST_END },
6013 { X86::VMOVLPSrm, X86::VMOVLPDrm, X86::INSTRUCTION_LIST_END },
6014 { X86::VMOVHPSrm, X86::VMOVHPDrm, X86::INSTRUCTION_LIST_END },
6015 { X86::VMOVHPSmr, X86::VMOVHPDmr, X86::INSTRUCTION_LIST_END },
6016 { X86::VMOVLPSZ128rm, X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
6017 { X86::VMOVHPSZ128rm, X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
6018 { X86::VMOVHPSZ128mr, X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
6019 };
6020
6021 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
6022 //PackedSingle PackedDouble PackedInt
6023 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6024 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6025 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6026 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6027 };
6028
6029 static const uint16_t ReplaceableInstrsAVX512[][4] = {
6030 // Two integer columns for 64-bit and 32-bit elements.
6031 //PackedSingle PackedDouble PackedInt PackedInt
6032 { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr },
6033 { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm },
6034 { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr },
6035 { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr },
6036 { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm },
6037 { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr },
6038 { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm },
6039 { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr },
6040 { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr },
6041 { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm },
6042 { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr },
6043 { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm },
6044 { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr },
6045 { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr },
6046 { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm },
6047 };
6048
6049 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
6050 // Two integer columns for 64-bit and 32-bit elements.
6051 //PackedSingle PackedDouble PackedInt PackedInt
6052 { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6053 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6054 { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
6055 { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
6056 { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm },
6057 { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr },
6058 { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
6059 { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
6060 { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6061 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6062 { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
6063 { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
6064 { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm },
6065 { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr },
6066 { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
6067 { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
6068 { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm },
6069 { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr },
6070 { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm },
6071 { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr },
6072 { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm },
6073 { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr },
6074 { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm },
6075 { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr },
6076 };
6077
6078 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
6079 // Two integer columns for 64-bit and 32-bit elements.
6080 //PackedSingle PackedDouble
6081 //PackedInt PackedInt
6082 { X86::VANDNPSZ128rmk, X86::VANDNPDZ128rmk,
6083 X86::VPANDNQZ128rmk, X86::VPANDNDZ128rmk },
6084 { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
6085 X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
6086 { X86::VANDNPSZ128rrk, X86::VANDNPDZ128rrk,
6087 X86::VPANDNQZ128rrk, X86::VPANDNDZ128rrk },
6088 { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
6089 X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
6090 { X86::VANDPSZ128rmk, X86::VANDPDZ128rmk,
6091 X86::VPANDQZ128rmk, X86::VPANDDZ128rmk },
6092 { X86::VANDPSZ128rmkz, X86::VANDPDZ128rmkz,
6093 X86::VPANDQZ128rmkz, X86::VPANDDZ128rmkz },
6094 { X86::VANDPSZ128rrk, X86::VANDPDZ128rrk,
6095 X86::VPANDQZ128rrk, X86::VPANDDZ128rrk },
6096 { X86::VANDPSZ128rrkz, X86::VANDPDZ128rrkz,
6097 X86::VPANDQZ128rrkz, X86::VPANDDZ128rrkz },
6098 { X86::VORPSZ128rmk, X86::VORPDZ128rmk,
6099 X86::VPORQZ128rmk, X86::VPORDZ128rmk },
6100 { X86::VORPSZ128rmkz, X86::VORPDZ128rmkz,
6101 X86::VPORQZ128rmkz, X86::VPORDZ128rmkz },
6102 { X86::VORPSZ128rrk, X86::VORPDZ128rrk,
6103 X86::VPORQZ128rrk, X86::VPORDZ128rrk },
6104 { X86::VORPSZ128rrkz, X86::VORPDZ128rrkz,
6105 X86::VPORQZ128rrkz, X86::VPORDZ128rrkz },
6106 { X86::VXORPSZ128rmk, X86::VXORPDZ128rmk,
6107 X86::VPXORQZ128rmk, X86::VPXORDZ128rmk },
6108 { X86::VXORPSZ128rmkz, X86::VXORPDZ128rmkz,
6109 X86::VPXORQZ128rmkz, X86::VPXORDZ128rmkz },
6110 { X86::VXORPSZ128rrk, X86::VXORPDZ128rrk,
6111 X86::VPXORQZ128rrk, X86::VPXORDZ128rrk },
6112 { X86::VXORPSZ128rrkz, X86::VXORPDZ128rrkz,
6113 X86::VPXORQZ128rrkz, X86::VPXORDZ128rrkz },
6114 { X86::VANDNPSZ256rmk, X86::VANDNPDZ256rmk,
6115 X86::VPANDNQZ256rmk, X86::VPANDNDZ256rmk },
6116 { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
6117 X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
6118 { X86::VANDNPSZ256rrk, X86::VANDNPDZ256rrk,
6119 X86::VPANDNQZ256rrk, X86::VPANDNDZ256rrk },
6120 { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
6121 X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
6122 { X86::VANDPSZ256rmk, X86::VANDPDZ256rmk,
6123 X86::VPANDQZ256rmk, X86::VPANDDZ256rmk },
6124 { X86::VANDPSZ256rmkz, X86::VANDPDZ256rmkz,
6125 X86::VPANDQZ256rmkz, X86::VPANDDZ256rmkz },
6126 { X86::VANDPSZ256rrk, X86::VANDPDZ256rrk,
6127 X86::VPANDQZ256rrk, X86::VPANDDZ256rrk },
6128 { X86::VANDPSZ256rrkz, X86::VANDPDZ256rrkz,
6129 X86::VPANDQZ256rrkz, X86::VPANDDZ256rrkz },
6130 { X86::VORPSZ256rmk, X86::VORPDZ256rmk,
6131 X86::VPORQZ256rmk, X86::VPORDZ256rmk },
6132 { X86::VORPSZ256rmkz, X86::VORPDZ256rmkz,
6133 X86::VPORQZ256rmkz, X86::VPORDZ256rmkz },
6134 { X86::VORPSZ256rrk, X86::VORPDZ256rrk,
6135 X86::VPORQZ256rrk, X86::VPORDZ256rrk },
6136 { X86::VORPSZ256rrkz, X86::VORPDZ256rrkz,
6137 X86::VPORQZ256rrkz, X86::VPORDZ256rrkz },
6138 { X86::VXORPSZ256rmk, X86::VXORPDZ256rmk,
6139 X86::VPXORQZ256rmk, X86::VPXORDZ256rmk },
6140 { X86::VXORPSZ256rmkz, X86::VXORPDZ256rmkz,
6141 X86::VPXORQZ256rmkz, X86::VPXORDZ256rmkz },
6142 { X86::VXORPSZ256rrk, X86::VXORPDZ256rrk,
6143 X86::VPXORQZ256rrk, X86::VPXORDZ256rrk },
6144 { X86::VXORPSZ256rrkz, X86::VXORPDZ256rrkz,
6145 X86::VPXORQZ256rrkz, X86::VPXORDZ256rrkz },
6146 { X86::VANDNPSZrmk, X86::VANDNPDZrmk,
6147 X86::VPANDNQZrmk, X86::VPANDNDZrmk },
6148 { X86::VANDNPSZrmkz, X86::VANDNPDZrmkz,
6149 X86::VPANDNQZrmkz, X86::VPANDNDZrmkz },
6150 { X86::VANDNPSZrrk, X86::VANDNPDZrrk,
6151 X86::VPANDNQZrrk, X86::VPANDNDZrrk },
6152 { X86::VANDNPSZrrkz, X86::VANDNPDZrrkz,
6153 X86::VPANDNQZrrkz, X86::VPANDNDZrrkz },
6154 { X86::VANDPSZrmk, X86::VANDPDZrmk,
6155 X86::VPANDQZrmk, X86::VPANDDZrmk },
6156 { X86::VANDPSZrmkz, X86::VANDPDZrmkz,
6157 X86::VPANDQZrmkz, X86::VPANDDZrmkz },
6158 { X86::VANDPSZrrk, X86::VANDPDZrrk,
6159 X86::VPANDQZrrk, X86::VPANDDZrrk },
6160 { X86::VANDPSZrrkz, X86::VANDPDZrrkz,
6161 X86::VPANDQZrrkz, X86::VPANDDZrrkz },
6162 { X86::VORPSZrmk, X86::VORPDZrmk,
6163 X86::VPORQZrmk, X86::VPORDZrmk },
6164 { X86::VORPSZrmkz, X86::VORPDZrmkz,
6165 X86::VPORQZrmkz, X86::VPORDZrmkz },
6166 { X86::VORPSZrrk, X86::VORPDZrrk,
6167 X86::VPORQZrrk, X86::VPORDZrrk },
6168 { X86::VORPSZrrkz, X86::VORPDZrrkz,
6169 X86::VPORQZrrkz, X86::VPORDZrrkz },
6170 { X86::VXORPSZrmk, X86::VXORPDZrmk,
6171 X86::VPXORQZrmk, X86::VPXORDZrmk },
6172 { X86::VXORPSZrmkz, X86::VXORPDZrmkz,
6173 X86::VPXORQZrmkz, X86::VPXORDZrmkz },
6174 { X86::VXORPSZrrk, X86::VXORPDZrrk,
6175 X86::VPXORQZrrk, X86::VPXORDZrrk },
6176 { X86::VXORPSZrrkz, X86::VXORPDZrrkz,
6177 X86::VPXORQZrrkz, X86::VPXORDZrrkz },
6178 // Broadcast loads can be handled the same as masked operations to avoid
6179 // changing element size.
6180 { X86::VANDNPSZ128rmb, X86::VANDNPDZ128rmb,
6181 X86::VPANDNQZ128rmb, X86::VPANDNDZ128rmb },
6182 { X86::VANDPSZ128rmb, X86::VANDPDZ128rmb,
6183 X86::VPANDQZ128rmb, X86::VPANDDZ128rmb },
6184 { X86::VORPSZ128rmb, X86::VORPDZ128rmb,
6185 X86::VPORQZ128rmb, X86::VPORDZ128rmb },
6186 { X86::VXORPSZ128rmb, X86::VXORPDZ128rmb,
6187 X86::VPXORQZ128rmb, X86::VPXORDZ128rmb },
6188 { X86::VANDNPSZ256rmb, X86::VANDNPDZ256rmb,
6189 X86::VPANDNQZ256rmb, X86::VPANDNDZ256rmb },
6190 { X86::VANDPSZ256rmb, X86::VANDPDZ256rmb,
6191 X86::VPANDQZ256rmb, X86::VPANDDZ256rmb },
6192 { X86::VORPSZ256rmb, X86::VORPDZ256rmb,
6193 X86::VPORQZ256rmb, X86::VPORDZ256rmb },
6194 { X86::VXORPSZ256rmb, X86::VXORPDZ256rmb,
6195 X86::VPXORQZ256rmb, X86::VPXORDZ256rmb },
6196 { X86::VANDNPSZrmb, X86::VANDNPDZrmb,
6197 X86::VPANDNQZrmb, X86::VPANDNDZrmb },
6198 { X86::VANDPSZrmb, X86::VANDPDZrmb,
6199 X86::VPANDQZrmb, X86::VPANDDZrmb },
6200 { X86::VANDPSZrmb, X86::VANDPDZrmb,
6201 X86::VPANDQZrmb, X86::VPANDDZrmb },
6202 { X86::VORPSZrmb, X86::VORPDZrmb,
6203 X86::VPORQZrmb, X86::VPORDZrmb },
6204 { X86::VXORPSZrmb, X86::VXORPDZrmb,
6205 X86::VPXORQZrmb, X86::VPXORDZrmb },
6206 { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
6207 X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
6208 { X86::VANDPSZ128rmbk, X86::VANDPDZ128rmbk,
6209 X86::VPANDQZ128rmbk, X86::VPANDDZ128rmbk },
6210 { X86::VORPSZ128rmbk, X86::VORPDZ128rmbk,
6211 X86::VPORQZ128rmbk, X86::VPORDZ128rmbk },
6212 { X86::VXORPSZ128rmbk, X86::VXORPDZ128rmbk,
6213 X86::VPXORQZ128rmbk, X86::VPXORDZ128rmbk },
6214 { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
6215 X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
6216 { X86::VANDPSZ256rmbk, X86::VANDPDZ256rmbk,
6217 X86::VPANDQZ256rmbk, X86::VPANDDZ256rmbk },
6218 { X86::VORPSZ256rmbk, X86::VORPDZ256rmbk,
6219 X86::VPORQZ256rmbk, X86::VPORDZ256rmbk },
6220 { X86::VXORPSZ256rmbk, X86::VXORPDZ256rmbk,
6221 X86::VPXORQZ256rmbk, X86::VPXORDZ256rmbk },
6222 { X86::VANDNPSZrmbk, X86::VANDNPDZrmbk,
6223 X86::VPANDNQZrmbk, X86::VPANDNDZrmbk },
6224 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
6225 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
6226 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
6227 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
6228 { X86::VORPSZrmbk, X86::VORPDZrmbk,
6229 X86::VPORQZrmbk, X86::VPORDZrmbk },
6230 { X86::VXORPSZrmbk, X86::VXORPDZrmbk,
6231 X86::VPXORQZrmbk, X86::VPXORDZrmbk },
6232 { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
6233 X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
6234 { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
6235 X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
6236 { X86::VORPSZ128rmbkz, X86::VORPDZ128rmbkz,
6237 X86::VPORQZ128rmbkz, X86::VPORDZ128rmbkz },
6238 { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
6239 X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
6240 { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
6241 X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
6242 { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
6243 X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
6244 { X86::VORPSZ256rmbkz, X86::VORPDZ256rmbkz,
6245 X86::VPORQZ256rmbkz, X86::VPORDZ256rmbkz },
6246 { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
6247 X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
6248 { X86::VANDNPSZrmbkz, X86::VANDNPDZrmbkz,
6249 X86::VPANDNQZrmbkz, X86::VPANDNDZrmbkz },
6250 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
6251 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
6252 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
6253 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
6254 { X86::VORPSZrmbkz, X86::VORPDZrmbkz,
6255 X86::VPORQZrmbkz, X86::VPORDZrmbkz },
6256 { X86::VXORPSZrmbkz, X86::VXORPDZrmbkz,
6257 X86::VPXORQZrmbkz, X86::VPXORDZrmbkz },
6258 };
6259
6260 // NOTE: These should only be used by the custom domain methods.
6261 static const uint16_t ReplaceableBlendInstrs[][3] = {
6262 //PackedSingle PackedDouble PackedInt
6263 { X86::BLENDPSrmi, X86::BLENDPDrmi, X86::PBLENDWrmi },
6264 { X86::BLENDPSrri, X86::BLENDPDrri, X86::PBLENDWrri },
6265 { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDWrmi },
6266 { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDWrri },
6267 { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDWYrmi },
6268 { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDWYrri },
6269 };
6270 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
6271 //PackedSingle PackedDouble PackedInt
6272 { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDDrmi },
6273 { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDDrri },
6274 { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDDYrmi },
6275 { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDDYrri },
6276 };
6277
6278 // Special table for changing EVEX logic instructions to VEX.
6279 // TODO: Should we run EVEX->VEX earlier?
6280 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
6281 // Two integer columns for 64-bit and 32-bit elements.
6282 //PackedSingle PackedDouble PackedInt PackedInt
6283 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6284 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6285 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
6286 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
6287 { X86::VORPSrm, X86::VORPDrm, X86::VPORQZ128rm, X86::VPORDZ128rm },
6288 { X86::VORPSrr, X86::VORPDrr, X86::VPORQZ128rr, X86::VPORDZ128rr },
6289 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
6290 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
6291 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6292 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6293 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
6294 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
6295 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORQZ256rm, X86::VPORDZ256rm },
6296 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORQZ256rr, X86::VPORDZ256rr },
6297 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
6298 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
6299 };
6300
6301 // FIXME: Some shuffle and unpack instructions have equivalents in different
6302 // domains, but they require a bit more work than just switching opcodes.
6303
6304 static const uint16_t *lookup(unsigned opcode, unsigned domain,
6305 ArrayRef<uint16_t[3]> Table) {
6306 for (const uint16_t (&Row)[3] : Table)
6307 if (Row[domain-1] == opcode)
6308 return Row;
6309 return nullptr;
6310 }
6311
6312 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
6313 ArrayRef<uint16_t[4]> Table) {
6314 // If this is the integer domain make sure to check both integer columns.
6315 for (const uint16_t (&Row)[4] : Table)
6316 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
6317 return Row;
6318 return nullptr;
6319 }
6320
6321 // Helper to attempt to widen/narrow blend masks.
6322 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
6323 unsigned NewWidth, unsigned *pNewMask = nullptr) {
6324 assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
6325 "Illegal blend mask scale");
6326 unsigned NewMask = 0;
6327
6328 if ((OldWidth % NewWidth) == 0) {
6329 unsigned Scale = OldWidth / NewWidth;
6330 unsigned SubMask = (1u << Scale) - 1;
6331 for (unsigned i = 0; i != NewWidth; ++i) {
6332 unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
6333 if (Sub == SubMask)
6334 NewMask |= (1u << i);
6335 else if (Sub != 0x0)
6336 return false;
6337 }
6338 } else {
6339 unsigned Scale = NewWidth / OldWidth;
6340 unsigned SubMask = (1u << Scale) - 1;
6341 for (unsigned i = 0; i != OldWidth; ++i) {
6342 if (OldMask & (1 << i)) {
6343 NewMask |= (SubMask << (i * Scale));
6344 }
6345 }
6346 }
6347
6348 if (pNewMask)
6349 *pNewMask = NewMask;
6350 return true;
6351 }
6352
6353 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
6354 unsigned Opcode = MI.getOpcode();
6355 unsigned NumOperands = MI.getDesc().getNumOperands();
6356
6357 auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
6358 uint16_t validDomains = 0;
6359 if (MI.getOperand(NumOperands - 1).isImm()) {
6360 unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
6361 if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
6362 validDomains |= 0x2; // PackedSingle
6363 if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
6364 validDomains |= 0x4; // PackedDouble
6365 if (!Is256 || Subtarget.hasAVX2())
6366 validDomains |= 0x8; // PackedInt
6367 }
6368 return validDomains;
6369 };
6370
6371 switch (Opcode) {
6372 case X86::BLENDPDrmi:
6373 case X86::BLENDPDrri:
6374 case X86::VBLENDPDrmi:
6375 case X86::VBLENDPDrri:
6376 return GetBlendDomains(2, false);
6377 case X86::VBLENDPDYrmi:
6378 case X86::VBLENDPDYrri:
6379 return GetBlendDomains(4, true);
6380 case X86::BLENDPSrmi:
6381 case X86::BLENDPSrri:
6382 case X86::VBLENDPSrmi:
6383 case X86::VBLENDPSrri:
6384 case X86::VPBLENDDrmi:
6385 case X86::VPBLENDDrri:
6386 return GetBlendDomains(4, false);
6387 case X86::VBLENDPSYrmi:
6388 case X86::VBLENDPSYrri:
6389 case X86::VPBLENDDYrmi:
6390 case X86::VPBLENDDYrri:
6391 return GetBlendDomains(8, true);
6392 case X86::PBLENDWrmi:
6393 case X86::PBLENDWrri:
6394 case X86::VPBLENDWrmi:
6395 case X86::VPBLENDWrri:
6396 // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
6397 case X86::VPBLENDWYrmi:
6398 case X86::VPBLENDWYrri:
6399 return GetBlendDomains(8, false);
6400 case X86::VPANDDZ128rr: case X86::VPANDDZ128rm:
6401 case X86::VPANDDZ256rr: case X86::VPANDDZ256rm:
6402 case X86::VPANDQZ128rr: case X86::VPANDQZ128rm:
6403 case X86::VPANDQZ256rr: case X86::VPANDQZ256rm:
6404 case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6405 case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6406 case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6407 case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6408 case X86::VPORDZ128rr: case X86::VPORDZ128rm:
6409 case X86::VPORDZ256rr: case X86::VPORDZ256rm:
6410 case X86::VPORQZ128rr: case X86::VPORQZ128rm:
6411 case X86::VPORQZ256rr: case X86::VPORQZ256rm:
6412 case X86::VPXORDZ128rr: case X86::VPXORDZ128rm:
6413 case X86::VPXORDZ256rr: case X86::VPXORDZ256rm:
6414 case X86::VPXORQZ128rr: case X86::VPXORQZ128rm:
6415 case X86::VPXORQZ256rr: case X86::VPXORQZ256rm:
6416 // If we don't have DQI see if we can still switch from an EVEX integer
6417 // instruction to a VEX floating point instruction.
6418 if (Subtarget.hasDQI())
6419 return 0;
6420
6421 if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
6422 return 0;
6423 if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
6424 return 0;
6425 // Register forms will have 3 operands. Memory form will have more.
6426 if (NumOperands == 3 &&
6427 RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
6428 return 0;
6429
6430 // All domains are valid.
6431 return 0xe;
6432 case X86::MOVHLPSrr:
6433 // We can swap domains when both inputs are the same register.
6434 // FIXME: This doesn't catch all the cases we would like. If the input
6435 // register isn't KILLed by the instruction, the two address instruction
6436 // pass puts a COPY on one input. The other input uses the original
6437 // register. This prevents the same physical register from being used by
6438 // both inputs.
6439 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6440 MI.getOperand(0).getSubReg() == 0 &&
6441 MI.getOperand(1).getSubReg() == 0 &&
6442 MI.getOperand(2).getSubReg() == 0)
6443 return 0x6;
6444 return 0;
6445 case X86::SHUFPDrri:
6446 return 0x6;
6447 }
6448 return 0;
6449 }
6450
6451 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
6452 unsigned Domain) const {
6453 assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
6454 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6455 assert(dom && "Not an SSE instruction");
6456
6457 unsigned Opcode = MI.getOpcode();
6458 unsigned NumOperands = MI.getDesc().getNumOperands();
6459
6460 auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
6461 if (MI.getOperand(NumOperands - 1).isImm()) {
6462 unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
6463 Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
6464 unsigned NewImm = Imm;
6465
6466 const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
6467 if (!table)
6468 table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
6469
6470 if (Domain == 1) { // PackedSingle
6471 AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6472 } else if (Domain == 2) { // PackedDouble
6473 AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
6474 } else if (Domain == 3) { // PackedInt
6475 if (Subtarget.hasAVX2()) {
6476 // If we are already VPBLENDW use that, else use VPBLENDD.
6477 if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
6478 table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
6479 AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6480 }
6481 } else {
6482 assert(!Is256 && "128-bit vector expected");
6483 AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
6484 }
6485 }
6486
6487 assert(table && table[Domain - 1] && "Unknown domain op");
6488 MI.setDesc(get(table[Domain - 1]));
6489 MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
6490 }
6491 return true;
6492 };
6493
6494 switch (Opcode) {
6495 case X86::BLENDPDrmi:
6496 case X86::BLENDPDrri:
6497 case X86::VBLENDPDrmi:
6498 case X86::VBLENDPDrri:
6499 return SetBlendDomain(2, false);
6500 case X86::VBLENDPDYrmi:
6501 case X86::VBLENDPDYrri:
6502 return SetBlendDomain(4, true);
6503 case X86::BLENDPSrmi:
6504 case X86::BLENDPSrri:
6505 case X86::VBLENDPSrmi:
6506 case X86::VBLENDPSrri:
6507 case X86::VPBLENDDrmi:
6508 case X86::VPBLENDDrri:
6509 return SetBlendDomain(4, false);
6510 case X86::VBLENDPSYrmi:
6511 case X86::VBLENDPSYrri:
6512 case X86::VPBLENDDYrmi:
6513 case X86::VPBLENDDYrri:
6514 return SetBlendDomain(8, true);
6515 case X86::PBLENDWrmi:
6516 case X86::PBLENDWrri:
6517 case X86::VPBLENDWrmi:
6518 case X86::VPBLENDWrri:
6519 return SetBlendDomain(8, false);
6520 case X86::VPBLENDWYrmi:
6521 case X86::VPBLENDWYrri:
6522 return SetBlendDomain(16, true);
6523 case X86::VPANDDZ128rr: case X86::VPANDDZ128rm:
6524 case X86::VPANDDZ256rr: case X86::VPANDDZ256rm:
6525 case X86::VPANDQZ128rr: case X86::VPANDQZ128rm:
6526 case X86::VPANDQZ256rr: case X86::VPANDQZ256rm:
6527 case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6528 case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6529 case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6530 case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6531 case X86::VPORDZ128rr: case X86::VPORDZ128rm:
6532 case X86::VPORDZ256rr: case X86::VPORDZ256rm:
6533 case X86::VPORQZ128rr: case X86::VPORQZ128rm:
6534 case X86::VPORQZ256rr: case X86::VPORQZ256rm:
6535 case X86::VPXORDZ128rr: case X86::VPXORDZ128rm:
6536 case X86::VPXORDZ256rr: case X86::VPXORDZ256rm:
6537 case X86::VPXORQZ128rr: case X86::VPXORQZ128rm:
6538 case X86::VPXORQZ256rr: case X86::VPXORQZ256rm: {
6539 // Without DQI, convert EVEX instructions to VEX instructions.
6540 if (Subtarget.hasDQI())
6541 return false;
6542
6543 const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
6544 ReplaceableCustomAVX512LogicInstrs);
6545 assert(table && "Instruction not found in table?");
6546 // Don't change integer Q instructions to D instructions and
6547 // use D intructions if we started with a PS instruction.
6548 if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6549 Domain = 4;
6550 MI.setDesc(get(table[Domain - 1]));
6551 return true;
6552 }
6553 case X86::UNPCKHPDrr:
6554 case X86::MOVHLPSrr:
6555 // We just need to commute the instruction which will switch the domains.
6556 if (Domain != dom && Domain != 3 &&
6557 MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6558 MI.getOperand(0).getSubReg() == 0 &&
6559 MI.getOperand(1).getSubReg() == 0 &&
6560 MI.getOperand(2).getSubReg() == 0) {
6561 commuteInstruction(MI, false);
6562 return true;
6563 }
6564 // We must always return true for MOVHLPSrr.
6565 if (Opcode == X86::MOVHLPSrr)
6566 return true;
6567 break;
6568 case X86::SHUFPDrri: {
6569 if (Domain == 1) {
6570 unsigned Imm = MI.getOperand(3).getImm();
6571 unsigned NewImm = 0x44;
6572 if (Imm & 1) NewImm |= 0x0a;
6573 if (Imm & 2) NewImm |= 0xa0;
6574 MI.getOperand(3).setImm(NewImm);
6575 MI.setDesc(get(X86::SHUFPSrri));
6576 }
6577 return true;
6578 }
6579 }
6580 return false;
6581 }
6582
6583 std::pair<uint16_t, uint16_t>
6584 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
6585 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6586 unsigned opcode = MI.getOpcode();
6587 uint16_t validDomains = 0;
6588 if (domain) {
6589 // Attempt to match for custom instructions.
6590 validDomains = getExecutionDomainCustom(MI);
6591 if (validDomains)
6592 return std::make_pair(domain, validDomains);
6593
6594 if (lookup(opcode, domain, ReplaceableInstrs)) {
6595 validDomains = 0xe;
6596 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
6597 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
6598 } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
6599 validDomains = 0x6;
6600 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
6601 // Insert/extract instructions should only effect domain if AVX2
6602 // is enabled.
6603 if (!Subtarget.hasAVX2())
6604 return std::make_pair(0, 0);
6605 validDomains = 0xe;
6606 } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
6607 validDomains = 0xe;
6608 } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
6609 ReplaceableInstrsAVX512DQ)) {
6610 validDomains = 0xe;
6611 } else if (Subtarget.hasDQI()) {
6612 if (const uint16_t *table = lookupAVX512(opcode, domain,
6613 ReplaceableInstrsAVX512DQMasked)) {
6614 if (domain == 1 || (domain == 3 && table[3] == opcode))
6615 validDomains = 0xa;
6616 else
6617 validDomains = 0xc;
6618 }
6619 }
6620 }
6621 return std::make_pair(domain, validDomains);
6622 }
6623
6624 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
6625 assert(Domain>0 && Domain<4 && "Invalid execution domain");
6626 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6627 assert(dom && "Not an SSE instruction");
6628
6629 // Attempt to match for custom instructions.
6630 if (setExecutionDomainCustom(MI, Domain))
6631 return;
6632
6633 const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
6634 if (!table) { // try the other table
6635 assert((Subtarget.hasAVX2() || Domain < 3) &&
6636 "256-bit vector operations only available in AVX2");
6637 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
6638 }
6639 if (!table) { // try the FP table
6640 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
6641 assert((!table || Domain < 3) &&
6642 "Can only select PackedSingle or PackedDouble");
6643 }
6644 if (!table) { // try the other table
6645 assert(Subtarget.hasAVX2() &&
6646 "256-bit insert/extract only available in AVX2");
6647 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
6648 }
6649 if (!table) { // try the AVX512 table
6650 assert(Subtarget.hasAVX512() && "Requires AVX-512");
6651 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
6652 // Don't change integer Q instructions to D instructions.
6653 if (table && Domain == 3 && table[3] == MI.getOpcode())
6654 Domain = 4;
6655 }
6656 if (!table) { // try the AVX512DQ table
6657 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6658 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
6659 // Don't change integer Q instructions to D instructions and
6660 // use D intructions if we started with a PS instruction.
6661 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6662 Domain = 4;
6663 }
6664 if (!table) { // try the AVX512DQMasked table
6665 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6666 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
6667 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6668 Domain = 4;
6669 }
6670 assert(table && "Cannot change domain");
6671 MI.setDesc(get(table[Domain - 1]));
6672 }
6673
6674 /// Return the noop instruction to use for a noop.
6675 void X86InstrInfo::getNoop(MCInst &NopInst) const {
6676 NopInst.setOpcode(X86::NOOP);
6677 }
6678
6679 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6680 switch (opc) {
6681 default: return false;
6682 case X86::DIVPDrm:
6683 case X86::DIVPDrr:
6684 case X86::DIVPSrm:
6685 case X86::DIVPSrr:
6686 case X86::DIVSDrm:
6687 case X86::DIVSDrm_Int:
6688 case X86::DIVSDrr:
6689 case X86::DIVSDrr_Int:
6690 case X86::DIVSSrm:
6691 case X86::DIVSSrm_Int:
6692 case X86::DIVSSrr:
6693 case X86::DIVSSrr_Int:
6694 case X86::SQRTPDm:
6695 case X86::SQRTPDr:
6696 case X86::SQRTPSm:
6697 case X86::SQRTPSr:
6698 case X86::SQRTSDm:
6699 case X86::SQRTSDm_Int:
6700 case X86::SQRTSDr:
6701 case X86::SQRTSDr_Int:
6702 case X86::SQRTSSm:
6703 case X86::SQRTSSm_Int:
6704 case X86::SQRTSSr:
6705 case X86::SQRTSSr_Int:
6706 // AVX instructions with high latency
6707 case X86::VDIVPDrm:
6708 case X86::VDIVPDrr:
6709 case X86::VDIVPDYrm:
6710 case X86::VDIVPDYrr:
6711 case X86::VDIVPSrm:
6712 case X86::VDIVPSrr:
6713 case X86::VDIVPSYrm:
6714 case X86::VDIVPSYrr:
6715 case X86::VDIVSDrm:
6716 case X86::VDIVSDrm_Int:
6717 case X86::VDIVSDrr:
6718 case X86::VDIVSDrr_Int:
6719 case X86::VDIVSSrm:
6720 case X86::VDIVSSrm_Int:
6721 case X86::VDIVSSrr:
6722 case X86::VDIVSSrr_Int:
6723 case X86::VSQRTPDm:
6724 case X86::VSQRTPDr:
6725 case X86::VSQRTPDYm:
6726 case X86::VSQRTPDYr:
6727 case X86::VSQRTPSm:
6728 case X86::VSQRTPSr:
6729 case X86::VSQRTPSYm:
6730 case X86::VSQRTPSYr:
6731 case X86::VSQRTSDm:
6732 case X86::VSQRTSDm_Int:
6733 case X86::VSQRTSDr:
6734 case X86::VSQRTSDr_Int:
6735 case X86::VSQRTSSm:
6736 case X86::VSQRTSSm_Int:
6737 case X86::VSQRTSSr:
6738 case X86::VSQRTSSr_Int:
6739 // AVX512 instructions with high latency
6740 case X86::VDIVPDZ128rm:
6741 case X86::VDIVPDZ128rmb:
6742 case X86::VDIVPDZ128rmbk:
6743 case X86::VDIVPDZ128rmbkz:
6744 case X86::VDIVPDZ128rmk:
6745 case X86::VDIVPDZ128rmkz:
6746 case X86::VDIVPDZ128rr:
6747 case X86::VDIVPDZ128rrk:
6748 case X86::VDIVPDZ128rrkz:
6749 case X86::VDIVPDZ256rm:
6750 case X86::VDIVPDZ256rmb:
6751 case X86::VDIVPDZ256rmbk:
6752 case X86::VDIVPDZ256rmbkz:
6753 case X86::VDIVPDZ256rmk:
6754 case X86::VDIVPDZ256rmkz:
6755 case X86::VDIVPDZ256rr:
6756 case X86::VDIVPDZ256rrk:
6757 case X86::VDIVPDZ256rrkz:
6758 case X86::VDIVPDZrrb:
6759 case X86::VDIVPDZrrbk:
6760 case X86::VDIVPDZrrbkz:
6761 case X86::VDIVPDZrm:
6762 case X86::VDIVPDZrmb:
6763 case X86::VDIVPDZrmbk:
6764 case X86::VDIVPDZrmbkz:
6765 case X86::VDIVPDZrmk:
6766 case X86::VDIVPDZrmkz:
6767 case X86::VDIVPDZrr:
6768 case X86::VDIVPDZrrk:
6769 case X86::VDIVPDZrrkz:
6770 case X86::VDIVPSZ128rm:
6771 case X86::VDIVPSZ128rmb:
6772 case X86::VDIVPSZ128rmbk:
6773 case X86::VDIVPSZ128rmbkz:
6774 case X86::VDIVPSZ128rmk:
6775 case X86::VDIVPSZ128rmkz:
6776 case X86::VDIVPSZ128rr:
6777 case X86::VDIVPSZ128rrk:
6778 case X86::VDIVPSZ128rrkz:
6779 case X86::VDIVPSZ256rm:
6780 case X86::VDIVPSZ256rmb:
6781 case X86::VDIVPSZ256rmbk:
6782 case X86::VDIVPSZ256rmbkz:
6783 case X86::VDIVPSZ256rmk:
6784 case X86::VDIVPSZ256rmkz:
6785 case X86::VDIVPSZ256rr:
6786 case X86::VDIVPSZ256rrk:
6787 case X86::VDIVPSZ256rrkz:
6788 case X86::VDIVPSZrrb:
6789 case X86::VDIVPSZrrbk:
6790 case X86::VDIVPSZrrbkz:
6791 case X86::VDIVPSZrm:
6792 case X86::VDIVPSZrmb:
6793 case X86::VDIVPSZrmbk:
6794 case X86::VDIVPSZrmbkz:
6795 case X86::VDIVPSZrmk:
6796 case X86::VDIVPSZrmkz:
6797 case X86::VDIVPSZrr:
6798 case X86::VDIVPSZrrk:
6799 case X86::VDIVPSZrrkz:
6800 case X86::VDIVSDZrm:
6801 case X86::VDIVSDZrr:
6802 case X86::VDIVSDZrm_Int:
6803 case X86::VDIVSDZrm_Intk:
6804 case X86::VDIVSDZrm_Intkz:
6805 case X86::VDIVSDZrr_Int:
6806 case X86::VDIVSDZrr_Intk:
6807 case X86::VDIVSDZrr_Intkz:
6808 case X86::VDIVSDZrrb_Int:
6809 case X86::VDIVSDZrrb_Intk:
6810 case X86::VDIVSDZrrb_Intkz:
6811 case X86::VDIVSSZrm:
6812 case X86::VDIVSSZrr:
6813 case X86::VDIVSSZrm_Int:
6814 case X86::VDIVSSZrm_Intk:
6815 case X86::VDIVSSZrm_Intkz:
6816 case X86::VDIVSSZrr_Int:
6817 case X86::VDIVSSZrr_Intk:
6818 case X86::VDIVSSZrr_Intkz:
6819 case X86::VDIVSSZrrb_Int:
6820 case X86::VDIVSSZrrb_Intk:
6821 case X86::VDIVSSZrrb_Intkz:
6822 case X86::VSQRTPDZ128m:
6823 case X86::VSQRTPDZ128mb:
6824 case X86::VSQRTPDZ128mbk:
6825 case X86::VSQRTPDZ128mbkz:
6826 case X86::VSQRTPDZ128mk:
6827 case X86::VSQRTPDZ128mkz:
6828 case X86::VSQRTPDZ128r:
6829 case X86::VSQRTPDZ128rk:
6830 case X86::VSQRTPDZ128rkz:
6831 case X86::VSQRTPDZ256m:
6832 case X86::VSQRTPDZ256mb:
6833 case X86::VSQRTPDZ256mbk:
6834 case X86::VSQRTPDZ256mbkz:
6835 case X86::VSQRTPDZ256mk:
6836 case X86::VSQRTPDZ256mkz:
6837 case X86::VSQRTPDZ256r:
6838 case X86::VSQRTPDZ256rk:
6839 case X86::VSQRTPDZ256rkz:
6840 case X86::VSQRTPDZm:
6841 case X86::VSQRTPDZmb:
6842 case X86::VSQRTPDZmbk:
6843 case X86::VSQRTPDZmbkz:
6844 case X86::VSQRTPDZmk:
6845 case X86::VSQRTPDZmkz:
6846 case X86::VSQRTPDZr:
6847 case X86::VSQRTPDZrb:
6848 case X86::VSQRTPDZrbk:
6849 case X86::VSQRTPDZrbkz:
6850 case X86::VSQRTPDZrk:
6851 case X86::VSQRTPDZrkz:
6852 case X86::VSQRTPSZ128m:
6853 case X86::VSQRTPSZ128mb:
6854 case X86::VSQRTPSZ128mbk:
6855 case X86::VSQRTPSZ128mbkz:
6856 case X86::VSQRTPSZ128mk:
6857 case X86::VSQRTPSZ128mkz:
6858 case X86::VSQRTPSZ128r:
6859 case X86::VSQRTPSZ128rk:
6860 case X86::VSQRTPSZ128rkz:
6861 case X86::VSQRTPSZ256m:
6862 case X86::VSQRTPSZ256mb:
6863 case X86::VSQRTPSZ256mbk:
6864 case X86::VSQRTPSZ256mbkz:
6865 case X86::VSQRTPSZ256mk:
6866 case X86::VSQRTPSZ256mkz:
6867 case X86::VSQRTPSZ256r:
6868 case X86::VSQRTPSZ256rk:
6869 case X86::VSQRTPSZ256rkz:
6870 case X86::VSQRTPSZm:
6871 case X86::VSQRTPSZmb:
6872 case X86::VSQRTPSZmbk:
6873 case X86::VSQRTPSZmbkz:
6874 case X86::VSQRTPSZmk:
6875 case X86::VSQRTPSZmkz:
6876 case X86::VSQRTPSZr:
6877 case X86::VSQRTPSZrb:
6878 case X86::VSQRTPSZrbk:
6879 case X86::VSQRTPSZrbkz:
6880 case X86::VSQRTPSZrk:
6881 case X86::VSQRTPSZrkz:
6882 case X86::VSQRTSDZm:
6883 case X86::VSQRTSDZm_Int:
6884 case X86::VSQRTSDZm_Intk:
6885 case X86::VSQRTSDZm_Intkz:
6886 case X86::VSQRTSDZr:
6887 case X86::VSQRTSDZr_Int:
6888 case X86::VSQRTSDZr_Intk:
6889 case X86::VSQRTSDZr_Intkz:
6890 case X86::VSQRTSDZrb_Int:
6891 case X86::VSQRTSDZrb_Intk:
6892 case X86::VSQRTSDZrb_Intkz:
6893 case X86::VSQRTSSZm:
6894 case X86::VSQRTSSZm_Int:
6895 case X86::VSQRTSSZm_Intk:
6896 case X86::VSQRTSSZm_Intkz:
6897 case X86::VSQRTSSZr:
6898 case X86::VSQRTSSZr_Int:
6899 case X86::VSQRTSSZr_Intk:
6900 case X86::VSQRTSSZr_Intkz:
6901 case X86::VSQRTSSZrb_Int:
6902 case X86::VSQRTSSZrb_Intk:
6903 case X86::VSQRTSSZrb_Intkz:
6904
6905 case X86::VGATHERDPDYrm:
6906 case X86::VGATHERDPDZ128rm:
6907 case X86::VGATHERDPDZ256rm:
6908 case X86::VGATHERDPDZrm:
6909 case X86::VGATHERDPDrm:
6910 case X86::VGATHERDPSYrm:
6911 case X86::VGATHERDPSZ128rm:
6912 case X86::VGATHERDPSZ256rm:
6913 case X86::VGATHERDPSZrm:
6914 case X86::VGATHERDPSrm:
6915 case X86::VGATHERPF0DPDm:
6916 case X86::VGATHERPF0DPSm:
6917 case X86::VGATHERPF0QPDm:
6918 case X86::VGATHERPF0QPSm:
6919 case X86::VGATHERPF1DPDm:
6920 case X86::VGATHERPF1DPSm:
6921 case X86::VGATHERPF1QPDm:
6922 case X86::VGATHERPF1QPSm:
6923 case X86::VGATHERQPDYrm:
6924 case X86::VGATHERQPDZ128rm:
6925 case X86::VGATHERQPDZ256rm:
6926 case X86::VGATHERQPDZrm:
6927 case X86::VGATHERQPDrm:
6928 case X86::VGATHERQPSYrm:
6929 case X86::VGATHERQPSZ128rm:
6930 case X86::VGATHERQPSZ256rm:
6931 case X86::VGATHERQPSZrm:
6932 case X86::VGATHERQPSrm:
6933 case X86::VPGATHERDDYrm:
6934 case X86::VPGATHERDDZ128rm:
6935 case X86::VPGATHERDDZ256rm:
6936 case X86::VPGATHERDDZrm:
6937 case X86::VPGATHERDDrm:
6938 case X86::VPGATHERDQYrm:
6939 case X86::VPGATHERDQZ128rm:
6940 case X86::VPGATHERDQZ256rm:
6941 case X86::VPGATHERDQZrm:
6942 case X86::VPGATHERDQrm:
6943 case X86::VPGATHERQDYrm:
6944 case X86::VPGATHERQDZ128rm:
6945 case X86::VPGATHERQDZ256rm:
6946 case X86::VPGATHERQDZrm:
6947 case X86::VPGATHERQDrm:
6948 case X86::VPGATHERQQYrm:
6949 case X86::VPGATHERQQZ128rm:
6950 case X86::VPGATHERQQZ256rm:
6951 case X86::VPGATHERQQZrm:
6952 case X86::VPGATHERQQrm:
6953 case X86::VSCATTERDPDZ128mr:
6954 case X86::VSCATTERDPDZ256mr:
6955 case X86::VSCATTERDPDZmr:
6956 case X86::VSCATTERDPSZ128mr:
6957 case X86::VSCATTERDPSZ256mr:
6958 case X86::VSCATTERDPSZmr:
6959 case X86::VSCATTERPF0DPDm:
6960 case X86::VSCATTERPF0DPSm:
6961 case X86::VSCATTERPF0QPDm:
6962 case X86::VSCATTERPF0QPSm:
6963 case X86::VSCATTERPF1DPDm:
6964 case X86::VSCATTERPF1DPSm:
6965 case X86::VSCATTERPF1QPDm:
6966 case X86::VSCATTERPF1QPSm:
6967 case X86::VSCATTERQPDZ128mr:
6968 case X86::VSCATTERQPDZ256mr:
6969 case X86::VSCATTERQPDZmr:
6970 case X86::VSCATTERQPSZ128mr:
6971 case X86::VSCATTERQPSZ256mr:
6972 case X86::VSCATTERQPSZmr:
6973 case X86::VPSCATTERDDZ128mr:
6974 case X86::VPSCATTERDDZ256mr:
6975 case X86::VPSCATTERDDZmr:
6976 case X86::VPSCATTERDQZ128mr:
6977 case X86::VPSCATTERDQZ256mr:
6978 case X86::VPSCATTERDQZmr:
6979 case X86::VPSCATTERQDZ128mr:
6980 case X86::VPSCATTERQDZ256mr:
6981 case X86::VPSCATTERQDZmr:
6982 case X86::VPSCATTERQQZ128mr:
6983 case X86::VPSCATTERQQZ256mr:
6984 case X86::VPSCATTERQQZmr:
6985 return true;
6986 }
6987 }
6988
6989 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
6990 const MachineRegisterInfo *MRI,
6991 const MachineInstr &DefMI,
6992 unsigned DefIdx,
6993 const MachineInstr &UseMI,
6994 unsigned UseIdx) const {
6995 return isHighLatencyDef(DefMI.getOpcode());
6996 }
6997
6998 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
6999 const MachineBasicBlock *MBB) const {
7000 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7001 "Reassociation needs binary operators");
7002
7003 // Integer binary math/logic instructions have a third source operand:
7004 // the EFLAGS register. That operand must be both defined here and never
7005 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7006 // not change anything because rearranging the operands could affect other
7007 // instructions that depend on the exact status flags (zero, sign, etc.)
7008 // that are set by using these particular operands with this operation.
7009 if (Inst.getNumOperands() == 4) {
7010 assert(Inst.getOperand(3).isReg() &&
7011 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7012 "Unexpected operand in reassociable instruction");
7013 if (!Inst.getOperand(3).isDead())
7014 return false;
7015 }
7016
7017 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7018 }
7019
7020 // TODO: There are many more machine instruction opcodes to match:
7021 // 1. Other data types (integer, vectors)
7022 // 2. Other math / logic operations (xor, or)
7023 // 3. Other forms of the same operation (intrinsics and other variants)
7024 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7025 switch (Inst.getOpcode()) {
7026 case X86::AND8rr:
7027 case X86::AND16rr:
7028 case X86::AND32rr:
7029 case X86::AND64rr:
7030 case X86::OR8rr:
7031 case X86::OR16rr:
7032 case X86::OR32rr:
7033 case X86::OR64rr:
7034 case X86::XOR8rr:
7035 case X86::XOR16rr:
7036 case X86::XOR32rr:
7037 case X86::XOR64rr:
7038 case X86::IMUL16rr:
7039 case X86::IMUL32rr:
7040 case X86::IMUL64rr:
7041 case X86::PANDrr:
7042 case X86::PORrr:
7043 case X86::PXORrr:
7044 case X86::ANDPDrr:
7045 case X86::ANDPSrr:
7046 case X86::ORPDrr:
7047 case X86::ORPSrr:
7048 case X86::XORPDrr:
7049 case X86::XORPSrr:
7050 case X86::PADDBrr:
7051 case X86::PADDWrr:
7052 case X86::PADDDrr:
7053 case X86::PADDQrr:
7054 case X86::PMULLWrr:
7055 case X86::PMULLDrr:
7056 case X86::PMAXSBrr:
7057 case X86::PMAXSDrr:
7058 case X86::PMAXSWrr:
7059 case X86::PMAXUBrr:
7060 case X86::PMAXUDrr:
7061 case X86::PMAXUWrr:
7062 case X86::PMINSBrr:
7063 case X86::PMINSDrr:
7064 case X86::PMINSWrr:
7065 case X86::PMINUBrr:
7066 case X86::PMINUDrr:
7067 case X86::PMINUWrr:
7068 case X86::VPANDrr:
7069 case X86::VPANDYrr:
7070 case X86::VPANDDZ128rr:
7071 case X86::VPANDDZ256rr:
7072 case X86::VPANDDZrr:
7073 case X86::VPANDQZ128rr:
7074 case X86::VPANDQZ256rr:
7075 case X86::VPANDQZrr:
7076 case X86::VPORrr:
7077 case X86::VPORYrr:
7078 case X86::VPORDZ128rr:
7079 case X86::VPORDZ256rr:
7080 case X86::VPORDZrr:
7081 case X86::VPORQZ128rr:
7082 case X86::VPORQZ256rr:
7083 case X86::VPORQZrr:
7084 case X86::VPXORrr:
7085 case X86::VPXORYrr:
7086 case X86::VPXORDZ128rr:
7087 case X86::VPXORDZ256rr:
7088 case X86::VPXORDZrr:
7089 case X86::VPXORQZ128rr:
7090 case X86::VPXORQZ256rr:
7091 case X86::VPXORQZrr:
7092 case X86::VANDPDrr:
7093 case X86::VANDPSrr:
7094 case X86::VANDPDYrr:
7095 case X86::VANDPSYrr:
7096 case X86::VANDPDZ128rr:
7097 case X86::VANDPSZ128rr:
7098 case X86::VANDPDZ256rr:
7099 case X86::VANDPSZ256rr:
7100 case X86::VANDPDZrr:
7101 case X86::VANDPSZrr:
7102 case X86::VORPDrr:
7103 case X86::VORPSrr:
7104 case X86::VORPDYrr:
7105 case X86::VORPSYrr:
7106 case X86::VORPDZ128rr:
7107 case X86::VORPSZ128rr:
7108 case X86::VORPDZ256rr:
7109 case X86::VORPSZ256rr:
7110 case X86::VORPDZrr:
7111 case X86::VORPSZrr:
7112 case X86::VXORPDrr:
7113 case X86::VXORPSrr:
7114 case X86::VXORPDYrr:
7115 case X86::VXORPSYrr:
7116 case X86::VXORPDZ128rr:
7117 case X86::VXORPSZ128rr:
7118 case X86::VXORPDZ256rr:
7119 case X86::VXORPSZ256rr:
7120 case X86::VXORPDZrr:
7121 case X86::VXORPSZrr:
7122 case X86::KADDBrr:
7123 case X86::KADDWrr:
7124 case X86::KADDDrr:
7125 case X86::KADDQrr:
7126 case X86::KANDBrr:
7127 case X86::KANDWrr:
7128 case X86::KANDDrr:
7129 case X86::KANDQrr:
7130 case X86::KORBrr:
7131 case X86::KORWrr:
7132 case X86::KORDrr:
7133 case X86::KORQrr:
7134 case X86::KXORBrr:
7135 case X86::KXORWrr:
7136 case X86::KXORDrr:
7137 case X86::KXORQrr:
7138 case X86::VPADDBrr:
7139 case X86::VPADDWrr:
7140 case X86::VPADDDrr:
7141 case X86::VPADDQrr:
7142 case X86::VPADDBYrr:
7143 case X86::VPADDWYrr:
7144 case X86::VPADDDYrr:
7145 case X86::VPADDQYrr:
7146 case X86::VPADDBZ128rr:
7147 case X86::VPADDWZ128rr:
7148 case X86::VPADDDZ128rr:
7149 case X86::VPADDQZ128rr:
7150 case X86::VPADDBZ256rr:
7151 case X86::VPADDWZ256rr:
7152 case X86::VPADDDZ256rr:
7153 case X86::VPADDQZ256rr:
7154 case X86::VPADDBZrr:
7155 case X86::VPADDWZrr:
7156 case X86::VPADDDZrr:
7157 case X86::VPADDQZrr:
7158 case X86::VPMULLWrr:
7159 case X86::VPMULLWYrr:
7160 case X86::VPMULLWZ128rr:
7161 case X86::VPMULLWZ256rr:
7162 case X86::VPMULLWZrr:
7163 case X86::VPMULLDrr:
7164 case X86::VPMULLDYrr:
7165 case X86::VPMULLDZ128rr:
7166 case X86::VPMULLDZ256rr:
7167 case X86::VPMULLDZrr:
7168 case X86::VPMULLQZ128rr:
7169 case X86::VPMULLQZ256rr:
7170 case X86::VPMULLQZrr:
7171 case X86::VPMAXSBrr:
7172 case X86::VPMAXSBYrr:
7173 case X86::VPMAXSBZ128rr:
7174 case X86::VPMAXSBZ256rr:
7175 case X86::VPMAXSBZrr:
7176 case X86::VPMAXSDrr:
7177 case X86::VPMAXSDYrr:
7178 case X86::VPMAXSDZ128rr:
7179 case X86::VPMAXSDZ256rr:
7180 case X86::VPMAXSDZrr:
7181 case X86::VPMAXSQZ128rr:
7182 case X86::VPMAXSQZ256rr:
7183 case X86::VPMAXSQZrr:
7184 case X86::VPMAXSWrr:
7185 case X86::VPMAXSWYrr:
7186 case X86::VPMAXSWZ128rr:
7187 case X86::VPMAXSWZ256rr:
7188 case X86::VPMAXSWZrr:
7189 case X86::VPMAXUBrr:
7190 case X86::VPMAXUBYrr:
7191 case X86::VPMAXUBZ128rr:
7192 case X86::VPMAXUBZ256rr:
7193 case X86::VPMAXUBZrr:
7194 case X86::VPMAXUDrr:
7195 case X86::VPMAXUDYrr:
7196 case X86::VPMAXUDZ128rr:
7197 case X86::VPMAXUDZ256rr:
7198 case X86::VPMAXUDZrr:
7199 case X86::VPMAXUQZ128rr:
7200 case X86::VPMAXUQZ256rr:
7201 case X86::VPMAXUQZrr:
7202 case X86::VPMAXUWrr:
7203 case X86::VPMAXUWYrr:
7204 case X86::VPMAXUWZ128rr:
7205 case X86::VPMAXUWZ256rr:
7206 case X86::VPMAXUWZrr:
7207 case X86::VPMINSBrr:
7208 case X86::VPMINSBYrr:
7209 case X86::VPMINSBZ128rr:
7210 case X86::VPMINSBZ256rr:
7211 case X86::VPMINSBZrr:
7212 case X86::VPMINSDrr:
7213 case X86::VPMINSDYrr:
7214 case X86::VPMINSDZ128rr:
7215 case X86::VPMINSDZ256rr:
7216 case X86::VPMINSDZrr:
7217 case X86::VPMINSQZ128rr:
7218 case X86::VPMINSQZ256rr:
7219 case X86::VPMINSQZrr:
7220 case X86::VPMINSWrr:
7221 case X86::VPMINSWYrr:
7222 case X86::VPMINSWZ128rr:
7223 case X86::VPMINSWZ256rr:
7224 case X86::VPMINSWZrr:
7225 case X86::VPMINUBrr:
7226 case X86::VPMINUBYrr:
7227 case X86::VPMINUBZ128rr:
7228 case X86::VPMINUBZ256rr:
7229 case X86::VPMINUBZrr:
7230 case X86::VPMINUDrr:
7231 case X86::VPMINUDYrr:
7232 case X86::VPMINUDZ128rr:
7233 case X86::VPMINUDZ256rr:
7234 case X86::VPMINUDZrr:
7235 case X86::VPMINUQZ128rr:
7236 case X86::VPMINUQZ256rr:
7237 case X86::VPMINUQZrr:
7238 case X86::VPMINUWrr:
7239 case X86::VPMINUWYrr:
7240 case X86::VPMINUWZ128rr:
7241 case X86::VPMINUWZ256rr:
7242 case X86::VPMINUWZrr:
7243 // Normal min/max instructions are not commutative because of NaN and signed
7244 // zero semantics, but these are. Thus, there's no need to check for global
7245 // relaxed math; the instructions themselves have the properties we need.
7246 case X86::MAXCPDrr:
7247 case X86::MAXCPSrr:
7248 case X86::MAXCSDrr:
7249 case X86::MAXCSSrr:
7250 case X86::MINCPDrr:
7251 case X86::MINCPSrr:
7252 case X86::MINCSDrr:
7253 case X86::MINCSSrr:
7254 case X86::VMAXCPDrr:
7255 case X86::VMAXCPSrr:
7256 case X86::VMAXCPDYrr:
7257 case X86::VMAXCPSYrr:
7258 case X86::VMAXCPDZ128rr:
7259 case X86::VMAXCPSZ128rr:
7260 case X86::VMAXCPDZ256rr:
7261 case X86::VMAXCPSZ256rr:
7262 case X86::VMAXCPDZrr:
7263 case X86::VMAXCPSZrr:
7264 case X86::VMAXCSDrr:
7265 case X86::VMAXCSSrr:
7266 case X86::VMAXCSDZrr:
7267 case X86::VMAXCSSZrr:
7268 case X86::VMINCPDrr:
7269 case X86::VMINCPSrr:
7270 case X86::VMINCPDYrr:
7271 case X86::VMINCPSYrr:
7272 case X86::VMINCPDZ128rr:
7273 case X86::VMINCPSZ128rr:
7274 case X86::VMINCPDZ256rr:
7275 case X86::VMINCPSZ256rr:
7276 case X86::VMINCPDZrr:
7277 case X86::VMINCPSZrr:
7278 case X86::VMINCSDrr:
7279 case X86::VMINCSSrr:
7280 case X86::VMINCSDZrr:
7281 case X86::VMINCSSZrr:
7282 return true;
7283 case X86::ADDPDrr:
7284 case X86::ADDPSrr:
7285 case X86::ADDSDrr:
7286 case X86::ADDSSrr:
7287 case X86::MULPDrr:
7288 case X86::MULPSrr:
7289 case X86::MULSDrr:
7290 case X86::MULSSrr:
7291 case X86::VADDPDrr:
7292 case X86::VADDPSrr:
7293 case X86::VADDPDYrr:
7294 case X86::VADDPSYrr:
7295 case X86::VADDPDZ128rr:
7296 case X86::VADDPSZ128rr:
7297 case X86::VADDPDZ256rr:
7298 case X86::VADDPSZ256rr:
7299 case X86::VADDPDZrr:
7300 case X86::VADDPSZrr:
7301 case X86::VADDSDrr:
7302 case X86::VADDSSrr:
7303 case X86::VADDSDZrr:
7304 case X86::VADDSSZrr:
7305 case X86::VMULPDrr:
7306 case X86::VMULPSrr:
7307 case X86::VMULPDYrr:
7308 case X86::VMULPSYrr:
7309 case X86::VMULPDZ128rr:
7310 case X86::VMULPSZ128rr:
7311 case X86::VMULPDZ256rr:
7312 case X86::VMULPSZ256rr:
7313 case X86::VMULPDZrr:
7314 case X86::VMULPSZrr:
7315 case X86::VMULSDrr:
7316 case X86::VMULSSrr:
7317 case X86::VMULSDZrr:
7318 case X86::VMULSSZrr:
7319 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7320 default:
7321 return false;
7322 }
7323 }
7324
7325 /// This is an architecture-specific helper function of reassociateOps.
7326 /// Set special operand attributes for new instructions after reassociation.
7327 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7328 MachineInstr &OldMI2,
7329 MachineInstr &NewMI1,
7330 MachineInstr &NewMI2) const {
7331 // Integer instructions define an implicit EFLAGS source register operand as
7332 // the third source (fourth total) operand.
7333 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7334 return;
7335
7336 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7337 "Unexpected instruction type for reassociation");
7338
7339 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7340 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7341 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7342 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7343
7344 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7345 "Must have dead EFLAGS operand in reassociable instruction");
7346 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7347 "Must have dead EFLAGS operand in reassociable instruction");
7348
7349 (void)OldOp1;
7350 (void)OldOp2;
7351
7352 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7353 "Unexpected operand in reassociable instruction");
7354 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7355 "Unexpected operand in reassociable instruction");
7356
7357 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7358 // of this pass or other passes. The EFLAGS operands must be dead in these new
7359 // instructions because the EFLAGS operands in the original instructions must
7360 // be dead in order for reassociation to occur.
7361 NewOp1.setIsDead();
7362 NewOp2.setIsDead();
7363 }
7364
7365 std::pair<unsigned, unsigned>
7366 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7367 return std::make_pair(TF, 0u);
7368 }
7369
7370 ArrayRef<std::pair<unsigned, const char *>>
7371 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7372 using namespace X86II;
7373 static const std::pair<unsigned, const char *> TargetFlags[] = {
7374 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7375 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7376 {MO_GOT, "x86-got"},
7377 {MO_GOTOFF, "x86-gotoff"},
7378 {MO_GOTPCREL, "x86-gotpcrel"},
7379 {MO_PLT, "x86-plt"},
7380 {MO_TLSGD, "x86-tlsgd"},
7381 {MO_TLSLD, "x86-tlsld"},
7382 {MO_TLSLDM, "x86-tlsldm"},
7383 {MO_GOTTPOFF, "x86-gottpoff"},
7384 {MO_INDNTPOFF, "x86-indntpoff"},
7385 {MO_TPOFF, "x86-tpoff"},
7386 {MO_DTPOFF, "x86-dtpoff"},
7387 {MO_NTPOFF, "x86-ntpoff"},
7388 {MO_GOTNTPOFF, "x86-gotntpoff"},
7389 {MO_DLLIMPORT, "x86-dllimport"},
7390 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7391 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7392 {MO_TLVP, "x86-tlvp"},
7393 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7394 {MO_SECREL, "x86-secrel"},
7395 {MO_COFFSTUB, "x86-coffstub"}};
7396 return makeArrayRef(TargetFlags);
7397 }
7398
7399 namespace {
7400 /// Create Global Base Reg pass. This initializes the PIC
7401 /// global base register for x86-32.
7402 struct CGBR : public MachineFunctionPass {
7403 static char ID;
7404 CGBR() : MachineFunctionPass(ID) {}
7405
7406 bool runOnMachineFunction(MachineFunction &MF) override {
7407 const X86TargetMachine *TM =
7408 static_cast<const X86TargetMachine *>(&MF.getTarget());
7409 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7410
7411 // Don't do anything in the 64-bit small and kernel code models. They use
7412 // RIP-relative addressing for everything.
7413 if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
7414 TM->getCodeModel() == CodeModel::Kernel))
7415 return false;
7416
7417 // Only emit a global base reg in PIC mode.
7418 if (!TM->isPositionIndependent())
7419 return false;
7420
7421 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7422 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7423
7424 // If we didn't need a GlobalBaseReg, don't insert code.
7425 if (GlobalBaseReg == 0)
7426 return false;
7427
7428 // Insert the set of GlobalBaseReg into the first MBB of the function
7429 MachineBasicBlock &FirstMBB = MF.front();
7430 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7431 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7432 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7433 const X86InstrInfo *TII = STI.getInstrInfo();
7434
7435 unsigned PC;
7436 if (STI.isPICStyleGOT())
7437 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7438 else
7439 PC = GlobalBaseReg;
7440
7441 if (STI.is64Bit()) {
7442 if (TM->getCodeModel() == CodeModel::Medium) {
7443 // In the medium code model, use a RIP-relative LEA to materialize the
7444 // GOT.
7445 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
7446 .addReg(X86::RIP)
7447 .addImm(0)
7448 .addReg(0)
7449 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
7450 .addReg(0);
7451 } else if (TM->getCodeModel() == CodeModel::Large) {
7452 // In the large code model, we are aiming for this code, though the
7453 // register allocation may vary:
7454 // leaq .LN$pb(%rip), %rax
7455 // movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
7456 // addq %rcx, %rax
7457 // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
7458 unsigned PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7459 unsigned GOTReg =
7460 RegInfo.createVirtualRegister(&X86::GR64RegClass);
7461 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
7462 .addReg(X86::RIP)
7463 .addImm(0)
7464 .addReg(0)
7465 .addSym(MF.getPICBaseSymbol())
7466 .addReg(0);
7467 std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
7468 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
7469 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7470 X86II::MO_PIC_BASE_OFFSET);
7471 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
7472 .addReg(PBReg, RegState::Kill)
7473 .addReg(GOTReg, RegState::Kill);
7474 } else {
7475 llvm_unreachable("unexpected code model");
7476 }
7477 } else {
7478 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7479 // only used in JIT code emission as displacement to pc.
7480 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7481
7482 // If we're using vanilla 'GOT' PIC style, we should use relative
7483 // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7484 if (STI.isPICStyleGOT()) {
7485 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
7486 // %some_register
7487 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7488 .addReg(PC)
7489 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7490 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7491 }
7492 }
7493
7494 return true;
7495 }
7496
7497 StringRef getPassName() const override {
7498 return "X86 PIC Global Base Reg Initialization";
7499 }
7500
7501 void getAnalysisUsage(AnalysisUsage &AU) const override {
7502 AU.setPreservesCFG();
7503 MachineFunctionPass::getAnalysisUsage(AU);
7504 }
7505 };
7506 }
7507
7508 char CGBR::ID = 0;
7509 FunctionPass*
7510 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7511
7512 namespace {
7513 struct LDTLSCleanup : public MachineFunctionPass {
7514 static char ID;
7515 LDTLSCleanup() : MachineFunctionPass(ID) {}
7516
7517 bool runOnMachineFunction(MachineFunction &MF) override {
7518 if (skipFunction(MF.getFunction()))
7519 return false;
7520
7521 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7522 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7523 // No point folding accesses if there isn't at least two.
7524 return false;
7525 }
7526
7527 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7528 return VisitNode(DT->getRootNode(), 0);
7529 }
7530
7531 // Visit the dominator subtree rooted at Node in pre-order.
7532 // If TLSBaseAddrReg is non-null, then use that to replace any
7533 // TLS_base_addr instructions. Otherwise, create the register
7534 // when the first such instruction is seen, and then use it
7535 // as we encounter more instructions.
7536 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7537 MachineBasicBlock *BB = Node->getBlock();
7538 bool Changed = false;
7539
7540 // Traverse the current block.
7541 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7542 ++I) {
7543 switch (I->getOpcode()) {
7544 case X86::TLS_base_addr32:
7545 case X86::TLS_base_addr64:
7546 if (TLSBaseAddrReg)
7547 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
7548 else
7549 I = SetRegister(*I, &TLSBaseAddrReg);
7550 Changed = true;
7551 break;
7552 default:
7553 break;
7554 }
7555 }
7556
7557 // Visit the children of this block in the dominator tree.
7558 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7559 I != E; ++I) {
7560 Changed |= VisitNode(*I, TLSBaseAddrReg);
7561 }
7562
7563 return Changed;
7564 }
7565
7566 // Replace the TLS_base_addr instruction I with a copy from
7567 // TLSBaseAddrReg, returning the new instruction.
7568 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
7569 unsigned TLSBaseAddrReg) {
7570 MachineFunction *MF = I.getParent()->getParent();
7571 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7572 const bool is64Bit = STI.is64Bit();
7573 const X86InstrInfo *TII = STI.getInstrInfo();
7574
7575 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7576 MachineInstr *Copy =
7577 BuildMI(*I.getParent(), I, I.getDebugLoc(),
7578 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7579 .addReg(TLSBaseAddrReg);
7580
7581 // Erase the TLS_base_addr instruction.
7582 I.eraseFromParent();
7583
7584 return Copy;
7585 }
7586
7587 // Create a virtual register in *TLSBaseAddrReg, and populate it by
7588 // inserting a copy instruction after I. Returns the new instruction.
7589 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
7590 MachineFunction *MF = I.getParent()->getParent();
7591 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7592 const bool is64Bit = STI.is64Bit();
7593 const X86InstrInfo *TII = STI.getInstrInfo();
7594
7595 // Create a virtual register for the TLS base address.
7596 MachineRegisterInfo &RegInfo = MF->getRegInfo();
7597 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7598 ? &X86::GR64RegClass
7599 : &X86::GR32RegClass);
7600
7601 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7602 MachineInstr *Next = I.getNextNode();
7603 MachineInstr *Copy =
7604 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
7605 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
7606 .addReg(is64Bit ? X86::RAX : X86::EAX);
7607
7608 return Copy;
7609 }
7610
7611 StringRef getPassName() const override {
7612 return "Local Dynamic TLS Access Clean-up";
7613 }
7614
7615 void getAnalysisUsage(AnalysisUsage &AU) const override {
7616 AU.setPreservesCFG();
7617 AU.addRequired<MachineDominatorTree>();
7618 MachineFunctionPass::getAnalysisUsage(AU);
7619 }
7620 };
7621 }
7622
7623 char LDTLSCleanup::ID = 0;
7624 FunctionPass*
7625 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7626
7627 /// Constants defining how certain sequences should be outlined.
7628 ///
7629 /// \p MachineOutlinerDefault implies that the function is called with a call
7630 /// instruction, and a return must be emitted for the outlined function frame.
7631 ///
7632 /// That is,
7633 ///
7634 /// I1 OUTLINED_FUNCTION:
7635 /// I2 --> call OUTLINED_FUNCTION I1
7636 /// I3 I2
7637 /// I3
7638 /// ret
7639 ///
7640 /// * Call construction overhead: 1 (call instruction)
7641 /// * Frame construction overhead: 1 (return instruction)
7642 ///
7643 /// \p MachineOutlinerTailCall implies that the function is being tail called.
7644 /// A jump is emitted instead of a call, and the return is already present in
7645 /// the outlined sequence. That is,
7646 ///
7647 /// I1 OUTLINED_FUNCTION:
7648 /// I2 --> jmp OUTLINED_FUNCTION I1
7649 /// ret I2
7650 /// ret
7651 ///
7652 /// * Call construction overhead: 1 (jump instruction)
7653 /// * Frame construction overhead: 0 (don't need to return)
7654 ///
7655 enum MachineOutlinerClass {
7656 MachineOutlinerDefault,
7657 MachineOutlinerTailCall
7658 };
7659
7660 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
7661 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
7662 unsigned SequenceSize =
7663 std::accumulate(RepeatedSequenceLocs[0].front(),
7664 std::next(RepeatedSequenceLocs[0].back()), 0,
7665 [](unsigned Sum, const MachineInstr &MI) {
7666 // FIXME: x86 doesn't implement getInstSizeInBytes, so
7667 // we can't tell the cost. Just assume each instruction
7668 // is one byte.
7669 if (MI.isDebugInstr() || MI.isKill())
7670 return Sum;
7671 return Sum + 1;
7672 });
7673
7674 // FIXME: Use real size in bytes for call and ret instructions.
7675 if (RepeatedSequenceLocs[0].back()->isTerminator()) {
7676 for (outliner::Candidate &C : RepeatedSequenceLocs)
7677 C.setCallInfo(MachineOutlinerTailCall, 1);
7678
7679 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
7680 0, // Number of bytes to emit frame.
7681 MachineOutlinerTailCall // Type of frame.
7682 );
7683 }
7684
7685 for (outliner::Candidate &C : RepeatedSequenceLocs)
7686 C.setCallInfo(MachineOutlinerDefault, 1);
7687
7688 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
7689 MachineOutlinerDefault);
7690 }
7691
7692 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
7693 bool OutlineFromLinkOnceODRs) const {
7694 const Function &F = MF.getFunction();
7695
7696 // Does the function use a red zone? If it does, then we can't risk messing
7697 // with the stack.
7698 if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
7699 // It could have a red zone. If it does, then we don't want to touch it.
7700 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7701 if (!X86FI || X86FI->getUsesRedZone())
7702 return false;
7703 }
7704
7705 // If we *don't* want to outline from things that could potentially be deduped
7706 // then return false.
7707 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
7708 return false;
7709
7710 // This function is viable for outlining, so return true.
7711 return true;
7712 }
7713
7714 outliner::InstrType
7715 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
7716 MachineInstr &MI = *MIT;
7717 // Don't allow debug values to impact outlining type.
7718 if (MI.isDebugInstr() || MI.isIndirectDebugValue())
7719 return outliner::InstrType::Invisible;
7720
7721 // At this point, KILL instructions don't really tell us much so we can go
7722 // ahead and skip over them.
7723 if (MI.isKill())
7724 return outliner::InstrType::Invisible;
7725
7726 // Is this a tail call? If yes, we can outline as a tail call.
7727 if (isTailCall(MI))
7728 return outliner::InstrType::Legal;
7729
7730 // Is this the terminator of a basic block?
7731 if (MI.isTerminator() || MI.isReturn()) {
7732
7733 // Does its parent have any successors in its MachineFunction?
7734 if (MI.getParent()->succ_empty())
7735 return outliner::InstrType::Legal;
7736
7737 // It does, so we can't tail call it.
7738 return outliner::InstrType::Illegal;
7739 }
7740
7741 // Don't outline anything that modifies or reads from the stack pointer.
7742 //
7743 // FIXME: There are instructions which are being manually built without
7744 // explicit uses/defs so we also have to check the MCInstrDesc. We should be
7745 // able to remove the extra checks once those are fixed up. For example,
7746 // sometimes we might get something like %rax = POP64r 1. This won't be
7747 // caught by modifiesRegister or readsRegister even though the instruction
7748 // really ought to be formed so that modifiesRegister/readsRegister would
7749 // catch it.
7750 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
7751 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
7752 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
7753 return outliner::InstrType::Illegal;
7754
7755 // Outlined calls change the instruction pointer, so don't read from it.
7756 if (MI.readsRegister(X86::RIP, &RI) ||
7757 MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
7758 MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
7759 return outliner::InstrType::Illegal;
7760
7761 // Positions can't safely be outlined.
7762 if (MI.isPosition())
7763 return outliner::InstrType::Illegal;
7764
7765 // Make sure none of the operands of this instruction do anything tricky.
7766 for (const MachineOperand &MOP : MI.operands())
7767 if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
7768 MOP.isTargetIndex())
7769 return outliner::InstrType::Illegal;
7770
7771 return outliner::InstrType::Legal;
7772 }
7773
7774 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
7775 MachineFunction &MF,
7776 const outliner::OutlinedFunction &OF)
7777 const {
7778 // If we're a tail call, we already have a return, so don't do anything.
7779 if (OF.FrameConstructionID == MachineOutlinerTailCall)
7780 return;
7781
7782 // We're a normal call, so our sequence doesn't have a return instruction.
7783 // Add it in.
7784 MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
7785 MBB.insert(MBB.end(), retq);
7786 }
7787
7788 MachineBasicBlock::iterator
7789 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
7790 MachineBasicBlock::iterator &It,
7791 MachineFunction &MF,
7792 const outliner::Candidate &C) const {
7793 // Is it a tail call?
7794 if (C.CallConstructionID == MachineOutlinerTailCall) {
7795 // Yes, just insert a JMP.
7796 It = MBB.insert(It,
7797 BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
7798 .addGlobalAddress(M.getNamedValue(MF.getName())));
7799 } else {
7800 // No, insert a call.
7801 It = MBB.insert(It,
7802 BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
7803 .addGlobalAddress(M.getNamedValue(MF.getName())));
7804 }
7805
7806 return It;
7807 }
7808
7809 #define GET_INSTRINFO_HELPERS
7810 #include "X86GenInstrInfo.inc"
The low level virtual machine