[LLVM][Alignment] Make functions using log of alignment explicit
commit016621df0e8772868e7751cdf494734b8bb64cd7
authorGuillaume Chatelet <gchatelet@google.com>
Thu, 5 Sep 2019 10:00:22 +0000 (5 10:00 +0000)
committerGuillaume Chatelet <gchatelet@google.com>
Thu, 5 Sep 2019 10:00:22 +0000 (5 10:00 +0000)
tree4fff87636d97c941e96b0cfd60b24d045d45e334
parentb04700fbb2b729f1bdfa05914f6f535f1f3b16c7
[LLVM][Alignment] Make functions using log of alignment explicit

Summary:
This patch renames functions that takes or returns alignment as log2, this patch will help with the transition to llvm::Align.
The renaming makes it explicit that we deal with log(alignment) instead of a power of two alignment.
A few renames uncovered dubious assignments:

 - `MirParser`/`MirPrinter` was expecting powers of two but `MachineFunction` and `MachineBasicBlock` were using deal with log2(align). This patch fixes it and updates the documentation.
 - `MachineBlockPlacement` exposes two flags (`align-all-blocks` and `align-all-nofallthru-blocks`) supposedly interpreted as power of two alignments, internally these values are interpreted as log2(align). This patch updates the documentation,
 - `MachineFunctionexposes` exposes `align-all-functions` also interpreted as power of two alignment, internally this value is interpreted as log2(align). This patch updates the documentation,

Reviewers: lattner, thegameg, courbet

Subscribers: dschuff, arsenm, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, dexonsmith, PkmX, jocewei, jsji, Jim, s.egerton, llvm-commits, courbet

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65945

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371045 91177308-0d34-0410-b5e6-96231b3b80d8
61 files changed:
docs/MIRLangRef.rst
include/llvm/CodeGen/MachineBasicBlock.h
include/llvm/CodeGen/MachineFunction.h
include/llvm/CodeGen/TargetLowering.h
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/CodeGen/AsmPrinter/WinException.cpp
lib/CodeGen/BranchRelaxation.cpp
lib/CodeGen/MIRParser/MIParser.cpp
lib/CodeGen/MIRParser/MIRParser.cpp
lib/CodeGen/MIRPrinter.cpp
lib/CodeGen/MachineBasicBlock.cpp
lib/CodeGen/MachineBlockPlacement.cpp
lib/CodeGen/MachineFunction.cpp
lib/CodeGen/PatchableFunction.cpp
lib/CodeGen/TargetLoweringBase.cpp
lib/Target/AArch64/AArch64ISelLowering.cpp
lib/Target/AArch64/AArch64Subtarget.cpp
lib/Target/AArch64/AArch64Subtarget.h
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
lib/Target/AMDGPU/R600AsmPrinter.cpp
lib/Target/AMDGPU/SIISelLowering.cpp
lib/Target/AMDGPU/SIISelLowering.h
lib/Target/ARC/ARCMachineFunctionInfo.h
lib/Target/ARM/ARM.td
lib/Target/ARM/ARMBasicBlockInfo.cpp
lib/Target/ARM/ARMConstantIslandPass.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMSubtarget.cpp
lib/Target/ARM/ARMSubtarget.h
lib/Target/AVR/AVRISelLowering.cpp
lib/Target/BPF/BPFISelLowering.cpp
lib/Target/Hexagon/HexagonBranchRelaxation.cpp
lib/Target/Hexagon/HexagonFixupHwLoops.cpp
lib/Target/Hexagon/HexagonISelLowering.cpp
lib/Target/Lanai/LanaiISelLowering.cpp
lib/Target/MSP430/MSP430ISelLowering.cpp
lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
lib/Target/Mips/MipsAsmPrinter.cpp
lib/Target/Mips/MipsBranchExpansion.cpp
lib/Target/Mips/MipsConstantIslandPass.cpp
lib/Target/Mips/MipsISelLowering.cpp
lib/Target/PowerPC/PPCBranchSelector.cpp
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCISelLowering.h
lib/Target/RISCV/RISCVISelLowering.cpp
lib/Target/Sparc/SparcISelLowering.cpp
lib/Target/SystemZ/SystemZISelLowering.cpp
lib/Target/SystemZ/SystemZLongBranch.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86RetpolineThunks.cpp
lib/Target/XCore/XCoreISelLowering.cpp
test/CodeGen/ARM/constant-island-movwt.mir
test/CodeGen/ARM/fp16-litpool-arm.mir
test/CodeGen/ARM/fp16-litpool-thumb.mir
test/CodeGen/ARM/fp16-litpool2-arm.mir
test/CodeGen/ARM/fp16-litpool3-arm.mir
test/CodeGen/Mips/unaligned-memops-mapping.mir
test/CodeGen/PowerPC/block-placement.mir
test/CodeGen/X86/tail-merge-after-mbp.mir
test/DebugInfo/X86/debug-loc-offset.mir