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[LLVM][Alignment] Make functions using log of alignment explicit
[llvm-complete.git] / lib / CodeGen / TargetLoweringBase.cpp
blob970b2067d4258d66705d20d58d0ddc52bbb7bab0
1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/ISDOpcodes.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/RuntimeLibcalls.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/CodeGen/TargetLowering.h"
33 #include "llvm/CodeGen/TargetOpcodes.h"
34 #include "llvm/CodeGen/TargetRegisterInfo.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalValue.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/IRBuilder.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
46 #include "llvm/Support/BranchProbability.h"
47 #include "llvm/Support/Casting.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MachineValueType.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include <algorithm>
55 #include <cassert>
56 #include <cstddef>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <tuple>
62 #include <utility>
63
64 using namespace llvm;
65
66 static cl::opt<bool> JumpIsExpensiveOverride(
67 "jump-is-expensive", cl::init(false),
68 cl::desc("Do not create extra branches to split comparison logic."),
69 cl::Hidden);
70
71 static cl::opt<unsigned> MinimumJumpTableEntries
72 ("min-jump-table-entries", cl::init(4), cl::Hidden,
73 cl::desc("Set minimum number of entries to use a jump table."));
74
75 static cl::opt<unsigned> MaximumJumpTableSize
76 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
77 cl::desc("Set maximum size of jump tables."));
78
79 /// Minimum jump table density for normal functions.
80 static cl::opt<unsigned>
81 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
82 cl::desc("Minimum density for building a jump table in "
83 "a normal function"));
84
85 /// Minimum jump table density for -Os or -Oz functions.
86 static cl::opt<unsigned> OptsizeJumpTableDensity(
87 "optsize-jump-table-density", cl::init(40), cl::Hidden,
88 cl::desc("Minimum density for building a jump table in "
89 "an optsize function"));
90
91 static bool darwinHasSinCos(const Triple &TT) {
92 assert(TT.isOSDarwin() && "should be called with darwin triple");
93 // Don't bother with 32 bit x86.
94 if (TT.getArch() == Triple::x86)
95 return false;
96 // Macos < 10.9 has no sincos_stret.
97 if (TT.isMacOSX())
98 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
99 // iOS < 7.0 has no sincos_stret.
100 if (TT.isiOS())
101 return !TT.isOSVersionLT(7, 0);
102 // Any other darwin such as WatchOS/TvOS is new enough.
103 return true;
104 }
105
106 // Although this default value is arbitrary, it is not random. It is assumed
107 // that a condition that evaluates the same way by a higher percentage than this
108 // is best represented as control flow. Therefore, the default value N should be
109 // set such that the win from N% correct executions is greater than the loss
110 // from (100 - N)% mispredicted executions for the majority of intended targets.
111 static cl::opt<int> MinPercentageForPredictableBranch(
112 "min-predictable-branch", cl::init(99),
113 cl::desc("Minimum percentage (0-100) that a condition must be either true "
114 "or false to assume that the condition is predictable"),
115 cl::Hidden);
116
117 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
118 #define HANDLE_LIBCALL(code, name) \
119 setLibcallName(RTLIB::code, name);
120 #include "llvm/IR/RuntimeLibcalls.def"
121 #undef HANDLE_LIBCALL
122 // Initialize calling conventions to their default.
123 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
124 setLibcallCallingConv((RTLIB::Libcall)LC, CallingConv::C);
125
126 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
127 if (TT.getArch() == Triple::ppc || TT.isPPC64()) {
128 setLibcallName(RTLIB::ADD_F128, "__addkf3");
129 setLibcallName(RTLIB::SUB_F128, "__subkf3");
130 setLibcallName(RTLIB::MUL_F128, "__mulkf3");
131 setLibcallName(RTLIB::DIV_F128, "__divkf3");
132 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
133 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
134 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
135 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
136 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
137 setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
138 setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
139 setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
140 setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
141 setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
142 setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
143 setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
144 setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
145 setLibcallName(RTLIB::UNE_F128, "__nekf2");
146 setLibcallName(RTLIB::OGE_F128, "__gekf2");
147 setLibcallName(RTLIB::OLT_F128, "__ltkf2");
148 setLibcallName(RTLIB::OLE_F128, "__lekf2");
149 setLibcallName(RTLIB::OGT_F128, "__gtkf2");
150 setLibcallName(RTLIB::UO_F128, "__unordkf2");
151 setLibcallName(RTLIB::O_F128, "__unordkf2");
152 }
153
154 // A few names are different on particular architectures or environments.
155 if (TT.isOSDarwin()) {
156 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
157 // of the gnueabi-style __gnu_*_ieee.
158 // FIXME: What about other targets?
159 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
160 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
161
162 // Some darwins have an optimized __bzero/bzero function.
163 switch (TT.getArch()) {
164 case Triple::x86:
165 case Triple::x86_64:
166 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
167 setLibcallName(RTLIB::BZERO, "__bzero");
168 break;
169 case Triple::aarch64:
170 setLibcallName(RTLIB::BZERO, "bzero");
171 break;
172 default:
173 break;
174 }
175
176 if (darwinHasSinCos(TT)) {
177 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
178 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
179 if (TT.isWatchABI()) {
180 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
181 CallingConv::ARM_AAPCS_VFP);
182 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
183 CallingConv::ARM_AAPCS_VFP);
184 }
185 }
186 } else {
187 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
188 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
189 }
190
191 if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
192 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
193 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
194 setLibcallName(RTLIB::SINCOS_F64, "sincos");
195 setLibcallName(RTLIB::SINCOS_F80, "sincosl");
196 setLibcallName(RTLIB::SINCOS_F128, "sincosl");
197 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
198 }
199
200 if (TT.isPS4CPU()) {
201 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
202 setLibcallName(RTLIB::SINCOS_F64, "sincos");
203 }
204
205 if (TT.isOSOpenBSD()) {
206 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
207 }
208 }
209
210 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
211 /// UNKNOWN_LIBCALL if there is none.
212 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
213 if (OpVT == MVT::f16) {
214 if (RetVT == MVT::f32)
215 return FPEXT_F16_F32;
216 } else if (OpVT == MVT::f32) {
217 if (RetVT == MVT::f64)
218 return FPEXT_F32_F64;
219 if (RetVT == MVT::f128)
220 return FPEXT_F32_F128;
221 if (RetVT == MVT::ppcf128)
222 return FPEXT_F32_PPCF128;
223 } else if (OpVT == MVT::f64) {
224 if (RetVT == MVT::f128)
225 return FPEXT_F64_F128;
226 else if (RetVT == MVT::ppcf128)
227 return FPEXT_F64_PPCF128;
228 } else if (OpVT == MVT::f80) {
229 if (RetVT == MVT::f128)
230 return FPEXT_F80_F128;
231 }
232
233 return UNKNOWN_LIBCALL;
234 }
235
236 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
237 /// UNKNOWN_LIBCALL if there is none.
238 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
239 if (RetVT == MVT::f16) {
240 if (OpVT == MVT::f32)
241 return FPROUND_F32_F16;
242 if (OpVT == MVT::f64)
243 return FPROUND_F64_F16;
244 if (OpVT == MVT::f80)
245 return FPROUND_F80_F16;
246 if (OpVT == MVT::f128)
247 return FPROUND_F128_F16;
248 if (OpVT == MVT::ppcf128)
249 return FPROUND_PPCF128_F16;
250 } else if (RetVT == MVT::f32) {
251 if (OpVT == MVT::f64)
252 return FPROUND_F64_F32;
253 if (OpVT == MVT::f80)
254 return FPROUND_F80_F32;
255 if (OpVT == MVT::f128)
256 return FPROUND_F128_F32;
257 if (OpVT == MVT::ppcf128)
258 return FPROUND_PPCF128_F32;
259 } else if (RetVT == MVT::f64) {
260 if (OpVT == MVT::f80)
261 return FPROUND_F80_F64;
262 if (OpVT == MVT::f128)
263 return FPROUND_F128_F64;
264 if (OpVT == MVT::ppcf128)
265 return FPROUND_PPCF128_F64;
266 } else if (RetVT == MVT::f80) {
267 if (OpVT == MVT::f128)
268 return FPROUND_F128_F80;
269 }
270
271 return UNKNOWN_LIBCALL;
272 }
273
274 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
275 /// UNKNOWN_LIBCALL if there is none.
276 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
277 if (OpVT == MVT::f32) {
278 if (RetVT == MVT::i32)
279 return FPTOSINT_F32_I32;
280 if (RetVT == MVT::i64)
281 return FPTOSINT_F32_I64;
282 if (RetVT == MVT::i128)
283 return FPTOSINT_F32_I128;
284 } else if (OpVT == MVT::f64) {
285 if (RetVT == MVT::i32)
286 return FPTOSINT_F64_I32;
287 if (RetVT == MVT::i64)
288 return FPTOSINT_F64_I64;
289 if (RetVT == MVT::i128)
290 return FPTOSINT_F64_I128;
291 } else if (OpVT == MVT::f80) {
292 if (RetVT == MVT::i32)
293 return FPTOSINT_F80_I32;
294 if (RetVT == MVT::i64)
295 return FPTOSINT_F80_I64;
296 if (RetVT == MVT::i128)
297 return FPTOSINT_F80_I128;
298 } else if (OpVT == MVT::f128) {
299 if (RetVT == MVT::i32)
300 return FPTOSINT_F128_I32;
301 if (RetVT == MVT::i64)
302 return FPTOSINT_F128_I64;
303 if (RetVT == MVT::i128)
304 return FPTOSINT_F128_I128;
305 } else if (OpVT == MVT::ppcf128) {
306 if (RetVT == MVT::i32)
307 return FPTOSINT_PPCF128_I32;
308 if (RetVT == MVT::i64)
309 return FPTOSINT_PPCF128_I64;
310 if (RetVT == MVT::i128)
311 return FPTOSINT_PPCF128_I128;
312 }
313 return UNKNOWN_LIBCALL;
314 }
315
316 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
317 /// UNKNOWN_LIBCALL if there is none.
318 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
319 if (OpVT == MVT::f32) {
320 if (RetVT == MVT::i32)
321 return FPTOUINT_F32_I32;
322 if (RetVT == MVT::i64)
323 return FPTOUINT_F32_I64;
324 if (RetVT == MVT::i128)
325 return FPTOUINT_F32_I128;
326 } else if (OpVT == MVT::f64) {
327 if (RetVT == MVT::i32)
328 return FPTOUINT_F64_I32;
329 if (RetVT == MVT::i64)
330 return FPTOUINT_F64_I64;
331 if (RetVT == MVT::i128)
332 return FPTOUINT_F64_I128;
333 } else if (OpVT == MVT::f80) {
334 if (RetVT == MVT::i32)
335 return FPTOUINT_F80_I32;
336 if (RetVT == MVT::i64)
337 return FPTOUINT_F80_I64;
338 if (RetVT == MVT::i128)
339 return FPTOUINT_F80_I128;
340 } else if (OpVT == MVT::f128) {
341 if (RetVT == MVT::i32)
342 return FPTOUINT_F128_I32;
343 if (RetVT == MVT::i64)
344 return FPTOUINT_F128_I64;
345 if (RetVT == MVT::i128)
346 return FPTOUINT_F128_I128;
347 } else if (OpVT == MVT::ppcf128) {
348 if (RetVT == MVT::i32)
349 return FPTOUINT_PPCF128_I32;
350 if (RetVT == MVT::i64)
351 return FPTOUINT_PPCF128_I64;
352 if (RetVT == MVT::i128)
353 return FPTOUINT_PPCF128_I128;
354 }
355 return UNKNOWN_LIBCALL;
356 }
357
358 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
359 /// UNKNOWN_LIBCALL if there is none.
360 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
361 if (OpVT == MVT::i32) {
362 if (RetVT == MVT::f32)
363 return SINTTOFP_I32_F32;
364 if (RetVT == MVT::f64)
365 return SINTTOFP_I32_F64;
366 if (RetVT == MVT::f80)
367 return SINTTOFP_I32_F80;
368 if (RetVT == MVT::f128)
369 return SINTTOFP_I32_F128;
370 if (RetVT == MVT::ppcf128)
371 return SINTTOFP_I32_PPCF128;
372 } else if (OpVT == MVT::i64) {
373 if (RetVT == MVT::f32)
374 return SINTTOFP_I64_F32;
375 if (RetVT == MVT::f64)
376 return SINTTOFP_I64_F64;
377 if (RetVT == MVT::f80)
378 return SINTTOFP_I64_F80;
379 if (RetVT == MVT::f128)
380 return SINTTOFP_I64_F128;
381 if (RetVT == MVT::ppcf128)
382 return SINTTOFP_I64_PPCF128;
383 } else if (OpVT == MVT::i128) {
384 if (RetVT == MVT::f32)
385 return SINTTOFP_I128_F32;
386 if (RetVT == MVT::f64)
387 return SINTTOFP_I128_F64;
388 if (RetVT == MVT::f80)
389 return SINTTOFP_I128_F80;
390 if (RetVT == MVT::f128)
391 return SINTTOFP_I128_F128;
392 if (RetVT == MVT::ppcf128)
393 return SINTTOFP_I128_PPCF128;
394 }
395 return UNKNOWN_LIBCALL;
396 }
397
398 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
399 /// UNKNOWN_LIBCALL if there is none.
400 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
401 if (OpVT == MVT::i32) {
402 if (RetVT == MVT::f32)
403 return UINTTOFP_I32_F32;
404 if (RetVT == MVT::f64)
405 return UINTTOFP_I32_F64;
406 if (RetVT == MVT::f80)
407 return UINTTOFP_I32_F80;
408 if (RetVT == MVT::f128)
409 return UINTTOFP_I32_F128;
410 if (RetVT == MVT::ppcf128)
411 return UINTTOFP_I32_PPCF128;
412 } else if (OpVT == MVT::i64) {
413 if (RetVT == MVT::f32)
414 return UINTTOFP_I64_F32;
415 if (RetVT == MVT::f64)
416 return UINTTOFP_I64_F64;
417 if (RetVT == MVT::f80)
418 return UINTTOFP_I64_F80;
419 if (RetVT == MVT::f128)
420 return UINTTOFP_I64_F128;
421 if (RetVT == MVT::ppcf128)
422 return UINTTOFP_I64_PPCF128;
423 } else if (OpVT == MVT::i128) {
424 if (RetVT == MVT::f32)
425 return UINTTOFP_I128_F32;
426 if (RetVT == MVT::f64)
427 return UINTTOFP_I128_F64;
428 if (RetVT == MVT::f80)
429 return UINTTOFP_I128_F80;
430 if (RetVT == MVT::f128)
431 return UINTTOFP_I128_F128;
432 if (RetVT == MVT::ppcf128)
433 return UINTTOFP_I128_PPCF128;
434 }
435 return UNKNOWN_LIBCALL;
436 }
437
438 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
439 #define OP_TO_LIBCALL(Name, Enum) \
440 case Name: \
441 switch (VT.SimpleTy) { \
442 default: \
443 return UNKNOWN_LIBCALL; \
444 case MVT::i8: \
445 return Enum##_1; \
446 case MVT::i16: \
447 return Enum##_2; \
448 case MVT::i32: \
449 return Enum##_4; \
450 case MVT::i64: \
451 return Enum##_8; \
452 case MVT::i128: \
453 return Enum##_16; \
454 }
455
456 switch (Opc) {
457 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
458 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
459 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
460 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
461 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
462 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
463 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
464 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
465 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
466 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
467 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
468 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
469 }
470
471 #undef OP_TO_LIBCALL
472
473 return UNKNOWN_LIBCALL;
474 }
475
476 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
477 switch (ElementSize) {
478 case 1:
479 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
480 case 2:
481 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
482 case 4:
483 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
484 case 8:
485 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
486 case 16:
487 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
488 default:
489 return UNKNOWN_LIBCALL;
490 }
491 }
492
493 RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
494 switch (ElementSize) {
495 case 1:
496 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
497 case 2:
498 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
499 case 4:
500 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
501 case 8:
502 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
503 case 16:
504 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
505 default:
506 return UNKNOWN_LIBCALL;
507 }
508 }
509
510 RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
511 switch (ElementSize) {
512 case 1:
513 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
514 case 2:
515 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
516 case 4:
517 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
518 case 8:
519 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
520 case 16:
521 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
522 default:
523 return UNKNOWN_LIBCALL;
524 }
525 }
526
527 /// InitCmpLibcallCCs - Set default comparison libcall CC.
528 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
529 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
530 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
531 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
532 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
533 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
534 CCs[RTLIB::UNE_F32] = ISD::SETNE;
535 CCs[RTLIB::UNE_F64] = ISD::SETNE;
536 CCs[RTLIB::UNE_F128] = ISD::SETNE;
537 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
538 CCs[RTLIB::OGE_F32] = ISD::SETGE;
539 CCs[RTLIB::OGE_F64] = ISD::SETGE;
540 CCs[RTLIB::OGE_F128] = ISD::SETGE;
541 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
542 CCs[RTLIB::OLT_F32] = ISD::SETLT;
543 CCs[RTLIB::OLT_F64] = ISD::SETLT;
544 CCs[RTLIB::OLT_F128] = ISD::SETLT;
545 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
546 CCs[RTLIB::OLE_F32] = ISD::SETLE;
547 CCs[RTLIB::OLE_F64] = ISD::SETLE;
548 CCs[RTLIB::OLE_F128] = ISD::SETLE;
549 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
550 CCs[RTLIB::OGT_F32] = ISD::SETGT;
551 CCs[RTLIB::OGT_F64] = ISD::SETGT;
552 CCs[RTLIB::OGT_F128] = ISD::SETGT;
553 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
554 CCs[RTLIB::UO_F32] = ISD::SETNE;
555 CCs[RTLIB::UO_F64] = ISD::SETNE;
556 CCs[RTLIB::UO_F128] = ISD::SETNE;
557 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
558 CCs[RTLIB::O_F32] = ISD::SETEQ;
559 CCs[RTLIB::O_F64] = ISD::SETEQ;
560 CCs[RTLIB::O_F128] = ISD::SETEQ;
561 CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
562 }
563
564 /// NOTE: The TargetMachine owns TLOF.
565 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
566 initActions();
567
568 // Perform these initializations only once.
569 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
570 MaxLoadsPerMemcmp = 8;
571 MaxGluedStoresPerMemcpy = 0;
572 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
573 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
574 UseUnderscoreSetJmp = false;
575 UseUnderscoreLongJmp = false;
576 HasMultipleConditionRegisters = false;
577 HasExtractBitsInsn = false;
578 JumpIsExpensive = JumpIsExpensiveOverride;
579 PredictableSelectIsExpensive = false;
580 EnableExtLdPromotion = false;
581 StackPointerRegisterToSaveRestore = 0;
582 BooleanContents = UndefinedBooleanContent;
583 BooleanFloatContents = UndefinedBooleanContent;
584 BooleanVectorContents = UndefinedBooleanContent;
585 SchedPreferenceInfo = Sched::ILP;
586 MinFunctionLogAlignment = 0;
587 PrefFunctionLogAlignment = 0;
588 PrefLoopLogAlignment = 0;
589 GatherAllAliasesMaxDepth = 18;
590 MinStackArgumentAlignment = 1;
591 // TODO: the default will be switched to 0 in the next commit, along
592 // with the Target-specific changes necessary.
593 MaxAtomicSizeInBitsSupported = 1024;
594
595 MinCmpXchgSizeInBits = 0;
596 SupportsUnalignedAtomics = false;
597
598 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
599
600 InitLibcalls(TM.getTargetTriple());
601 InitCmpLibcallCCs(CmpLibcallCCs);
602 }
603
604 void TargetLoweringBase::initActions() {
605 // All operations default to being supported.
606 memset(OpActions, 0, sizeof(OpActions));
607 memset(LoadExtActions, 0, sizeof(LoadExtActions));
608 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
609 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
610 memset(CondCodeActions, 0, sizeof(CondCodeActions));
611 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
612 std::fill(std::begin(TargetDAGCombineArray),
613 std::end(TargetDAGCombineArray), 0);
614
615 for (MVT VT : MVT::fp_valuetypes()) {
616 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
617 if (IntVT.isValid()) {
618 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote);
619 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT);
620 }
621 }
622
623 // Set default actions for various operations.
624 for (MVT VT : MVT::all_valuetypes()) {
625 // Default all indexed load / store to expand.
626 for (unsigned IM = (unsigned)ISD::PRE_INC;
627 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
628 setIndexedLoadAction(IM, VT, Expand);
629 setIndexedStoreAction(IM, VT, Expand);
630 }
631
632 // Most backends expect to see the node which just returns the value loaded.
633 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
634
635 // These operations default to expand.
636 setOperationAction(ISD::FGETSIGN, VT, Expand);
637 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
638 setOperationAction(ISD::FMINNUM, VT, Expand);
639 setOperationAction(ISD::FMAXNUM, VT, Expand);
640 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand);
641 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand);
642 setOperationAction(ISD::FMINIMUM, VT, Expand);
643 setOperationAction(ISD::FMAXIMUM, VT, Expand);
644 setOperationAction(ISD::FMAD, VT, Expand);
645 setOperationAction(ISD::SMIN, VT, Expand);
646 setOperationAction(ISD::SMAX, VT, Expand);
647 setOperationAction(ISD::UMIN, VT, Expand);
648 setOperationAction(ISD::UMAX, VT, Expand);
649 setOperationAction(ISD::ABS, VT, Expand);
650 setOperationAction(ISD::FSHL, VT, Expand);
651 setOperationAction(ISD::FSHR, VT, Expand);
652 setOperationAction(ISD::SADDSAT, VT, Expand);
653 setOperationAction(ISD::UADDSAT, VT, Expand);
654 setOperationAction(ISD::SSUBSAT, VT, Expand);
655 setOperationAction(ISD::USUBSAT, VT, Expand);
656 setOperationAction(ISD::SMULFIX, VT, Expand);
657 setOperationAction(ISD::SMULFIXSAT, VT, Expand);
658 setOperationAction(ISD::UMULFIX, VT, Expand);
659
660 // Overflow operations default to expand
661 setOperationAction(ISD::SADDO, VT, Expand);
662 setOperationAction(ISD::SSUBO, VT, Expand);
663 setOperationAction(ISD::UADDO, VT, Expand);
664 setOperationAction(ISD::USUBO, VT, Expand);
665 setOperationAction(ISD::SMULO, VT, Expand);
666 setOperationAction(ISD::UMULO, VT, Expand);
667
668 // ADDCARRY operations default to expand
669 setOperationAction(ISD::ADDCARRY, VT, Expand);
670 setOperationAction(ISD::SUBCARRY, VT, Expand);
671 setOperationAction(ISD::SETCCCARRY, VT, Expand);
672
673 // ADDC/ADDE/SUBC/SUBE default to expand.
674 setOperationAction(ISD::ADDC, VT, Expand);
675 setOperationAction(ISD::ADDE, VT, Expand);
676 setOperationAction(ISD::SUBC, VT, Expand);
677 setOperationAction(ISD::SUBE, VT, Expand);
678
679 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
680 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
681 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
682
683 setOperationAction(ISD::BITREVERSE, VT, Expand);
684
685 // These library functions default to expand.
686 setOperationAction(ISD::FROUND, VT, Expand);
687 setOperationAction(ISD::FPOWI, VT, Expand);
688
689 // These operations default to expand for vector types.
690 if (VT.isVector()) {
691 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
692 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
693 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
694 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
695 }
696
697 // Constrained floating-point operations default to expand.
698 setOperationAction(ISD::STRICT_FADD, VT, Expand);
699 setOperationAction(ISD::STRICT_FSUB, VT, Expand);
700 setOperationAction(ISD::STRICT_FMUL, VT, Expand);
701 setOperationAction(ISD::STRICT_FDIV, VT, Expand);
702 setOperationAction(ISD::STRICT_FREM, VT, Expand);
703 setOperationAction(ISD::STRICT_FMA, VT, Expand);
704 setOperationAction(ISD::STRICT_FSQRT, VT, Expand);
705 setOperationAction(ISD::STRICT_FPOW, VT, Expand);
706 setOperationAction(ISD::STRICT_FPOWI, VT, Expand);
707 setOperationAction(ISD::STRICT_FSIN, VT, Expand);
708 setOperationAction(ISD::STRICT_FCOS, VT, Expand);
709 setOperationAction(ISD::STRICT_FEXP, VT, Expand);
710 setOperationAction(ISD::STRICT_FEXP2, VT, Expand);
711 setOperationAction(ISD::STRICT_FLOG, VT, Expand);
712 setOperationAction(ISD::STRICT_FLOG10, VT, Expand);
713 setOperationAction(ISD::STRICT_FLOG2, VT, Expand);
714 setOperationAction(ISD::STRICT_FRINT, VT, Expand);
715 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Expand);
716 setOperationAction(ISD::STRICT_FCEIL, VT, Expand);
717 setOperationAction(ISD::STRICT_FFLOOR, VT, Expand);
718 setOperationAction(ISD::STRICT_FROUND, VT, Expand);
719 setOperationAction(ISD::STRICT_FTRUNC, VT, Expand);
720 setOperationAction(ISD::STRICT_FMAXNUM, VT, Expand);
721 setOperationAction(ISD::STRICT_FMINNUM, VT, Expand);
722 setOperationAction(ISD::STRICT_FP_ROUND, VT, Expand);
723 setOperationAction(ISD::STRICT_FP_EXTEND, VT, Expand);
724 setOperationAction(ISD::STRICT_FP_TO_SINT, VT, Expand);
725 setOperationAction(ISD::STRICT_FP_TO_UINT, VT, Expand);
726
727 // For most targets @llvm.get.dynamic.area.offset just returns 0.
728 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
729
730 // Vector reduction default to expand.
731 setOperationAction(ISD::VECREDUCE_FADD, VT, Expand);
732 setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand);
733 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand);
734 setOperationAction(ISD::VECREDUCE_MUL, VT, Expand);
735 setOperationAction(ISD::VECREDUCE_AND, VT, Expand);
736 setOperationAction(ISD::VECREDUCE_OR, VT, Expand);
737 setOperationAction(ISD::VECREDUCE_XOR, VT, Expand);
738 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand);
739 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand);
740 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand);
741 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand);
742 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand);
743 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand);
744 }
745
746 // Most targets ignore the @llvm.prefetch intrinsic.
747 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
748
749 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
750 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
751
752 // ConstantFP nodes default to expand. Targets can either change this to
753 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
754 // to optimize expansions for certain constants.
755 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
756 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
757 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
758 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
759 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
760
761 // These library functions default to expand.
762 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
763 setOperationAction(ISD::FCBRT, VT, Expand);
764 setOperationAction(ISD::FLOG , VT, Expand);
765 setOperationAction(ISD::FLOG2, VT, Expand);
766 setOperationAction(ISD::FLOG10, VT, Expand);
767 setOperationAction(ISD::FEXP , VT, Expand);
768 setOperationAction(ISD::FEXP2, VT, Expand);
769 setOperationAction(ISD::FFLOOR, VT, Expand);
770 setOperationAction(ISD::FNEARBYINT, VT, Expand);
771 setOperationAction(ISD::FCEIL, VT, Expand);
772 setOperationAction(ISD::FRINT, VT, Expand);
773 setOperationAction(ISD::FTRUNC, VT, Expand);
774 setOperationAction(ISD::FROUND, VT, Expand);
775 setOperationAction(ISD::LROUND, VT, Expand);
776 setOperationAction(ISD::LLROUND, VT, Expand);
777 setOperationAction(ISD::LRINT, VT, Expand);
778 setOperationAction(ISD::LLRINT, VT, Expand);
779 }
780
781 // Default ISD::TRAP to expand (which turns it into abort).
782 setOperationAction(ISD::TRAP, MVT::Other, Expand);
783
784 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
785 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
786 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
787 }
788
789 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
790 EVT) const {
791 return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
792 }
793
794 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
795 bool LegalTypes) const {
796 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
797 if (LHSTy.isVector())
798 return LHSTy;
799 return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
800 : getPointerTy(DL);
801 }
802
803 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
804 assert(isTypeLegal(VT));
805 switch (Op) {
806 default:
807 return false;
808 case ISD::SDIV:
809 case ISD::UDIV:
810 case ISD::SREM:
811 case ISD::UREM:
812 return true;
813 }
814 }
815
816 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
817 // If the command-line option was specified, ignore this request.
818 if (!JumpIsExpensiveOverride.getNumOccurrences())
819 JumpIsExpensive = isExpensive;
820 }
821
822 TargetLoweringBase::LegalizeKind
823 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
824 // If this is a simple type, use the ComputeRegisterProp mechanism.
825 if (VT.isSimple()) {
826 MVT SVT = VT.getSimpleVT();
827 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
828 MVT NVT = TransformToType[SVT.SimpleTy];
829 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
830
831 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
832 (NVT.isVector() ||
833 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
834 "Promote may not follow Expand or Promote");
835
836 if (LA == TypeSplitVector)
837 return LegalizeKind(LA,
838 EVT::getVectorVT(Context, SVT.getVectorElementType(),
839 SVT.getVectorNumElements() / 2));
840 if (LA == TypeScalarizeVector)
841 return LegalizeKind(LA, SVT.getVectorElementType());
842 return LegalizeKind(LA, NVT);
843 }
844
845 // Handle Extended Scalar Types.
846 if (!VT.isVector()) {
847 assert(VT.isInteger() && "Float types must be simple");
848 unsigned BitSize = VT.getSizeInBits();
849 // First promote to a power-of-two size, then expand if necessary.
850 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
851 EVT NVT = VT.getRoundIntegerType(Context);
852 assert(NVT != VT && "Unable to round integer VT");
853 LegalizeKind NextStep = getTypeConversion(Context, NVT);
854 // Avoid multi-step promotion.
855 if (NextStep.first == TypePromoteInteger)
856 return NextStep;
857 // Return rounded integer type.
858 return LegalizeKind(TypePromoteInteger, NVT);
859 }
860
861 return LegalizeKind(TypeExpandInteger,
862 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
863 }
864
865 // Handle vector types.
866 unsigned NumElts = VT.getVectorNumElements();
867 EVT EltVT = VT.getVectorElementType();
868
869 // Vectors with only one element are always scalarized.
870 if (NumElts == 1)
871 return LegalizeKind(TypeScalarizeVector, EltVT);
872
873 // Try to widen vector elements until the element type is a power of two and
874 // promote it to a legal type later on, for example:
875 // <3 x i8> -> <4 x i8> -> <4 x i32>
876 if (EltVT.isInteger()) {
877 // Vectors with a number of elements that is not a power of two are always
878 // widened, for example <3 x i8> -> <4 x i8>.
879 if (!VT.isPow2VectorType()) {
880 NumElts = (unsigned)NextPowerOf2(NumElts);
881 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
882 return LegalizeKind(TypeWidenVector, NVT);
883 }
884
885 // Examine the element type.
886 LegalizeKind LK = getTypeConversion(Context, EltVT);
887
888 // If type is to be expanded, split the vector.
889 // <4 x i140> -> <2 x i140>
890 if (LK.first == TypeExpandInteger)
891 return LegalizeKind(TypeSplitVector,
892 EVT::getVectorVT(Context, EltVT, NumElts / 2));
893
894 // Promote the integer element types until a legal vector type is found
895 // or until the element integer type is too big. If a legal type was not
896 // found, fallback to the usual mechanism of widening/splitting the
897 // vector.
898 EVT OldEltVT = EltVT;
899 while (true) {
900 // Increase the bitwidth of the element to the next pow-of-two
901 // (which is greater than 8 bits).
902 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
903 .getRoundIntegerType(Context);
904
905 // Stop trying when getting a non-simple element type.
906 // Note that vector elements may be greater than legal vector element
907 // types. Example: X86 XMM registers hold 64bit element on 32bit
908 // systems.
909 if (!EltVT.isSimple())
910 break;
911
912 // Build a new vector type and check if it is legal.
913 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
914 // Found a legal promoted vector type.
915 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
916 return LegalizeKind(TypePromoteInteger,
917 EVT::getVectorVT(Context, EltVT, NumElts));
918 }
919
920 // Reset the type to the unexpanded type if we did not find a legal vector
921 // type with a promoted vector element type.
922 EltVT = OldEltVT;
923 }
924
925 // Try to widen the vector until a legal type is found.
926 // If there is no wider legal type, split the vector.
927 while (true) {
928 // Round up to the next power of 2.
929 NumElts = (unsigned)NextPowerOf2(NumElts);
930
931 // If there is no simple vector type with this many elements then there
932 // cannot be a larger legal vector type. Note that this assumes that
933 // there are no skipped intermediate vector types in the simple types.
934 if (!EltVT.isSimple())
935 break;
936 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
937 if (LargerVector == MVT())
938 break;
939
940 // If this type is legal then widen the vector.
941 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
942 return LegalizeKind(TypeWidenVector, LargerVector);
943 }
944
945 // Widen odd vectors to next power of two.
946 if (!VT.isPow2VectorType()) {
947 EVT NVT = VT.getPow2VectorType(Context);
948 return LegalizeKind(TypeWidenVector, NVT);
949 }
950
951 // Vectors with illegal element types are expanded.
952 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
953 return LegalizeKind(TypeSplitVector, NVT);
954 }
955
956 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
957 unsigned &NumIntermediates,
958 MVT &RegisterVT,
959 TargetLoweringBase *TLI) {
960 // Figure out the right, legal destination reg to copy into.
961 unsigned NumElts = VT.getVectorNumElements();
962 MVT EltTy = VT.getVectorElementType();
963
964 unsigned NumVectorRegs = 1;
965
966 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
967 // could break down into LHS/RHS like LegalizeDAG does.
968 if (!isPowerOf2_32(NumElts)) {
969 NumVectorRegs = NumElts;
970 NumElts = 1;
971 }
972
973 // Divide the input until we get to a supported size. This will always
974 // end with a scalar if the target doesn't support vectors.
975 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
976 NumElts >>= 1;
977 NumVectorRegs <<= 1;
978 }
979
980 NumIntermediates = NumVectorRegs;
981
982 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
983 if (!TLI->isTypeLegal(NewVT))
984 NewVT = EltTy;
985 IntermediateVT = NewVT;
986
987 unsigned NewVTSize = NewVT.getSizeInBits();
988
989 // Convert sizes such as i33 to i64.
990 if (!isPowerOf2_32(NewVTSize))
991 NewVTSize = NextPowerOf2(NewVTSize);
992
993 MVT DestVT = TLI->getRegisterType(NewVT);
994 RegisterVT = DestVT;
995 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
996 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
997
998 // Otherwise, promotion or legal types use the same number of registers as
999 // the vector decimated to the appropriate level.
1000 return NumVectorRegs;
1001 }
1002
1003 /// isLegalRC - Return true if the value types that can be represented by the
1004 /// specified register class are all legal.
1005 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1006 const TargetRegisterClass &RC) const {
1007 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1008 if (isTypeLegal(*I))
1009 return true;
1010 return false;
1011 }
1012
1013 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1014 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1015 MachineBasicBlock *
1016 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
1017 MachineBasicBlock *MBB) const {
1018 MachineInstr *MI = &InitialMI;
1019 MachineFunction &MF = *MI->getMF();
1020 MachineFrameInfo &MFI = MF.getFrameInfo();
1021
1022 // We're handling multiple types of operands here:
1023 // PATCHPOINT MetaArgs - live-in, read only, direct
1024 // STATEPOINT Deopt Spill - live-through, read only, indirect
1025 // STATEPOINT Deopt Alloca - live-through, read only, direct
1026 // (We're currently conservative and mark the deopt slots read/write in
1027 // practice.)
1028 // STATEPOINT GC Spill - live-through, read/write, indirect
1029 // STATEPOINT GC Alloca - live-through, read/write, direct
1030 // The live-in vs live-through is handled already (the live through ones are
1031 // all stack slots), but we need to handle the different type of stackmap
1032 // operands and memory effects here.
1033
1034 // MI changes inside this loop as we grow operands.
1035 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1036 MachineOperand &MO = MI->getOperand(OperIdx);
1037 if (!MO.isFI())
1038 continue;
1039
1040 // foldMemoryOperand builds a new MI after replacing a single FI operand
1041 // with the canonical set of five x86 addressing-mode operands.
1042 int FI = MO.getIndex();
1043 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1044
1045 // Copy operands before the frame-index.
1046 for (unsigned i = 0; i < OperIdx; ++i)
1047 MIB.add(MI->getOperand(i));
1048 // Add frame index operands recognized by stackmaps.cpp
1049 if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1050 // indirect-mem-ref tag, size, #FI, offset.
1051 // Used for spills inserted by StatepointLowering. This codepath is not
1052 // used for patchpoints/stackmaps at all, for these spilling is done via
1053 // foldMemoryOperand callback only.
1054 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1055 MIB.addImm(StackMaps::IndirectMemRefOp);
1056 MIB.addImm(MFI.getObjectSize(FI));
1057 MIB.add(MI->getOperand(OperIdx));
1058 MIB.addImm(0);
1059 } else {
1060 // direct-mem-ref tag, #FI, offset.
1061 // Used by patchpoint, and direct alloca arguments to statepoints
1062 MIB.addImm(StackMaps::DirectMemRefOp);
1063 MIB.add(MI->getOperand(OperIdx));
1064 MIB.addImm(0);
1065 }
1066 // Copy the operands after the frame index.
1067 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1068 MIB.add(MI->getOperand(i));
1069
1070 // Inherit previous memory operands.
1071 MIB.cloneMemRefs(*MI);
1072 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1073
1074 // Add a new memory operand for this FI.
1075 assert(MFI.getObjectOffset(FI) != -1);
1076
1077 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1078 // PATCHPOINT should be updated to do the same. (TODO)
1079 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1080 auto Flags = MachineMemOperand::MOLoad;
1081 MachineMemOperand *MMO = MF.getMachineMemOperand(
1082 MachinePointerInfo::getFixedStack(MF, FI), Flags,
1083 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
1084 MIB->addMemOperand(MF, MMO);
1085 }
1086
1087 // Replace the instruction and update the operand index.
1088 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1089 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1090 MI->eraseFromParent();
1091 MI = MIB;
1092 }
1093 return MBB;
1094 }
1095
1096 MachineBasicBlock *
1097 TargetLoweringBase::emitXRayCustomEvent(MachineInstr &MI,
1098 MachineBasicBlock *MBB) const {
1099 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1100 "Called emitXRayCustomEvent on the wrong MI!");
1101 auto &MF = *MI.getMF();
1102 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1103 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1104 MIB.add(MI.getOperand(OpIdx));
1105
1106 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1107 MI.eraseFromParent();
1108 return MBB;
1109 }
1110
1111 MachineBasicBlock *
1112 TargetLoweringBase::emitXRayTypedEvent(MachineInstr &MI,
1113 MachineBasicBlock *MBB) const {
1114 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1115 "Called emitXRayTypedEvent on the wrong MI!");
1116 auto &MF = *MI.getMF();
1117 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1118 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1119 MIB.add(MI.getOperand(OpIdx));
1120
1121 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1122 MI.eraseFromParent();
1123 return MBB;
1124 }
1125
1126 /// findRepresentativeClass - Return the largest legal super-reg register class
1127 /// of the register class for the specified type and its associated "cost".
1128 // This function is in TargetLowering because it uses RegClassForVT which would
1129 // need to be moved to TargetRegisterInfo and would necessitate moving
1130 // isTypeLegal over as well - a massive change that would just require
1131 // TargetLowering having a TargetRegisterInfo class member that it would use.
1132 std::pair<const TargetRegisterClass *, uint8_t>
1133 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1134 MVT VT) const {
1135 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1136 if (!RC)
1137 return std::make_pair(RC, 0);
1138
1139 // Compute the set of all super-register classes.
1140 BitVector SuperRegRC(TRI->getNumRegClasses());
1141 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1142 SuperRegRC.setBitsInMask(RCI.getMask());
1143
1144 // Find the first legal register class with the largest spill size.
1145 const TargetRegisterClass *BestRC = RC;
1146 for (unsigned i : SuperRegRC.set_bits()) {
1147 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1148 // We want the largest possible spill size.
1149 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1150 continue;
1151 if (!isLegalRC(*TRI, *SuperRC))
1152 continue;
1153 BestRC = SuperRC;
1154 }
1155 return std::make_pair(BestRC, 1);
1156 }
1157
1158 /// computeRegisterProperties - Once all of the register classes are added,
1159 /// this allows us to compute derived properties we expose.
1160 void TargetLoweringBase::computeRegisterProperties(
1161 const TargetRegisterInfo *TRI) {
1162 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1163 "Too many value types for ValueTypeActions to hold!");
1164
1165 // Everything defaults to needing one register.
1166 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1167 NumRegistersForVT[i] = 1;
1168 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1169 }
1170 // ...except isVoid, which doesn't need any registers.
1171 NumRegistersForVT[MVT::isVoid] = 0;
1172
1173 // Find the largest integer register class.
1174 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1175 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1176 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1177
1178 // Every integer value type larger than this largest register takes twice as
1179 // many registers to represent as the previous ValueType.
1180 for (unsigned ExpandedReg = LargestIntReg + 1;
1181 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1182 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1183 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1184 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1185 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1186 TypeExpandInteger);
1187 }
1188
1189 // Inspect all of the ValueType's smaller than the largest integer
1190 // register to see which ones need promotion.
1191 unsigned LegalIntReg = LargestIntReg;
1192 for (unsigned IntReg = LargestIntReg - 1;
1193 IntReg >= (unsigned)MVT::i1; --IntReg) {
1194 MVT IVT = (MVT::SimpleValueType)IntReg;
1195 if (isTypeLegal(IVT)) {
1196 LegalIntReg = IntReg;
1197 } else {
1198 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1199 (MVT::SimpleValueType)LegalIntReg;
1200 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1201 }
1202 }
1203
1204 // ppcf128 type is really two f64's.
1205 if (!isTypeLegal(MVT::ppcf128)) {
1206 if (isTypeLegal(MVT::f64)) {
1207 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1208 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1209 TransformToType[MVT::ppcf128] = MVT::f64;
1210 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1211 } else {
1212 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1213 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1214 TransformToType[MVT::ppcf128] = MVT::i128;
1215 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1216 }
1217 }
1218
1219 // Decide how to handle f128. If the target does not have native f128 support,
1220 // expand it to i128 and we will be generating soft float library calls.
1221 if (!isTypeLegal(MVT::f128)) {
1222 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1223 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1224 TransformToType[MVT::f128] = MVT::i128;
1225 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1226 }
1227
1228 // Decide how to handle f64. If the target does not have native f64 support,
1229 // expand it to i64 and we will be generating soft float library calls.
1230 if (!isTypeLegal(MVT::f64)) {
1231 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1232 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1233 TransformToType[MVT::f64] = MVT::i64;
1234 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1235 }
1236
1237 // Decide how to handle f32. If the target does not have native f32 support,
1238 // expand it to i32 and we will be generating soft float library calls.
1239 if (!isTypeLegal(MVT::f32)) {
1240 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1241 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1242 TransformToType[MVT::f32] = MVT::i32;
1243 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1244 }
1245
1246 // Decide how to handle f16. If the target does not have native f16 support,
1247 // promote it to f32, because there are no f16 library calls (except for
1248 // conversions).
1249 if (!isTypeLegal(MVT::f16)) {
1250 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1251 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1252 TransformToType[MVT::f16] = MVT::f32;
1253 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1254 }
1255
1256 // Loop over all of the vector value types to see which need transformations.
1257 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1258 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1259 MVT VT = (MVT::SimpleValueType) i;
1260 if (isTypeLegal(VT))
1261 continue;
1262
1263 MVT EltVT = VT.getVectorElementType();
1264 unsigned NElts = VT.getVectorNumElements();
1265 bool IsLegalWiderType = false;
1266 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1267 switch (PreferredAction) {
1268 case TypePromoteInteger:
1269 // Try to promote the elements of integer vectors. If no legal
1270 // promotion was found, fall through to the widen-vector method.
1271 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
1272 MVT SVT = (MVT::SimpleValueType) nVT;
1273 // Promote vectors of integers to vectors with the same number
1274 // of elements, with a wider element type.
1275 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1276 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
1277 TransformToType[i] = SVT;
1278 RegisterTypeForVT[i] = SVT;
1279 NumRegistersForVT[i] = 1;
1280 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1281 IsLegalWiderType = true;
1282 break;
1283 }
1284 }
1285 if (IsLegalWiderType)
1286 break;
1287 LLVM_FALLTHROUGH;
1288
1289 case TypeWidenVector:
1290 if (isPowerOf2_32(NElts)) {
1291 // Try to widen the vector.
1292 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1293 MVT SVT = (MVT::SimpleValueType) nVT;
1294 if (SVT.getVectorElementType() == EltVT
1295 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1296 TransformToType[i] = SVT;
1297 RegisterTypeForVT[i] = SVT;
1298 NumRegistersForVT[i] = 1;
1299 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1300 IsLegalWiderType = true;
1301 break;
1302 }
1303 }
1304 if (IsLegalWiderType)
1305 break;
1306 } else {
1307 // Only widen to the next power of 2 to keep consistency with EVT.
1308 MVT NVT = VT.getPow2VectorType();
1309 if (isTypeLegal(NVT)) {
1310 TransformToType[i] = NVT;
1311 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1312 RegisterTypeForVT[i] = NVT;
1313 NumRegistersForVT[i] = 1;
1314 break;
1315 }
1316 }
1317 LLVM_FALLTHROUGH;
1318
1319 case TypeSplitVector:
1320 case TypeScalarizeVector: {
1321 MVT IntermediateVT;
1322 MVT RegisterVT;
1323 unsigned NumIntermediates;
1324 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1325 NumIntermediates, RegisterVT, this);
1326 RegisterTypeForVT[i] = RegisterVT;
1327
1328 MVT NVT = VT.getPow2VectorType();
1329 if (NVT == VT) {
1330 // Type is already a power of 2. The default action is to split.
1331 TransformToType[i] = MVT::Other;
1332 if (PreferredAction == TypeScalarizeVector)
1333 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1334 else if (PreferredAction == TypeSplitVector)
1335 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1336 else
1337 // Set type action according to the number of elements.
1338 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1339 : TypeSplitVector);
1340 } else {
1341 TransformToType[i] = NVT;
1342 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1343 }
1344 break;
1345 }
1346 default:
1347 llvm_unreachable("Unknown vector legalization action!");
1348 }
1349 }
1350
1351 // Determine the 'representative' register class for each value type.
1352 // An representative register class is the largest (meaning one which is
1353 // not a sub-register class / subreg register class) legal register class for
1354 // a group of value types. For example, on i386, i8, i16, and i32
1355 // representative would be GR32; while on x86_64 it's GR64.
1356 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1357 const TargetRegisterClass* RRC;
1358 uint8_t Cost;
1359 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1360 RepRegClassForVT[i] = RRC;
1361 RepRegClassCostForVT[i] = Cost;
1362 }
1363 }
1364
1365 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1366 EVT VT) const {
1367 assert(!VT.isVector() && "No default SetCC type for vectors!");
1368 return getPointerTy(DL).SimpleTy;
1369 }
1370
1371 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1372 return MVT::i32; // return the default value
1373 }
1374
1375 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1376 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1377 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1378 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1379 ///
1380 /// This method returns the number of registers needed, and the VT for each
1381 /// register. It also returns the VT and quantity of the intermediate values
1382 /// before they are promoted/expanded.
1383 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1384 EVT &IntermediateVT,
1385 unsigned &NumIntermediates,
1386 MVT &RegisterVT) const {
1387 unsigned NumElts = VT.getVectorNumElements();
1388
1389 // If there is a wider vector type with the same element type as this one,
1390 // or a promoted vector type that has the same number of elements which
1391 // are wider, then we should convert to that legal vector type.
1392 // This handles things like <2 x float> -> <4 x float> and
1393 // <4 x i1> -> <4 x i32>.
1394 LegalizeTypeAction TA = getTypeAction(Context, VT);
1395 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1396 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1397 if (isTypeLegal(RegisterEVT)) {
1398 IntermediateVT = RegisterEVT;
1399 RegisterVT = RegisterEVT.getSimpleVT();
1400 NumIntermediates = 1;
1401 return 1;
1402 }
1403 }
1404
1405 // Figure out the right, legal destination reg to copy into.
1406 EVT EltTy = VT.getVectorElementType();
1407
1408 unsigned NumVectorRegs = 1;
1409
1410 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1411 // could break down into LHS/RHS like LegalizeDAG does.
1412 if (!isPowerOf2_32(NumElts)) {
1413 NumVectorRegs = NumElts;
1414 NumElts = 1;
1415 }
1416
1417 // Divide the input until we get to a supported size. This will always
1418 // end with a scalar if the target doesn't support vectors.
1419 while (NumElts > 1 && !isTypeLegal(
1420 EVT::getVectorVT(Context, EltTy, NumElts))) {
1421 NumElts >>= 1;
1422 NumVectorRegs <<= 1;
1423 }
1424
1425 NumIntermediates = NumVectorRegs;
1426
1427 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1428 if (!isTypeLegal(NewVT))
1429 NewVT = EltTy;
1430 IntermediateVT = NewVT;
1431
1432 MVT DestVT = getRegisterType(Context, NewVT);
1433 RegisterVT = DestVT;
1434 unsigned NewVTSize = NewVT.getSizeInBits();
1435
1436 // Convert sizes such as i33 to i64.
1437 if (!isPowerOf2_32(NewVTSize))
1438 NewVTSize = NextPowerOf2(NewVTSize);
1439
1440 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1441 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1442
1443 // Otherwise, promotion or legal types use the same number of registers as
1444 // the vector decimated to the appropriate level.
1445 return NumVectorRegs;
1446 }
1447
1448 /// Get the EVTs and ArgFlags collections that represent the legalized return
1449 /// type of the given function. This does not require a DAG or a return value,
1450 /// and is suitable for use before any DAGs for the function are constructed.
1451 /// TODO: Move this out of TargetLowering.cpp.
1452 void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
1453 AttributeList attr,
1454 SmallVectorImpl<ISD::OutputArg> &Outs,
1455 const TargetLowering &TLI, const DataLayout &DL) {
1456 SmallVector<EVT, 4> ValueVTs;
1457 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1458 unsigned NumValues = ValueVTs.size();
1459 if (NumValues == 0) return;
1460
1461 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1462 EVT VT = ValueVTs[j];
1463 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1464
1465 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1466 ExtendKind = ISD::SIGN_EXTEND;
1467 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1468 ExtendKind = ISD::ZERO_EXTEND;
1469
1470 // FIXME: C calling convention requires the return type to be promoted to
1471 // at least 32-bit. But this is not necessary for non-C calling
1472 // conventions. The frontend should mark functions whose return values
1473 // require promoting with signext or zeroext attributes.
1474 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1475 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1476 if (VT.bitsLT(MinVT))
1477 VT = MinVT;
1478 }
1479
1480 unsigned NumParts =
1481 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1482 MVT PartVT =
1483 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1484
1485 // 'inreg' on function refers to return value
1486 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1487 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1488 Flags.setInReg();
1489
1490 // Propagate extension type if any
1491 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1492 Flags.setSExt();
1493 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1494 Flags.setZExt();
1495
1496 for (unsigned i = 0; i < NumParts; ++i)
1497 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1498 }
1499 }
1500
1501 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1502 /// function arguments in the caller parameter area. This is the actual
1503 /// alignment, not its logarithm.
1504 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1505 const DataLayout &DL) const {
1506 return DL.getABITypeAlignment(Ty);
1507 }
1508
1509 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1510 const DataLayout &DL, EVT VT,
1511 unsigned AddrSpace,
1512 unsigned Alignment,
1513 MachineMemOperand::Flags Flags,
1514 bool *Fast) const {
1515 // Check if the specified alignment is sufficient based on the data layout.
1516 // TODO: While using the data layout works in practice, a better solution
1517 // would be to implement this check directly (make this a virtual function).
1518 // For example, the ABI alignment may change based on software platform while
1519 // this function should only be affected by hardware implementation.
1520 Type *Ty = VT.getTypeForEVT(Context);
1521 if (Alignment >= DL.getABITypeAlignment(Ty)) {
1522 // Assume that an access that meets the ABI-specified alignment is fast.
1523 if (Fast != nullptr)
1524 *Fast = true;
1525 return true;
1526 }
1527
1528 // This is a misaligned access.
1529 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1530 }
1531
1532 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1533 const DataLayout &DL, EVT VT,
1534 const MachineMemOperand &MMO,
1535 bool *Fast) const {
1536 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(),
1537 MMO.getAlignment(), MMO.getFlags(), Fast);
1538 }
1539
1540 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const {
1541 return BranchProbability(MinPercentageForPredictableBranch, 100);
1542 }
1543
1544 //===----------------------------------------------------------------------===//
1545 // TargetTransformInfo Helpers
1546 //===----------------------------------------------------------------------===//
1547
1548 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1549 enum InstructionOpcodes {
1550 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1551 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1552 #include "llvm/IR/Instruction.def"
1553 };
1554 switch (static_cast<InstructionOpcodes>(Opcode)) {
1555 case Ret: return 0;
1556 case Br: return 0;
1557 case Switch: return 0;
1558 case IndirectBr: return 0;
1559 case Invoke: return 0;
1560 case CallBr: return 0;
1561 case Resume: return 0;
1562 case Unreachable: return 0;
1563 case CleanupRet: return 0;
1564 case CatchRet: return 0;
1565 case CatchPad: return 0;
1566 case CatchSwitch: return 0;
1567 case CleanupPad: return 0;
1568 case FNeg: return ISD::FNEG;
1569 case Add: return ISD::ADD;
1570 case FAdd: return ISD::FADD;
1571 case Sub: return ISD::SUB;
1572 case FSub: return ISD::FSUB;
1573 case Mul: return ISD::MUL;
1574 case FMul: return ISD::FMUL;
1575 case UDiv: return ISD::UDIV;
1576 case SDiv: return ISD::SDIV;
1577 case FDiv: return ISD::FDIV;
1578 case URem: return ISD::UREM;
1579 case SRem: return ISD::SREM;
1580 case FRem: return ISD::FREM;
1581 case Shl: return ISD::SHL;
1582 case LShr: return ISD::SRL;
1583 case AShr: return ISD::SRA;
1584 case And: return ISD::AND;
1585 case Or: return ISD::OR;
1586 case Xor: return ISD::XOR;
1587 case Alloca: return 0;
1588 case Load: return ISD::LOAD;
1589 case Store: return ISD::STORE;
1590 case GetElementPtr: return 0;
1591 case Fence: return 0;
1592 case AtomicCmpXchg: return 0;
1593 case AtomicRMW: return 0;
1594 case Trunc: return ISD::TRUNCATE;
1595 case ZExt: return ISD::ZERO_EXTEND;
1596 case SExt: return ISD::SIGN_EXTEND;
1597 case FPToUI: return ISD::FP_TO_UINT;
1598 case FPToSI: return ISD::FP_TO_SINT;
1599 case UIToFP: return ISD::UINT_TO_FP;
1600 case SIToFP: return ISD::SINT_TO_FP;
1601 case FPTrunc: return ISD::FP_ROUND;
1602 case FPExt: return ISD::FP_EXTEND;
1603 case PtrToInt: return ISD::BITCAST;
1604 case IntToPtr: return ISD::BITCAST;
1605 case BitCast: return ISD::BITCAST;
1606 case AddrSpaceCast: return ISD::ADDRSPACECAST;
1607 case ICmp: return ISD::SETCC;
1608 case FCmp: return ISD::SETCC;
1609 case PHI: return 0;
1610 case Call: return 0;
1611 case Select: return ISD::SELECT;
1612 case UserOp1: return 0;
1613 case UserOp2: return 0;
1614 case VAArg: return 0;
1615 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1616 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1617 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1618 case ExtractValue: return ISD::MERGE_VALUES;
1619 case InsertValue: return ISD::MERGE_VALUES;
1620 case LandingPad: return 0;
1621 }
1622
1623 llvm_unreachable("Unknown instruction type encountered!");
1624 }
1625
1626 std::pair<int, MVT>
1627 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1628 Type *Ty) const {
1629 LLVMContext &C = Ty->getContext();
1630 EVT MTy = getValueType(DL, Ty);
1631
1632 int Cost = 1;
1633 // We keep legalizing the type until we find a legal kind. We assume that
1634 // the only operation that costs anything is the split. After splitting
1635 // we need to handle two types.
1636 while (true) {
1637 LegalizeKind LK = getTypeConversion(C, MTy);
1638
1639 if (LK.first == TypeLegal)
1640 return std::make_pair(Cost, MTy.getSimpleVT());
1641
1642 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1643 Cost *= 2;
1644
1645 // Do not loop with f128 type.
1646 if (MTy == LK.second)
1647 return std::make_pair(Cost, MTy.getSimpleVT());
1648
1649 // Keep legalizing the type.
1650 MTy = LK.second;
1651 }
1652 }
1653
1654 Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1655 bool UseTLS) const {
1656 // compiler-rt provides a variable with a magic name. Targets that do not
1657 // link with compiler-rt may also provide such a variable.
1658 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1659 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1660 auto UnsafeStackPtr =
1661 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1662
1663 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1664
1665 if (!UnsafeStackPtr) {
1666 auto TLSModel = UseTLS ?
1667 GlobalValue::InitialExecTLSModel :
1668 GlobalValue::NotThreadLocal;
1669 // The global variable is not defined yet, define it ourselves.
1670 // We use the initial-exec TLS model because we do not support the
1671 // variable living anywhere other than in the main executable.
1672 UnsafeStackPtr = new GlobalVariable(
1673 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1674 UnsafeStackPtrVar, nullptr, TLSModel);
1675 } else {
1676 // The variable exists, check its type and attributes.
1677 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1678 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1679 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1680 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1681 (UseTLS ? "" : "not ") + "be thread-local");
1682 }
1683 return UnsafeStackPtr;
1684 }
1685
1686 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1687 if (!TM.getTargetTriple().isAndroid())
1688 return getDefaultSafeStackPointerLocation(IRB, true);
1689
1690 // Android provides a libc function to retrieve the address of the current
1691 // thread's unsafe stack pointer.
1692 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1693 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1694 FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1695 StackPtrTy->getPointerTo(0));
1696 return IRB.CreateCall(Fn);
1697 }
1698
1699 //===----------------------------------------------------------------------===//
1700 // Loop Strength Reduction hooks
1701 //===----------------------------------------------------------------------===//
1702
1703 /// isLegalAddressingMode - Return true if the addressing mode represented
1704 /// by AM is legal for this target, for a load/store of the specified type.
1705 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1706 const AddrMode &AM, Type *Ty,
1707 unsigned AS, Instruction *I) const {
1708 // The default implementation of this implements a conservative RISCy, r+r and
1709 // r+i addr mode.
1710
1711 // Allows a sign-extended 16-bit immediate field.
1712 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1713 return false;
1714
1715 // No global is ever allowed as a base.
1716 if (AM.BaseGV)
1717 return false;
1718
1719 // Only support r+r,
1720 switch (AM.Scale) {
1721 case 0: // "r+i" or just "i", depending on HasBaseReg.
1722 break;
1723 case 1:
1724 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1725 return false;
1726 // Otherwise we have r+r or r+i.
1727 break;
1728 case 2:
1729 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1730 return false;
1731 // Allow 2*r as r+r.
1732 break;
1733 default: // Don't allow n * r
1734 return false;
1735 }
1736
1737 return true;
1738 }
1739
1740 //===----------------------------------------------------------------------===//
1741 // Stack Protector
1742 //===----------------------------------------------------------------------===//
1743
1744 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1745 // so that SelectionDAG handle SSP.
1746 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
1747 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1748 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1749 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1750 return M.getOrInsertGlobal("__guard_local", PtrTy);
1751 }
1752 return nullptr;
1753 }
1754
1755 // Currently only support "standard" __stack_chk_guard.
1756 // TODO: add LOAD_STACK_GUARD support.
1757 void TargetLoweringBase::insertSSPDeclarations(Module &M) const {
1758 if (!M.getNamedValue("__stack_chk_guard"))
1759 new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1760 GlobalVariable::ExternalLinkage,
1761 nullptr, "__stack_chk_guard");
1762 }
1763
1764 // Currently only support "standard" __stack_chk_guard.
1765 // TODO: add LOAD_STACK_GUARD support.
1766 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const {
1767 return M.getNamedValue("__stack_chk_guard");
1768 }
1769
1770 Function *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const {
1771 return nullptr;
1772 }
1773
1774 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
1775 return MinimumJumpTableEntries;
1776 }
1777
1778 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
1779 MinimumJumpTableEntries = Val;
1780 }
1781
1782 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1783 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1784 }
1785
1786 unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
1787 return MaximumJumpTableSize;
1788 }
1789
1790 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
1791 MaximumJumpTableSize = Val;
1792 }
1793
1794 //===----------------------------------------------------------------------===//
1795 // Reciprocal Estimates
1796 //===----------------------------------------------------------------------===//
1797
1798 /// Get the reciprocal estimate attribute string for a function that will
1799 /// override the target defaults.
1800 static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
1801 const Function &F = MF.getFunction();
1802 return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1803 }
1804
1805 /// Construct a string for the given reciprocal operation of the given type.
1806 /// This string should match the corresponding option to the front-end's
1807 /// "-mrecip" flag assuming those strings have been passed through in an
1808 /// attribute string. For example, "vec-divf" for a division of a vXf32.
1809 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1810 std::string Name = VT.isVector() ? "vec-" : "";
1811
1812 Name += IsSqrt ? "sqrt" : "div";
1813
1814 // TODO: Handle "half" or other float types?
1815 if (VT.getScalarType() == MVT::f64) {
1816 Name += "d";
1817 } else {
1818 assert(VT.getScalarType() == MVT::f32 &&
1819 "Unexpected FP type for reciprocal estimate");
1820 Name += "f";
1821 }
1822
1823 return Name;
1824 }
1825
1826 /// Return the character position and value (a single numeric character) of a
1827 /// customized refinement operation in the input string if it exists. Return
1828 /// false if there is no customized refinement step count.
1829 static bool parseRefinementStep(StringRef In, size_t &Position,
1830 uint8_t &Value) {
1831 const char RefStepToken = ':';
1832 Position = In.find(RefStepToken);
1833 if (Position == StringRef::npos)
1834 return false;
1835
1836 StringRef RefStepString = In.substr(Position + 1);
1837 // Allow exactly one numeric character for the additional refinement
1838 // step parameter.
1839 if (RefStepString.size() == 1) {
1840 char RefStepChar = RefStepString[0];
1841 if (RefStepChar >= '0' && RefStepChar <= '9') {
1842 Value = RefStepChar - '0';
1843 return true;
1844 }
1845 }
1846 report_fatal_error("Invalid refinement step for -recip.");
1847 }
1848
1849 /// For the input attribute string, return one of the ReciprocalEstimate enum
1850 /// status values (enabled, disabled, or not specified) for this operation on
1851 /// the specified data type.
1852 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1853 if (Override.empty())
1854 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1855
1856 SmallVector<StringRef, 4> OverrideVector;
1857 Override.split(OverrideVector, ',');
1858 unsigned NumArgs = OverrideVector.size();
1859
1860 // Check if "all", "none", or "default" was specified.
1861 if (NumArgs == 1) {
1862 // Look for an optional setting of the number of refinement steps needed
1863 // for this type of reciprocal operation.
1864 size_t RefPos;
1865 uint8_t RefSteps;
1866 if (parseRefinementStep(Override, RefPos, RefSteps)) {
1867 // Split the string for further processing.
1868 Override = Override.substr(0, RefPos);
1869 }
1870
1871 // All reciprocal types are enabled.
1872 if (Override == "all")
1873 return TargetLoweringBase::ReciprocalEstimate::Enabled;
1874
1875 // All reciprocal types are disabled.
1876 if (Override == "none")
1877 return TargetLoweringBase::ReciprocalEstimate::Disabled;
1878
1879 // Target defaults for enablement are used.
1880 if (Override == "default")
1881 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1882 }
1883
1884 // The attribute string may omit the size suffix ('f'/'d').
1885 std::string VTName = getReciprocalOpName(IsSqrt, VT);
1886 std::string VTNameNoSize = VTName;
1887 VTNameNoSize.pop_back();
1888 static const char DisabledPrefix = '!';
1889
1890 for (StringRef RecipType : OverrideVector) {
1891 size_t RefPos;
1892 uint8_t RefSteps;
1893 if (parseRefinementStep(RecipType, RefPos, RefSteps))
1894 RecipType = RecipType.substr(0, RefPos);
1895
1896 // Ignore the disablement token for string matching.
1897 bool IsDisabled = RecipType[0] == DisabledPrefix;
1898 if (IsDisabled)
1899 RecipType = RecipType.substr(1);
1900
1901 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1902 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1903 : TargetLoweringBase::ReciprocalEstimate::Enabled;
1904 }
1905
1906 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1907 }
1908
1909 /// For the input attribute string, return the customized refinement step count
1910 /// for this operation on the specified data type. If the step count does not
1911 /// exist, return the ReciprocalEstimate enum value for unspecified.
1912 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1913 if (Override.empty())
1914 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1915
1916 SmallVector<StringRef, 4> OverrideVector;
1917 Override.split(OverrideVector, ',');
1918 unsigned NumArgs = OverrideVector.size();
1919
1920 // Check if "all", "default", or "none" was specified.
1921 if (NumArgs == 1) {
1922 // Look for an optional setting of the number of refinement steps needed
1923 // for this type of reciprocal operation.
1924 size_t RefPos;
1925 uint8_t RefSteps;
1926 if (!parseRefinementStep(Override, RefPos, RefSteps))
1927 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1928
1929 // Split the string for further processing.
1930 Override = Override.substr(0, RefPos);
1931 assert(Override != "none" &&
1932 "Disabled reciprocals, but specifed refinement steps?");
1933
1934 // If this is a general override, return the specified number of steps.
1935 if (Override == "all" || Override == "default")
1936 return RefSteps;
1937 }
1938
1939 // The attribute string may omit the size suffix ('f'/'d').
1940 std::string VTName = getReciprocalOpName(IsSqrt, VT);
1941 std::string VTNameNoSize = VTName;
1942 VTNameNoSize.pop_back();
1943
1944 for (StringRef RecipType : OverrideVector) {
1945 size_t RefPos;
1946 uint8_t RefSteps;
1947 if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1948 continue;
1949
1950 RecipType = RecipType.substr(0, RefPos);
1951 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1952 return RefSteps;
1953 }
1954
1955 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1956 }
1957
1958 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
1959 MachineFunction &MF) const {
1960 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1961 }
1962
1963 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
1964 MachineFunction &MF) const {
1965 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1966 }
1967
1968 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
1969 MachineFunction &MF) const {
1970 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1971 }
1972
1973 int TargetLoweringBase::getDivRefinementSteps(EVT VT,
1974 MachineFunction &MF) const {
1975 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
1976 }
1977
1978 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
1979 MF.getRegInfo().freezeReservedRegs(MF);
1980 }
The low level virtual machine