lib/Target/PowerPC/PPCMachineFunctionInfo.h

   1 //===-- PPCMachineFunctionInfo.h - Private data used for PowerPC --*- C++ -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file declares the PowerPC specific subclass of MachineFunctionInfo.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
  15 #define LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
  16
  17 #include "llvm/ADT/SmallVector.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/TargetCallingConv.h"
  20
  21 namespace llvm {
  22
  23 /// PPCFunctionInfo - This class is derived from MachineFunction private
  24 /// PowerPC target-specific information for each MachineFunction.
  25 class PPCFunctionInfo : public MachineFunctionInfo {
  26   virtual void anchor();
  27
  28   /// FramePointerSaveIndex - Frame index of where the old frame pointer is
  29   /// stored.  Also used as an anchor for instructions that need to be altered
  30   /// when using frame pointers (dyna_add, dyna_sub.)
  31   int FramePointerSaveIndex = 0;
  32
  33   /// ReturnAddrSaveIndex - Frame index of where the return address is stored.
  34   ///
  35   int ReturnAddrSaveIndex = 0;
  36
  37   /// Frame index where the old base pointer is stored.
  38   int BasePointerSaveIndex = 0;
  39
  40   /// Frame index where the old PIC base pointer is stored.
  41   int PICBasePointerSaveIndex = 0;
  42
  43   /// MustSaveLR - Indicates whether LR is defined (or clobbered) in the current
  44   /// function.  This is only valid after the initial scan of the function by
  45   /// PEI.
  46   bool MustSaveLR;
  47
  48   /// Does this function have any stack spills.
  49   bool HasSpills = false;
  50
  51   /// Does this function spill using instructions with only r+r (not r+i)
  52   /// forms.
  53   bool HasNonRISpills = false;
  54
  55   /// SpillsCR - Indicates whether CR is spilled in the current function.
  56   bool SpillsCR = false;
  57
  58   /// Indicates whether VRSAVE is spilled in the current function.
  59   bool SpillsVRSAVE = false;
  60
  61   /// LRStoreRequired - The bool indicates whether there is some explicit use of
  62   /// the LR/LR8 stack slot that is not obvious from scanning the code.  This
  63   /// requires that the code generator produce a store of LR to the stack on
  64   /// entry, even though LR may otherwise apparently not be used.
  65   bool LRStoreRequired = false;
  66
  67   /// This function makes use of the PPC64 ELF TOC base pointer (register r2).
  68   bool UsesTOCBasePtr = false;
  69
  70   /// MinReservedArea - This is the frame size that is at least reserved in a
  71   /// potential caller (parameter+linkage area).
  72   unsigned MinReservedArea = 0;
  73
  74   /// TailCallSPDelta - Stack pointer delta used when tail calling. Maximum
  75   /// amount the stack pointer is adjusted to make the frame bigger for tail
  76   /// calls. Used for creating an area before the register spill area.
  77   int TailCallSPDelta = 0;
  78
  79   /// HasFastCall - Does this function contain a fast call. Used to determine
  80   /// how the caller's stack pointer should be calculated (epilog/dynamicalloc).
  81   bool HasFastCall = false;
  82
  83   /// VarArgsFrameIndex - FrameIndex for start of varargs area.
  84   int VarArgsFrameIndex = 0;
  85
  86   /// VarArgsStackOffset - StackOffset for start of stack
  87   /// arguments.
  88
  89   int VarArgsStackOffset = 0;
  90
  91   /// VarArgsNumGPR - Index of the first unused integer
  92   /// register for parameter passing.
  93   unsigned VarArgsNumGPR = 0;
  94
  95   /// VarArgsNumFPR - Index of the first unused double
  96   /// register for parameter passing.
  97   unsigned VarArgsNumFPR = 0;
  98
  99   /// CRSpillFrameIndex - FrameIndex for CR spill slot for 32-bit SVR4.
 100   int CRSpillFrameIndex = 0;
 101
 102   /// If any of CR[2-4] need to be saved in the prologue and restored in the
 103   /// epilogue then they are added to this array. This is used for the
 104   /// 64-bit SVR4 ABI.
 105   SmallVector<unsigned, 3> MustSaveCRs;
 106
 107   /// Hold onto our MachineFunction context.
 108   MachineFunction &MF;
 109
 110   /// Whether this uses the PIC Base register or not.
 111   bool UsesPICBase = false;
 112
 113   /// True if this function has a subset of CSRs that is handled explicitly via
 114   /// copies
 115   bool IsSplitCSR = false;
 116
 117   /// We keep track attributes for each live-in virtual registers
 118   /// to use SExt/ZExt flags in later optimization.
 119   std::vector<std::pair<unsigned, ISD::ArgFlagsTy>> LiveInAttrs;
 120
 121 public:
 122   explicit PPCFunctionInfo(MachineFunction &MF) : MF(MF) {}
 123
 124   int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
 125   void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
 126
 127   int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; }
 128   void setReturnAddrSaveIndex(int idx) { ReturnAddrSaveIndex = idx; }
 129
 130   int getBasePointerSaveIndex() const { return BasePointerSaveIndex; }
 131   void setBasePointerSaveIndex(int Idx) { BasePointerSaveIndex = Idx; }
 132
 133   int getPICBasePointerSaveIndex() const { return PICBasePointerSaveIndex; }
 134   void setPICBasePointerSaveIndex(int Idx) { PICBasePointerSaveIndex = Idx; }
 135
 136   unsigned getMinReservedArea() const { return MinReservedArea; }
 137   void setMinReservedArea(unsigned size) { MinReservedArea = size; }
 138
 139   int getTailCallSPDelta() const { return TailCallSPDelta; }
 140   void setTailCallSPDelta(int size) { TailCallSPDelta = size; }
 141
 142   /// MustSaveLR - This is set when the prolog/epilog inserter does its initial
 143   /// scan of the function. It is true if the LR/LR8 register is ever explicitly
 144   /// defined/clobbered in the machine function (e.g. by calls and movpctolr,
 145   /// which is used in PIC generation), or if the LR stack slot is explicitly
 146   /// referenced by builtin_return_address.
 147   void setMustSaveLR(bool U) { MustSaveLR = U; }
 148   bool mustSaveLR() const    { return MustSaveLR; }
 149
 150   void setHasSpills()      { HasSpills = true; }
 151   bool hasSpills() const   { return HasSpills; }
 152
 153   void setHasNonRISpills()    { HasNonRISpills = true; }
 154   bool hasNonRISpills() const { return HasNonRISpills; }
 155
 156   void setSpillsCR()       { SpillsCR = true; }
 157   bool isCRSpilled() const { return SpillsCR; }
 158
 159   void setSpillsVRSAVE()       { SpillsVRSAVE = true; }
 160   bool isVRSAVESpilled() const { return SpillsVRSAVE; }
 161
 162   void setLRStoreRequired() { LRStoreRequired = true; }
 163   bool isLRStoreRequired() const { return LRStoreRequired; }
 164
 165   void setUsesTOCBasePtr()    { UsesTOCBasePtr = true; }
 166   bool usesTOCBasePtr() const { return UsesTOCBasePtr; }
 167
 168   void setHasFastCall() { HasFastCall = true; }
 169   bool hasFastCall() const { return HasFastCall;}
 170
 171   int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
 172   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
 173
 174   int getVarArgsStackOffset() const { return VarArgsStackOffset; }
 175   void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; }
 176
 177   unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; }
 178   void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; }
 179
 180   unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; }
 181   void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; }
 182
 183   /// This function associates attributes for each live-in virtual register.
 184   void addLiveInAttr(unsigned VReg, ISD::ArgFlagsTy Flags) {
 185     LiveInAttrs.push_back(std::make_pair(VReg, Flags));
 186   }
 187
 188   /// This function returns true if the spesified vreg is
 189   /// a live-in register and sign-extended.
 190   bool isLiveInSExt(unsigned VReg) const;
 191
 192   /// This function returns true if the spesified vreg is
 193   /// a live-in register and zero-extended.
 194   bool isLiveInZExt(unsigned VReg) const;
 195
 196   int getCRSpillFrameIndex() const { return CRSpillFrameIndex; }
 197   void setCRSpillFrameIndex(int idx) { CRSpillFrameIndex = idx; }
 198
 199   const SmallVectorImpl<unsigned> &
 200     getMustSaveCRs() const { return MustSaveCRs; }
 201   void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); }
 202
 203   void setUsesPICBase(bool uses) { UsesPICBase = uses; }
 204   bool usesPICBase() const { return UsesPICBase; }
 205
 206   bool isSplitCSR() const { return IsSplitCSR; }
 207   void setIsSplitCSR(bool s) { IsSplitCSR = s; }
 208
 209   MCSymbol *getPICOffsetSymbol() const;
 210
 211   MCSymbol *getGlobalEPSymbol() const;
 212   MCSymbol *getLocalEPSymbol() const;
 213   MCSymbol *getTOCOffsetSymbol() const;
 214 };
 215
 216 } // end namespace llvm
 217
 218 #endif // LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H