[llvm-exegesis][NFC] Pass Instruction instead of bare Opcode
[llvm-core.git] / lib / CodeGen / MachineInstrBundle.cpp
blobae378cc8c4647668aa1260222b0574e1b7ab6ef7
1 //===-- lib/CodeGen/MachineInstrBundle.cpp --------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
10 #include "llvm/CodeGen/MachineInstrBundle.h"
11 #include "llvm/ADT/SmallSet.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/CodeGen/TargetInstrInfo.h"
17 #include "llvm/CodeGen/TargetRegisterInfo.h"
18 #include "llvm/CodeGen/TargetSubtargetInfo.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include <utility>
21 using namespace llvm;
23 namespace {
24 class UnpackMachineBundles : public MachineFunctionPass {
25 public:
26 static char ID; // Pass identification
27 UnpackMachineBundles(
28 std::function<bool(const MachineFunction &)> Ftor = nullptr)
29 : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
30 initializeUnpackMachineBundlesPass(*PassRegistry::getPassRegistry());
33 bool runOnMachineFunction(MachineFunction &MF) override;
35 private:
36 std::function<bool(const MachineFunction &)> PredicateFtor;
38 } // end anonymous namespace
40 char UnpackMachineBundles::ID = 0;
41 char &llvm::UnpackMachineBundlesID = UnpackMachineBundles::ID;
42 INITIALIZE_PASS(UnpackMachineBundles, "unpack-mi-bundles",
43 "Unpack machine instruction bundles", false, false)
45 bool UnpackMachineBundles::runOnMachineFunction(MachineFunction &MF) {
46 if (PredicateFtor && !PredicateFtor(MF))
47 return false;
49 bool Changed = false;
50 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
51 MachineBasicBlock *MBB = &*I;
53 for (MachineBasicBlock::instr_iterator MII = MBB->instr_begin(),
54 MIE = MBB->instr_end(); MII != MIE; ) {
55 MachineInstr *MI = &*MII;
57 // Remove BUNDLE instruction and the InsideBundle flags from bundled
58 // instructions.
59 if (MI->isBundle()) {
60 while (++MII != MIE && MII->isBundledWithPred()) {
61 MII->unbundleFromPred();
62 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
63 MachineOperand &MO = MII->getOperand(i);
64 if (MO.isReg() && MO.isInternalRead())
65 MO.setIsInternalRead(false);
68 MI->eraseFromParent();
70 Changed = true;
71 continue;
74 ++MII;
78 return Changed;
81 FunctionPass *
82 llvm::createUnpackMachineBundles(
83 std::function<bool(const MachineFunction &)> Ftor) {
84 return new UnpackMachineBundles(std::move(Ftor));
87 namespace {
88 class FinalizeMachineBundles : public MachineFunctionPass {
89 public:
90 static char ID; // Pass identification
91 FinalizeMachineBundles() : MachineFunctionPass(ID) {
92 initializeFinalizeMachineBundlesPass(*PassRegistry::getPassRegistry());
95 bool runOnMachineFunction(MachineFunction &MF) override;
97 } // end anonymous namespace
99 char FinalizeMachineBundles::ID = 0;
100 char &llvm::FinalizeMachineBundlesID = FinalizeMachineBundles::ID;
101 INITIALIZE_PASS(FinalizeMachineBundles, "finalize-mi-bundles",
102 "Finalize machine instruction bundles", false, false)
104 bool FinalizeMachineBundles::runOnMachineFunction(MachineFunction &MF) {
105 return llvm::finalizeBundles(MF);
108 /// Return the first found DebugLoc that has a DILocation, given a range of
109 /// instructions. The search range is from FirstMI to LastMI (exclusive). If no
110 /// DILocation is found, then an empty location is returned.
111 static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI,
112 MachineBasicBlock::instr_iterator LastMI) {
113 for (auto MII = FirstMI; MII != LastMI; ++MII)
114 if (MII->getDebugLoc().get())
115 return MII->getDebugLoc();
116 return DebugLoc();
119 /// finalizeBundle - Finalize a machine instruction bundle which includes
120 /// a sequence of instructions starting from FirstMI to LastMI (exclusive).
121 /// This routine adds a BUNDLE instruction to represent the bundle, it adds
122 /// IsInternalRead markers to MachineOperands which are defined inside the
123 /// bundle, and it copies externally visible defs and uses to the BUNDLE
124 /// instruction.
125 void llvm::finalizeBundle(MachineBasicBlock &MBB,
126 MachineBasicBlock::instr_iterator FirstMI,
127 MachineBasicBlock::instr_iterator LastMI) {
128 assert(FirstMI != LastMI && "Empty bundle?");
129 MIBundleBuilder Bundle(MBB, FirstMI, LastMI);
131 MachineFunction &MF = *MBB.getParent();
132 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
133 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
135 MachineInstrBuilder MIB =
136 BuildMI(MF, getDebugLoc(FirstMI, LastMI), TII->get(TargetOpcode::BUNDLE));
137 Bundle.prepend(MIB);
139 SmallVector<unsigned, 32> LocalDefs;
140 SmallSet<unsigned, 32> LocalDefSet;
141 SmallSet<unsigned, 8> DeadDefSet;
142 SmallSet<unsigned, 16> KilledDefSet;
143 SmallVector<unsigned, 8> ExternUses;
144 SmallSet<unsigned, 8> ExternUseSet;
145 SmallSet<unsigned, 8> KilledUseSet;
146 SmallSet<unsigned, 8> UndefUseSet;
147 SmallVector<MachineOperand*, 4> Defs;
148 for (auto MII = FirstMI; MII != LastMI; ++MII) {
149 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
150 MachineOperand &MO = MII->getOperand(i);
151 if (!MO.isReg())
152 continue;
153 if (MO.isDef()) {
154 Defs.push_back(&MO);
155 continue;
158 unsigned Reg = MO.getReg();
159 if (!Reg)
160 continue;
161 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
162 if (LocalDefSet.count(Reg)) {
163 MO.setIsInternalRead();
164 if (MO.isKill())
165 // Internal def is now killed.
166 KilledDefSet.insert(Reg);
167 } else {
168 if (ExternUseSet.insert(Reg).second) {
169 ExternUses.push_back(Reg);
170 if (MO.isUndef())
171 UndefUseSet.insert(Reg);
173 if (MO.isKill())
174 // External def is now killed.
175 KilledUseSet.insert(Reg);
179 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
180 MachineOperand &MO = *Defs[i];
181 unsigned Reg = MO.getReg();
182 if (!Reg)
183 continue;
185 if (LocalDefSet.insert(Reg).second) {
186 LocalDefs.push_back(Reg);
187 if (MO.isDead()) {
188 DeadDefSet.insert(Reg);
190 } else {
191 // Re-defined inside the bundle, it's no longer killed.
192 KilledDefSet.erase(Reg);
193 if (!MO.isDead())
194 // Previously defined but dead.
195 DeadDefSet.erase(Reg);
198 if (!MO.isDead()) {
199 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
200 unsigned SubReg = *SubRegs;
201 if (LocalDefSet.insert(SubReg).second)
202 LocalDefs.push_back(SubReg);
207 Defs.clear();
210 SmallSet<unsigned, 32> Added;
211 for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
212 unsigned Reg = LocalDefs[i];
213 if (Added.insert(Reg).second) {
214 // If it's not live beyond end of the bundle, mark it dead.
215 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg);
216 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
217 getImplRegState(true));
221 for (unsigned i = 0, e = ExternUses.size(); i != e; ++i) {
222 unsigned Reg = ExternUses[i];
223 bool isKill = KilledUseSet.count(Reg);
224 bool isUndef = UndefUseSet.count(Reg);
225 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
226 getImplRegState(true));
229 // Set FrameSetup/FrameDestroy for the bundle. If any of the instructions got
230 // the property, then also set it on the bundle.
231 for (auto MII = FirstMI; MII != LastMI; ++MII) {
232 if (MII->getFlag(MachineInstr::FrameSetup))
233 MIB.setMIFlag(MachineInstr::FrameSetup);
234 if (MII->getFlag(MachineInstr::FrameDestroy))
235 MIB.setMIFlag(MachineInstr::FrameDestroy);
239 /// finalizeBundle - Same functionality as the previous finalizeBundle except
240 /// the last instruction in the bundle is not provided as an input. This is
241 /// used in cases where bundles are pre-determined by marking instructions
242 /// with 'InsideBundle' marker. It returns the MBB instruction iterator that
243 /// points to the end of the bundle.
244 MachineBasicBlock::instr_iterator
245 llvm::finalizeBundle(MachineBasicBlock &MBB,
246 MachineBasicBlock::instr_iterator FirstMI) {
247 MachineBasicBlock::instr_iterator E = MBB.instr_end();
248 MachineBasicBlock::instr_iterator LastMI = std::next(FirstMI);
249 while (LastMI != E && LastMI->isInsideBundle())
250 ++LastMI;
251 finalizeBundle(MBB, FirstMI, LastMI);
252 return LastMI;
255 /// finalizeBundles - Finalize instruction bundles in the specified
256 /// MachineFunction. Return true if any bundles are finalized.
257 bool llvm::finalizeBundles(MachineFunction &MF) {
258 bool Changed = false;
259 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
260 MachineBasicBlock &MBB = *I;
261 MachineBasicBlock::instr_iterator MII = MBB.instr_begin();
262 MachineBasicBlock::instr_iterator MIE = MBB.instr_end();
263 if (MII == MIE)
264 continue;
265 assert(!MII->isInsideBundle() &&
266 "First instr cannot be inside bundle before finalization!");
268 for (++MII; MII != MIE; ) {
269 if (!MII->isInsideBundle())
270 ++MII;
271 else {
272 MII = finalizeBundle(MBB, std::prev(MII));
273 Changed = true;
278 return Changed;
281 //===----------------------------------------------------------------------===//
282 // MachineOperand iterator
283 //===----------------------------------------------------------------------===//
285 MachineOperandIteratorBase::VirtRegInfo
286 MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg,
287 SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) {
288 VirtRegInfo RI = { false, false, false };
289 for(; isValid(); ++*this) {
290 MachineOperand &MO = deref();
291 if (!MO.isReg() || MO.getReg() != Reg)
292 continue;
294 // Remember each (MI, OpNo) that refers to Reg.
295 if (Ops)
296 Ops->push_back(std::make_pair(MO.getParent(), getOperandNo()));
298 // Both defs and uses can read virtual registers.
299 if (MO.readsReg()) {
300 RI.Reads = true;
301 if (MO.isDef())
302 RI.Tied = true;
305 // Only defs can write.
306 if (MO.isDef())
307 RI.Writes = true;
308 else if (!RI.Tied && MO.getParent()->isRegTiedToDefOperand(getOperandNo()))
309 RI.Tied = true;
311 return RI;
314 MachineOperandIteratorBase::PhysRegInfo
315 MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
316 const TargetRegisterInfo *TRI) {
317 bool AllDefsDead = true;
318 PhysRegInfo PRI = {false, false, false, false, false, false, false, false};
320 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
321 "analyzePhysReg not given a physical register!");
322 for (; isValid(); ++*this) {
323 MachineOperand &MO = deref();
325 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
326 PRI.Clobbered = true;
327 continue;
330 if (!MO.isReg())
331 continue;
333 unsigned MOReg = MO.getReg();
334 if (!MOReg || !TargetRegisterInfo::isPhysicalRegister(MOReg))
335 continue;
337 if (!TRI->regsOverlap(MOReg, Reg))
338 continue;
340 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg);
341 if (MO.readsReg()) {
342 PRI.Read = true;
343 if (Covered) {
344 PRI.FullyRead = true;
345 if (MO.isKill())
346 PRI.Killed = true;
348 } else if (MO.isDef()) {
349 PRI.Defined = true;
350 if (Covered)
351 PRI.FullyDefined = true;
352 if (!MO.isDead())
353 AllDefsDead = false;
357 if (AllDefsDead) {
358 if (PRI.FullyDefined || PRI.Clobbered)
359 PRI.DeadDef = true;
360 else if (PRI.Defined)
361 PRI.PartialDeadDef = true;
364 return PRI;