lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // ARM Subtarget state.
  20 //
  21
  22 def ModeThumb             : SubtargetFeature<"thumb-mode", "InThumbMode",
  23                                              "true", "Thumb mode">;
  24
  25 def ModeSoftFloat         : SubtargetFeature<"soft-float","UseSoftFloat",
  26                                              "true", "Use software floating "
  27                                              "point features.">;
  28
  29
  30 //===----------------------------------------------------------------------===//
  31 // ARM Subtarget features.
  32 //
  33
  34 // Floating Point, HW Division and Neon Support
  35
  36 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
  37 // version).
  38 def FeatureFPRegs         : SubtargetFeature<"fpregs", "HasFPRegs", "true",
  39                                              "Enable FP registers">;
  40
  41 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
  42 // extension) and MVE (even in the integer-only version).
  43 def FeatureFPRegs16       : SubtargetFeature<"fpregs16", "HasFPRegs16", "true",
  44                                              "Enable 16-bit FP registers",
  45                                              [FeatureFPRegs]>;
  46
  47 def FeatureFPRegs64       : SubtargetFeature<"fpregs64", "HasFPRegs64", "true",
  48                                              "Enable 64-bit FP registers",
  49                                              [FeatureFPRegs]>;
  50
  51 def FeatureFP64           : SubtargetFeature<"fp64", "HasFP64", "true",
  52                                              "Floating point unit supports "
  53                                              "double precision",
  54                                              [FeatureFPRegs64]>;
  55
  56 def FeatureD32            : SubtargetFeature<"d32", "HasD32", "true",
  57                                              "Extend FP to 32 double registers">;
  58
  59 multiclass VFPver<string name, string query, string description,
  60                   list<SubtargetFeature> prev = [],
  61                   list<SubtargetFeature> otherimplies = []> {
  62   def _D16_SP: SubtargetFeature<
  63     name#"d16sp", query#"D16SP", "true",
  64     description#" with only 16 d-registers and no double precision",
  65     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # otherimplies>;
  66   def _SP: SubtargetFeature<
  67     name#"sp", query#"SP", "true",
  68     description#" with no double precision",
  69     !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) #
  70       otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
  71   def _D16: SubtargetFeature<
  72     name#"d16", query#"D16", "true",
  73     description#" with only 16 d-registers",
  74     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) #
  75       otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
  76   def "": SubtargetFeature<
  77     name, query, "true", description,
  78     prev # otherimplies # [
  79         !cast<SubtargetFeature>(NAME # "_D16"),
  80         !cast<SubtargetFeature>(NAME # "_SP")]>;
  81 }
  82
  83 defm FeatureVFP2: VFPver<"vfp2", "HasVFPv2", "Enable VFP2 instructions",
  84                          [], [FeatureFPRegs]>;
  85
  86 defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
  87                          [FeatureVFP2]>;
  88
  89 def FeatureNEON           : SubtargetFeature<"neon", "HasNEON", "true",
  90                                              "Enable NEON instructions",
  91                                              [FeatureVFP3]>;
  92
  93 def FeatureFP16           : SubtargetFeature<"fp16", "HasFP16", "true",
  94                                              "Enable half-precision "
  95                                              "floating point">;
  96
  97 defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions",
  98                          [FeatureVFP3], [FeatureFP16]>;
  99
 100 defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
 101                          [FeatureVFP4]>;
 102
 103 def FeatureFullFP16       : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
 104                                              "Enable full half-precision "
 105                                              "floating point",
 106                                              [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>;
 107
 108 def FeatureFP16FML        : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
 109                                              "Enable full half-precision "
 110                                              "floating point fml instructions",
 111                                              [FeatureFullFP16]>;
 112
 113 def FeatureHWDivThumb     : SubtargetFeature<"hwdiv",
 114                                              "HasHardwareDivideInThumb", "true",
 115                                              "Enable divide instructions in Thumb">;
 116
 117 def FeatureHWDivARM       : SubtargetFeature<"hwdiv-arm",
 118                                              "HasHardwareDivideInARM", "true",
 119                                              "Enable divide instructions in ARM mode">;
 120
 121 // Atomic Support
 122 def FeatureDB             : SubtargetFeature<"db", "HasDataBarrier", "true",
 123                                              "Has data barrier (dmb/dsb) instructions">;
 124
 125 def FeatureV7Clrex        : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
 126                                              "Has v7 clrex instruction">;
 127
 128 def FeatureDFB  : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
 129                                    "Has full data barrier (dfb) instruction">;
 130
 131 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
 132                                              "HasAcquireRelease", "true",
 133                                              "Has v8 acquire/release (lda/ldaex "
 134                                              " etc) instructions">;
 135
 136
 137 def FeatureSlowFPBrcc     : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
 138                                              "FP compare + branch is slow">;
 139
 140 def FeaturePerfMon        : SubtargetFeature<"perfmon", "HasPerfMon", "true",
 141                                              "Enable support for Performance "
 142                                              "Monitor extensions">;
 143
 144
 145 // TrustZone Security Extensions
 146 def FeatureTrustZone      : SubtargetFeature<"trustzone", "HasTrustZone", "true",
 147                                              "Enable support for TrustZone "
 148                                              "security extensions">;
 149
 150 def Feature8MSecExt       : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
 151                                              "Enable support for ARMv8-M "
 152                                              "Security Extensions">;
 153
 154 def FeatureSHA2           : SubtargetFeature<"sha2", "HasSHA2", "true",
 155                                              "Enable SHA1 and SHA256 support", [FeatureNEON]>;
 156
 157 def FeatureAES            : SubtargetFeature<"aes", "HasAES", "true",
 158                                              "Enable AES support", [FeatureNEON]>;
 159
 160 def FeatureCrypto         : SubtargetFeature<"crypto", "HasCrypto", "true",
 161                                              "Enable support for "
 162                                              "Cryptography extensions",
 163                                              [FeatureNEON, FeatureSHA2, FeatureAES]>;
 164
 165 def FeatureCRC            : SubtargetFeature<"crc", "HasCRC", "true",
 166                                              "Enable support for CRC instructions">;
 167
 168 def FeatureDotProd        : SubtargetFeature<"dotprod", "HasDotProd", "true",
 169                                              "Enable support for dot product instructions",
 170                                              [FeatureNEON]>;
 171
 172 // Not to be confused with FeatureHasRetAddrStack (return address stack)
 173 def FeatureRAS            : SubtargetFeature<"ras", "HasRAS", "true",
 174                                              "Enable Reliability, Availability "
 175                                              "and Serviceability extensions">;
 176
 177 // Fast computation of non-negative address offsets
 178 def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",
 179                                              "Enable fast computation of "
 180                                              "positive address offsets">;
 181
 182 // Fast execution of AES crypto operations
 183 def FeatureFuseAES        : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
 184                                              "CPU fuses AES crypto operations">;
 185
 186 // Fast execution of bottom and top halves of literal generation
 187 def FeatureFuseLiterals   : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",
 188                                              "CPU fuses literal generation operations">;
 189
 190 // The way of reading thread pointer
 191 def FeatureReadTp :  SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
 192                                       "Reading thread pointer from register">;
 193
 194 // Cyclone can zero VFP registers in 0 cycles.
 195 def FeatureZCZeroing      : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 196                                              "Has zero-cycle zeroing instructions">;
 197
 198 // Whether it is profitable to unpredicate certain instructions during if-conversion
 199 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
 200                                               "IsProfitableToUnpredicate", "true",
 201                                               "Is profitable to unpredicate">;
 202
 203 // Some targets (e.g. Swift) have microcoded VGETLNi32.
 204 def FeatureSlowVGETLNi32  : SubtargetFeature<"slow-vgetlni32",
 205                                              "HasSlowVGETLNi32", "true",
 206                                              "Has slow VGETLNi32 - prefer VMOV">;
 207
 208 // Some targets (e.g. Swift) have microcoded VDUP32.
 209 def FeatureSlowVDUP32     : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
 210                                              "true",
 211                                              "Has slow VDUP32 - prefer VMOV">;
 212
 213 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
 214 // for scalar FP, as this allows more effective execution domain optimization.
 215 def FeaturePreferVMOVSR   : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
 216                                              "true", "Prefer VMOVSR">;
 217
 218 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
 219 // than ISH
 220 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
 221                                                "true", "Prefer ISHST barriers">;
 222
 223 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
 224 def FeatureMuxedUnits     : SubtargetFeature<"muxed-units", "HasMuxedUnits",
 225                                              "true",
 226                                              "Has muxed AGU and NEON/FPU">;
 227
 228 // Whether VLDM/VSTM starting with odd register number need more microops
 229 // than single VLDRS
 230 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
 231                                               "true", "VLDM/VSTM starting "
 232                                               "with an odd register is slow">;
 233
 234 // Some targets have a renaming dependency when loading into D subregisters.
 235 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
 236                                               "SlowLoadDSubregister", "true",
 237                                               "Loading into D subregs is slow">;
 238
 239 def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp",
 240                                                "UseWideStrideVFP", "true",
 241                                                "Use a wide stride when allocating VFP registers">;
 242
 243 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 244 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
 245                                              "DontWidenVMOVS", "true",
 246                                              "Don't widen VMOVS to VMOVD">;
 247
 248 // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
 249 // VFP register widths.
 250 def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon",
 251                                              "SplatVFPToNeon", "true",
 252                                              "Splat register from VFP to NEON",
 253                                              [FeatureDontWidenVMOVS]>;
 254
 255 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 256 def FeatureExpandMLx      : SubtargetFeature<"expand-fp-mlx",
 257                                              "ExpandMLx", "true",
 258                                              "Expand VFP/NEON MLA/MLS instructions">;
 259
 260 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 261 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
 262                                              "true", "Has VMLx hazards">;
 263
 264 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
 265 // VFP to NEON, as an execution domain optimization.
 266 def FeatureNEONForFPMovs  : SubtargetFeature<"neon-fpmovs",
 267                                              "UseNEONForFPMovs", "true",
 268                                              "Convert VMOVSR, VMOVRS, "
 269                                              "VMOVS to NEON">;
 270
 271 // Some processors benefit from using NEON instructions for scalar
 272 // single-precision FP operations. This affects instruction selection and should
 273 // only be enabled if the handling of denormals is not important.
 274 def FeatureNEONForFP      : SubtargetFeature<"neonfp",
 275                                              "UseNEONForSinglePrecisionFP",
 276                                              "true",
 277                                              "Use NEON for single precision FP">;
 278
 279 // On some processors, VLDn instructions that access unaligned data take one
 280 // extra cycle. Take that into account when computing operand latencies.
 281 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
 282                                              "true",
 283                                              "Check for VLDn unaligned access">;
 284
 285 // Some processors have a nonpipelined VFP coprocessor.
 286 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
 287                                               "NonpipelinedVFP", "true",
 288                                               "VFP instructions are not pipelined">;
 289
 290 // Some processors have FP multiply-accumulate instructions that don't
 291 // play nicely with other VFP / NEON instructions, and it's generally better
 292 // to just not use them.
 293 def FeatureHasSlowFPVMLx  : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 294                                              "Disable VFP / NEON MAC instructions">;
 295
 296 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 297 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 298                                              "HasVMLxForwarding", "true",
 299                                              "Has multiplier accumulator forwarding">;
 300
 301 // Disable 32-bit to 16-bit narrowing for experimentation.
 302 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 303                                              "Prefer 32-bit Thumb instrs">;
 304
 305 def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopAlignment","2",
 306                                               "Prefer 32-bit alignment for loops">;
 307
 308 def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1",
 309                         "Model MVE instructions as a 1 beat per tick architecture">;
 310
 311 def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2",
 312                         "Model MVE instructions as a 2 beats per tick architecture">;
 313
 314 def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4",
 315                         "Model MVE instructions as a 4 beats per tick architecture">;
 316
 317 /// Some instructions update CPSR partially, which can add false dependency for
 318 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 319 /// mapped to a separate physical register. Avoid partial CPSR update for these
 320 /// processors.
 321 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 322                                                "AvoidCPSRPartialUpdate", "true",
 323                                  "Avoid CPSR partial update for OOO execution">;
 324
 325 /// Disable +1 predication cost for instructions updating CPSR.
 326 /// Enabled for Cortex-A57.
 327 def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
 328                                                   "CheapPredicableCPSRDef",
 329                                                   "true",
 330                   "Disable +1 predication cost for instructions updating CPSR">;
 331
 332 def FeatureAvoidMOVsShOp  : SubtargetFeature<"avoid-movs-shop",
 333                                              "AvoidMOVsShifterOperand", "true",
 334                                              "Avoid movs instructions with "
 335                                              "shifter operand">;
 336
 337 // Some processors perform return stack prediction. CodeGen should avoid issue
 338 // "normal" call instructions to callees which do not return.
 339 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
 340                                               "HasRetAddrStack", "true",
 341                                               "Has return address stack">;
 342
 343 // Some processors have no branch predictor, which changes the expected cost of
 344 // taking a branch which affects the choice of whether to use predicated
 345 // instructions.
 346 def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
 347                                                    "HasBranchPredictor", "false",
 348                                                    "Has no branch predictor">;
 349
 350 /// DSP extension.
 351 def FeatureDSP            : SubtargetFeature<"dsp", "HasDSP", "true",
 352                                              "Supports DSP instructions in "
 353                                              "ARM and/or Thumb2">;
 354
 355 // Multiprocessing extension.
 356 def FeatureMP             : SubtargetFeature<"mp", "HasMPExtension", "true",
 357                                         "Supports Multiprocessing extension">;
 358
 359 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 360 def FeatureVirtualization : SubtargetFeature<"virtualization",
 361                                              "HasVirtualization", "true",
 362                                              "Supports Virtualization extension",
 363                                              [FeatureHWDivThumb, FeatureHWDivARM]>;
 364
 365 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 366 // See ARMInstrInfo.td for details.
 367 def FeatureNaClTrap       : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 368                                              "NaCl trap">;
 369
 370 def FeatureStrictAlign    : SubtargetFeature<"strict-align",
 371                                              "StrictAlign", "true",
 372                                              "Disallow all unaligned memory "
 373                                              "access">;
 374
 375 def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 376                                              "Generate calls via indirect call "
 377                                              "instructions">;
 378
 379 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
 380                                              "GenExecuteOnly", "true",
 381                                              "Enable the generation of "
 382                                              "execute only code.">;
 383
 384 def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 385                                              "Reserve R9, making it unavailable"
 386                                              " as GPR">;
 387
 388 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
 389                                              "Don't use movt/movw pairs for "
 390                                              "32-bit imms">;
 391
 392 def FeatureNoNegativeImmediates
 393                           : SubtargetFeature<"no-neg-immediates",
 394                                              "NegativeImmediates", "false",
 395                                              "Convert immediates and instructions "
 396                                              "to their negated or complemented "
 397                                              "equivalent when the immediate does "
 398                                              "not fit in the encoding.">;
 399
 400 // Use the MachineScheduler for instruction scheduling for the subtarget.
 401 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
 402                                         "Use the MachineScheduler">;
 403
 404 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
 405     "DisablePostRAScheduler", "true",
 406     "Don't schedule again after register allocation">;
 407
 408 // Enable use of alias analysis during code generation
 409 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
 410                                     "Use alias analysis during codegen">;
 411
 412 // Armv8.5-A extensions
 413
 414 def FeatureSB       : SubtargetFeature<"sb", "HasSB", "true",
 415   "Enable v8.5a Speculation Barrier" >;
 416
 417 // Armv8.1-M extensions
 418
 419 def FeatureLOB            : SubtargetFeature<"lob", "HasLOB", "true",
 420                                              "Enable Low Overhead Branch "
 421                                              "extensions">;
 422
 423 //===----------------------------------------------------------------------===//
 424 // ARM architecture class
 425 //
 426
 427 // A-series ISA
 428 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 429                                      "Is application profile ('A' series)">;
 430
 431 // R-series ISA
 432 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 433                                      "Is realtime profile ('R' series)">;
 434
 435 // M-series ISA
 436 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 437                                      "Is microcontroller profile ('M' series)">;
 438
 439
 440 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
 441                                      "Enable Thumb2 instructions">;
 442
 443 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
 444                                      "Does not support ARM mode execution">;
 445
 446 //===----------------------------------------------------------------------===//
 447 // ARM ISAa.
 448 //
 449
 450 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 451                                    "Support ARM v4T instructions">;
 452
 453 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 454                                    "Support ARM v5T instructions",
 455                                    [HasV4TOps]>;
 456
 457 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 458                                    "Support ARM v5TE, v5TEj, and "
 459                                    "v5TExp instructions",
 460                                    [HasV5TOps]>;
 461
 462 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 463                                    "Support ARM v6 instructions",
 464                                    [HasV5TEOps]>;
 465
 466 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 467                                    "Support ARM v6M instructions",
 468                                    [HasV6Ops]>;
 469
 470 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
 471                                          "Support ARM v8M Baseline instructions",
 472                                          [HasV6MOps]>;
 473
 474 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 475                                    "Support ARM v6k instructions",
 476                                    [HasV6Ops]>;
 477
 478 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 479                                    "Support ARM v6t2 instructions",
 480                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 481
 482 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 483                                    "Support ARM v7 instructions",
 484                                    [HasV6T2Ops, FeaturePerfMon,
 485                                     FeatureV7Clrex]>;
 486
 487 def HasV8MMainlineOps :
 488                   SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
 489                                    "Support ARM v8M Mainline instructions",
 490                                    [HasV7Ops]>;
 491
 492 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 493                                    "Support ARM v8 instructions",
 494                                    [HasV7Ops, FeatureAcquireRelease]>;
 495
 496 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 497                                    "Support ARM v8.1a instructions",
 498                                    [HasV8Ops]>;
 499
 500 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 501                                    "Support ARM v8.2a instructions",
 502                                    [HasV8_1aOps]>;
 503
 504 def HasV8_3aOps   : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 505                                    "Support ARM v8.3a instructions",
 506                                    [HasV8_2aOps]>;
 507
 508 def HasV8_4aOps   : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 509                                    "Support ARM v8.4a instructions",
 510                                    [HasV8_3aOps, FeatureDotProd]>;
 511
 512 def HasV8_5aOps   : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
 513                                    "Support ARM v8.5a instructions",
 514                                    [HasV8_4aOps, FeatureSB]>;
 515
 516 def HasV8_1MMainlineOps : SubtargetFeature<
 517                "v8.1m.main", "HasV8_1MMainlineOps", "true",
 518                "Support ARM v8-1M Mainline instructions",
 519                [HasV8MMainlineOps]>;
 520 def HasMVEIntegerOps : SubtargetFeature<
 521                "mve", "HasMVEIntegerOps", "true",
 522                "Support M-Class Vector Extension with integer ops",
 523                [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>;
 524 def HasMVEFloatOps : SubtargetFeature<
 525                "mve.fp", "HasMVEFloatOps", "true",
 526                "Support M-Class Vector Extension with integer and floating ops",
 527                [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>;
 528
 529 //===----------------------------------------------------------------------===//
 530 // ARM Processor subtarget features.
 531 //
 532
 533 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 534                                    "Cortex-A5 ARM processors", []>;
 535 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 536                                    "Cortex-A7 ARM processors", []>;
 537 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 538                                    "Cortex-A8 ARM processors", []>;
 539 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 540                                    "Cortex-A9 ARM processors", []>;
 541 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 542                                    "Cortex-A12 ARM processors", []>;
 543 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 544                                    "Cortex-A15 ARM processors", []>;
 545 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 546                                    "Cortex-A17 ARM processors", []>;
 547 def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
 548                                    "Cortex-A32 ARM processors", []>;
 549 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 550                                    "Cortex-A35 ARM processors", []>;
 551 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 552                                    "Cortex-A53 ARM processors", []>;
 553 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 554                                    "Cortex-A55 ARM processors", []>;
 555 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 556                                    "Cortex-A57 ARM processors", []>;
 557 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 558                                    "Cortex-A72 ARM processors", []>;
 559 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 560                                    "Cortex-A73 ARM processors", []>;
 561 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 562                                    "Cortex-A75 ARM processors", []>;
 563 def ProcA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
 564                                    "Cortex-A76 ARM processors", []>;
 565
 566 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 567                                    "Qualcomm Krait processors", []>;
 568 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 569                                    "Qualcomm Kryo processors", []>;
 570 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 571                                    "Swift ARM processors", []>;
 572
 573 def ProcExynos  : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",
 574                                    "Samsung Exynos processors",
 575                                    [FeatureZCZeroing,
 576                                     FeatureUseWideStrideVFP,
 577                                     FeatureUseAA,
 578                                     FeatureSplatVFPToNeon,
 579                                     FeatureSlowVGETLNi32,
 580                                     FeatureSlowVDUP32,
 581                                     FeatureSlowFPBrcc,
 582                                     FeatureProfUnpredicate,
 583                                     FeatureHWDivThumb,
 584                                     FeatureHWDivARM,
 585                                     FeatureHasSlowFPVMLx,
 586                                     FeatureHasRetAddrStack,
 587                                     FeatureFuseLiterals,
 588                                     FeatureFuseAES,
 589                                     FeatureExpandMLx,
 590                                     FeatureCrypto,
 591                                     FeatureCRC]>;
 592
 593 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 594                                    "Cortex-R4 ARM processors", []>;
 595 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 596                                    "Cortex-R5 ARM processors", []>;
 597 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 598                                    "Cortex-R7 ARM processors", []>;
 599 def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 600                                    "Cortex-R52 ARM processors", []>;
 601
 602 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
 603                                    "Cortex-M3 ARM processors", []>;
 604
 605
 606 //===----------------------------------------------------------------------===//
 607 // ARM Helper classes.
 608 //
 609
 610 class Architecture<string fname, string aname, list<SubtargetFeature> features>
 611   : SubtargetFeature<fname, "ARMArch", aname,
 612                      !strconcat(aname, " architecture"), features>;
 613
 614 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 615   : Processor<Name, NoItineraries, Features>;
 616
 617
 618 //===----------------------------------------------------------------------===//
 619 // ARM architectures
 620 //
 621
 622 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 623
 624 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 625
 626 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 627
 628 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 629
 630 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 631
 632 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 633
 634 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 635
 636 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 637
 638 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 639
 640 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops,
 641                                                        FeatureDSP]>;
 642
 643 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 644                                                        FeatureDSP]>;
 645
 646 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 647
 648 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 649                                                        FeatureTrustZone]>;
 650
 651 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 652                                                        FeatureNoARM,
 653                                                        ModeThumb,
 654                                                        FeatureDB,
 655                                                        FeatureMClass,
 656                                                        FeatureStrictAlign]>;
 657
 658 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 659                                                        FeatureNoARM,
 660                                                        ModeThumb,
 661                                                        FeatureDB,
 662                                                        FeatureMClass,
 663                                                        FeatureStrictAlign]>;
 664
 665 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 666                                                        FeatureNEON,
 667                                                        FeatureDB,
 668                                                        FeatureDSP,
 669                                                        FeatureAClass]>;
 670
 671 def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
 672                                                        FeatureNEON,
 673                                                        FeatureDB,
 674                                                        FeatureDSP,
 675                                                        FeatureTrustZone,
 676                                                        FeatureMP,
 677                                                        FeatureVirtualization,
 678                                                        FeatureAClass]>;
 679
 680 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 681                                                        FeatureDB,
 682                                                        FeatureDSP,
 683                                                        FeatureHWDivThumb,
 684                                                        FeatureRClass]>;
 685
 686 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 687                                                        FeatureThumb2,
 688                                                        FeatureNoARM,
 689                                                        ModeThumb,
 690                                                        FeatureDB,
 691                                                        FeatureHWDivThumb,
 692                                                        FeatureMClass]>;
 693
 694 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 695                                                        FeatureThumb2,
 696                                                        FeatureNoARM,
 697                                                        ModeThumb,
 698                                                        FeatureDB,
 699                                                        FeatureHWDivThumb,
 700                                                        FeatureMClass,
 701                                                        FeatureDSP]>;
 702
 703 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 704                                                        FeatureAClass,
 705                                                        FeatureDB,
 706                                                        FeatureFPARMv8,
 707                                                        FeatureNEON,
 708                                                        FeatureDSP,
 709                                                        FeatureTrustZone,
 710                                                        FeatureMP,
 711                                                        FeatureVirtualization,
 712                                                        FeatureCrypto,
 713                                                        FeatureCRC]>;
 714
 715 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 716                                                        FeatureAClass,
 717                                                        FeatureDB,
 718                                                        FeatureFPARMv8,
 719                                                        FeatureNEON,
 720                                                        FeatureDSP,
 721                                                        FeatureTrustZone,
 722                                                        FeatureMP,
 723                                                        FeatureVirtualization,
 724                                                        FeatureCrypto,
 725                                                        FeatureCRC]>;
 726
 727 def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
 728                                                        FeatureAClass,
 729                                                        FeatureDB,
 730                                                        FeatureFPARMv8,
 731                                                        FeatureNEON,
 732                                                        FeatureDSP,
 733                                                        FeatureTrustZone,
 734                                                        FeatureMP,
 735                                                        FeatureVirtualization,
 736                                                        FeatureCrypto,
 737                                                        FeatureCRC,
 738                                                        FeatureRAS]>;
 739
 740 def ARMv83a   : Architecture<"armv8.3-a", "ARMv83a",  [HasV8_3aOps,
 741                                                        FeatureAClass,
 742                                                        FeatureDB,
 743                                                        FeatureFPARMv8,
 744                                                        FeatureNEON,
 745                                                        FeatureDSP,
 746                                                        FeatureTrustZone,
 747                                                        FeatureMP,
 748                                                        FeatureVirtualization,
 749                                                        FeatureCrypto,
 750                                                        FeatureCRC,
 751                                                        FeatureRAS]>;
 752
 753 def ARMv84a   : Architecture<"armv8.4-a", "ARMv84a",  [HasV8_4aOps,
 754                                                        FeatureAClass,
 755                                                        FeatureDB,
 756                                                        FeatureFPARMv8,
 757                                                        FeatureNEON,
 758                                                        FeatureDSP,
 759                                                        FeatureTrustZone,
 760                                                        FeatureMP,
 761                                                        FeatureVirtualization,
 762                                                        FeatureCrypto,
 763                                                        FeatureCRC,
 764                                                        FeatureRAS,
 765                                                        FeatureDotProd]>;
 766
 767 def ARMv85a   : Architecture<"armv8.5-a", "ARMv85a",  [HasV8_5aOps,
 768                                                        FeatureAClass,
 769                                                        FeatureDB,
 770                                                        FeatureFPARMv8,
 771                                                        FeatureNEON,
 772                                                        FeatureDSP,
 773                                                        FeatureTrustZone,
 774                                                        FeatureMP,
 775                                                        FeatureVirtualization,
 776                                                        FeatureCrypto,
 777                                                        FeatureCRC,
 778                                                        FeatureRAS,
 779                                                        FeatureDotProd]>;
 780
 781 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
 782                                                        FeatureRClass,
 783                                                        FeatureDB,
 784                                                        FeatureDFB,
 785                                                        FeatureDSP,
 786                                                        FeatureCRC,
 787                                                        FeatureMP,
 788                                                        FeatureVirtualization,
 789                                                        FeatureFPARMv8,
 790                                                        FeatureNEON]>;
 791
 792 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
 793                                                       [HasV8MBaselineOps,
 794                                                        FeatureNoARM,
 795                                                        ModeThumb,
 796                                                        FeatureDB,
 797                                                        FeatureHWDivThumb,
 798                                                        FeatureV7Clrex,
 799                                                        Feature8MSecExt,
 800                                                        FeatureAcquireRelease,
 801                                                        FeatureMClass,
 802                                                        FeatureStrictAlign]>;
 803
 804 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
 805                                                       [HasV8MMainlineOps,
 806                                                        FeatureNoARM,
 807                                                        ModeThumb,
 808                                                        FeatureDB,
 809                                                        FeatureHWDivThumb,
 810                                                        Feature8MSecExt,
 811                                                        FeatureAcquireRelease,
 812                                                        FeatureMClass]>;
 813
 814 def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline",
 815                                                       [HasV8_1MMainlineOps,
 816                                                        FeatureNoARM,
 817                                                        ModeThumb,
 818                                                        FeatureDB,
 819                                                        FeatureHWDivThumb,
 820                                                        Feature8MSecExt,
 821                                                        FeatureAcquireRelease,
 822                                                        FeatureMClass,
 823                                                        FeatureRAS,
 824                                                        FeatureLOB]>;
 825
 826 // Aliases
 827 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 828 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 829 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 830 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 831 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 832 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 833
 834
 835 //===----------------------------------------------------------------------===//
 836 // ARM schedules.
 837 //===----------------------------------------------------------------------===//
 838 //
 839 include "ARMPredicates.td"
 840 include "ARMSchedule.td"
 841
 842 //===----------------------------------------------------------------------===//
 843 // ARM processors
 844 //
 845
 846 // Dummy CPU, used to target architectures
 847 def : ProcessorModel<"generic",     CortexA8Model,      []>;
 848
 849 // FIXME: Several processors below are not using their own scheduler
 850 // model, but one of similar/previous processor. These should be fixed.
 851
 852 def : ProcNoItin<"arm8",                                [ARMv4]>;
 853 def : ProcNoItin<"arm810",                              [ARMv4]>;
 854 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 855 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 856 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 857 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 858
 859 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 860 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 861 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 862 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 863 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 864 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 865 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 866 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 867 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 868 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 869 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 870
 871 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 872 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 873
 874 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 875 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 876 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 877 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 878 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 879 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 880 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 881 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 882 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 883 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 884
 885 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 886 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 887                                                          FeatureVFP2,
 888                                                          FeatureHasSlowFPVMLx]>;
 889
 890 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 891 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 892 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 893 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 894
 895 def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
 896 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 897 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 898                                                          FeatureVFP2,
 899                                                          FeatureHasSlowFPVMLx]>;
 900
 901 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 902 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 903                                                          FeatureVFP2,
 904                                                          FeatureHasSlowFPVMLx]>;
 905
 906 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 907 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 908                                                          FeatureVFP2,
 909                                                          FeatureHasSlowFPVMLx]>;
 910
 911 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 912                                                          FeatureHasRetAddrStack,
 913                                                          FeatureTrustZone,
 914                                                          FeatureSlowFPBrcc,
 915                                                          FeatureHasSlowFPVMLx,
 916                                                          FeatureVMLxForwarding,
 917                                                          FeatureMP,
 918                                                          FeatureVFP4]>;
 919
 920 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 921                                                          FeatureHasRetAddrStack,
 922                                                          FeatureTrustZone,
 923                                                          FeatureSlowFPBrcc,
 924                                                          FeatureHasVMLxHazards,
 925                                                          FeatureHasSlowFPVMLx,
 926                                                          FeatureVMLxForwarding,
 927                                                          FeatureMP,
 928                                                          FeatureVFP4,
 929                                                          FeatureVirtualization]>;
 930
 931 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 932                                                          FeatureHasRetAddrStack,
 933                                                          FeatureNonpipelinedVFP,
 934                                                          FeatureTrustZone,
 935                                                          FeatureSlowFPBrcc,
 936                                                          FeatureHasVMLxHazards,
 937                                                          FeatureHasSlowFPVMLx,
 938                                                          FeatureVMLxForwarding]>;
 939
 940 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 941                                                          FeatureHasRetAddrStack,
 942                                                          FeatureTrustZone,
 943                                                          FeatureHasVMLxHazards,
 944                                                          FeatureVMLxForwarding,
 945                                                          FeatureFP16,
 946                                                          FeatureAvoidPartialCPSR,
 947                                                          FeatureExpandMLx,
 948                                                          FeaturePreferVMOVSR,
 949                                                          FeatureMuxedUnits,
 950                                                          FeatureNEONForFPMovs,
 951                                                          FeatureCheckVLDnAlign,
 952                                                          FeatureMP]>;
 953
 954 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 955                                                          FeatureHasRetAddrStack,
 956                                                          FeatureTrustZone,
 957                                                          FeatureVMLxForwarding,
 958                                                          FeatureVFP4,
 959                                                          FeatureAvoidPartialCPSR,
 960                                                          FeatureVirtualization,
 961                                                          FeatureMP]>;
 962
 963 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 964                                                          FeatureDontWidenVMOVS,
 965                                                          FeatureSplatVFPToNeon,
 966                                                          FeatureHasRetAddrStack,
 967                                                          FeatureMuxedUnits,
 968                                                          FeatureTrustZone,
 969                                                          FeatureVFP4,
 970                                                          FeatureMP,
 971                                                          FeatureCheckVLDnAlign,
 972                                                          FeatureAvoidPartialCPSR,
 973                                                          FeatureVirtualization]>;
 974
 975 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 976                                                          FeatureHasRetAddrStack,
 977                                                          FeatureTrustZone,
 978                                                          FeatureMP,
 979                                                          FeatureVMLxForwarding,
 980                                                          FeatureVFP4,
 981                                                          FeatureAvoidPartialCPSR,
 982                                                          FeatureVirtualization]>;
 983
 984 // FIXME: krait has currently the same features as A9 plus VFP4 and  HWDiv
 985 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 986                                                          FeatureHasRetAddrStack,
 987                                                          FeatureMuxedUnits,
 988                                                          FeatureCheckVLDnAlign,
 989                                                          FeatureVMLxForwarding,
 990                                                          FeatureFP16,
 991                                                          FeatureAvoidPartialCPSR,
 992                                                          FeatureVFP4,
 993                                                          FeatureHWDivThumb,
 994                                                          FeatureHWDivARM]>;
 995
 996 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
 997                                                          FeatureHasRetAddrStack,
 998                                                          FeatureNEONForFP,
 999                                                          FeatureVFP4,
1000                                                          FeatureUseWideStrideVFP,
1001                                                          FeatureMP,
1002                                                          FeatureHWDivThumb,
1003                                                          FeatureHWDivARM,
1004                                                          FeatureAvoidPartialCPSR,
1005                                                          FeatureAvoidMOVsShOp,
1006                                                          FeatureHasSlowFPVMLx,
1007                                                          FeatureHasVMLxHazards,
1008                                                          FeatureProfUnpredicate,
1009                                                          FeaturePrefISHSTBarrier,
1010                                                          FeatureSlowOddRegister,
1011                                                          FeatureSlowLoadDSubreg,
1012                                                          FeatureSlowVGETLNi32,
1013                                                          FeatureSlowVDUP32,
1014                                                          FeatureUseMISched,
1015                                                          FeatureNoPostRASched]>;
1016
1017 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
1018                                                          FeatureHasRetAddrStack,
1019                                                          FeatureAvoidPartialCPSR]>;
1020
1021 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
1022                                                          FeatureHasRetAddrStack,
1023                                                          FeatureSlowFPBrcc,
1024                                                          FeatureHasSlowFPVMLx,
1025                                                          FeatureVFP3_D16,
1026                                                          FeatureAvoidPartialCPSR]>;
1027
1028 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
1029                                                          FeatureHasRetAddrStack,
1030                                                          FeatureVFP3_D16,
1031                                                          FeatureSlowFPBrcc,
1032                                                          FeatureHWDivARM,
1033                                                          FeatureHasSlowFPVMLx,
1034                                                          FeatureAvoidPartialCPSR]>;
1035
1036 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
1037                                                          FeatureHasRetAddrStack,
1038                                                          FeatureVFP3_D16,
1039                                                          FeatureFP16,
1040                                                          FeatureMP,
1041                                                          FeatureSlowFPBrcc,
1042                                                          FeatureHWDivARM,
1043                                                          FeatureHasSlowFPVMLx,
1044                                                          FeatureAvoidPartialCPSR]>;
1045
1046 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
1047                                                          FeatureHasRetAddrStack,
1048                                                          FeatureVFP3_D16,
1049                                                          FeatureFP16,
1050                                                          FeatureMP,
1051                                                          FeatureSlowFPBrcc,
1052                                                          FeatureHWDivARM,
1053                                                          FeatureHasSlowFPVMLx,
1054                                                          FeatureAvoidPartialCPSR]>;
1055
1056 def : ProcessorModel<"cortex-m3",   CortexM4Model,      [ARMv7m,
1057                                                          ProcM3,
1058                                                          FeaturePrefLoopAlign32,
1059                                                          FeatureUseMISched,
1060                                                          FeatureUseAA,
1061                                                          FeatureHasNoBranchPredictor]>;
1062
1063 def : ProcessorModel<"sc300",       CortexM4Model,      [ARMv7m,
1064                                                          ProcM3,
1065                                                          FeatureUseMISched,
1066                                                          FeatureUseAA,
1067                                                          FeatureHasNoBranchPredictor]>;
1068
1069 def : ProcessorModel<"cortex-m4", CortexM4Model,        [ARMv7em,
1070                                                          FeatureVFP4_D16_SP,
1071                                                          FeaturePrefLoopAlign32,
1072                                                          FeatureHasSlowFPVMLx,
1073                                                          FeatureUseMISched,
1074                                                          FeatureUseAA,
1075                                                          FeatureHasNoBranchPredictor]>;
1076
1077 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
1078                                                          FeatureFPARMv8_D16]>;
1079
1080 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
1081                                                          FeatureNoMovt]>;
1082
1083 def : ProcessorModel<"cortex-m33", CortexM4Model,       [ARMv8mMainline,
1084                                                          FeatureDSP,
1085                                                          FeatureFPARMv8_D16_SP,
1086                                                          FeaturePrefLoopAlign32,
1087                                                          FeatureHasSlowFPVMLx,
1088                                                          FeatureUseMISched,
1089                                                          FeatureUseAA,
1090                                                          FeatureHasNoBranchPredictor]>;
1091
1092 def : ProcessorModel<"cortex-m35p", CortexM4Model,      [ARMv8mMainline,
1093                                                          FeatureDSP,
1094                                                          FeatureFPARMv8_D16_SP,
1095                                                          FeaturePrefLoopAlign32,
1096                                                          FeatureHasSlowFPVMLx,
1097                                                          FeatureUseMISched,
1098                                                          FeatureUseAA,
1099                                                          FeatureHasNoBranchPredictor]>;
1100
1101
1102 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
1103                                                          FeatureHWDivThumb,
1104                                                          FeatureHWDivARM,
1105                                                          FeatureCrypto,
1106                                                          FeatureCRC]>;
1107
1108 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
1109                                                          FeatureHWDivThumb,
1110                                                          FeatureHWDivARM,
1111                                                          FeatureCrypto,
1112                                                          FeatureCRC]>;
1113
1114 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
1115                                                          FeatureHWDivThumb,
1116                                                          FeatureHWDivARM,
1117                                                          FeatureCrypto,
1118                                                          FeatureCRC,
1119                                                          FeatureFPAO]>;
1120
1121 def : ProcNoItin<"cortex-a55",                          [ARMv82a, ProcA55,
1122                                                          FeatureHWDivThumb,
1123                                                          FeatureHWDivARM,
1124                                                          FeatureDotProd]>;
1125
1126 def : ProcessorModel<"cortex-a57",  CortexA57Model,     [ARMv8a, ProcA57,
1127                                                          FeatureHWDivThumb,
1128                                                          FeatureHWDivARM,
1129                                                          FeatureCrypto,
1130                                                          FeatureCRC,
1131                                                          FeatureFPAO,
1132                                                          FeatureAvoidPartialCPSR,
1133                                                          FeatureCheapPredicableCPSR]>;
1134
1135 def : ProcessorModel<"cortex-a72",  CortexA57Model,     [ARMv8a, ProcA72,
1136                                                          FeatureHWDivThumb,
1137                                                          FeatureHWDivARM,
1138                                                          FeatureCrypto,
1139                                                          FeatureCRC]>;
1140
1141 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
1142                                                          FeatureHWDivThumb,
1143                                                          FeatureHWDivARM,
1144                                                          FeatureCrypto,
1145                                                          FeatureCRC]>;
1146
1147 def : ProcNoItin<"cortex-a75",                          [ARMv82a, ProcA75,
1148                                                          FeatureHWDivThumb,
1149                                                          FeatureHWDivARM,
1150                                                          FeatureDotProd]>;
1151
1152 def : ProcNoItin<"cortex-a76",                          [ARMv82a, ProcA76,
1153                                                          FeatureHWDivThumb,
1154                                                          FeatureHWDivARM,
1155                                                          FeatureCrypto,
1156                                                          FeatureCRC,
1157                                                          FeatureFullFP16,
1158                                                          FeatureDotProd]>;
1159
1160 def : ProcNoItin<"cortex-a76ae",                        [ARMv82a, ProcA76,
1161                                                          FeatureHWDivThumb,
1162                                                          FeatureHWDivARM,
1163                                                          FeatureCrypto,
1164                                                          FeatureCRC,
1165                                                          FeatureFullFP16,
1166                                                          FeatureDotProd]>;
1167
1168 def : ProcNoItin<"neoverse-n1",                         [ARMv82a,
1169                                                          FeatureHWDivThumb,
1170                                                          FeatureHWDivARM,
1171                                                          FeatureCrypto,
1172                                                          FeatureCRC,
1173                                                          FeatureDotProd]>;
1174
1175 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
1176                                                          FeatureHasRetAddrStack,
1177                                                          FeatureNEONForFP,
1178                                                          FeatureVFP4,
1179                                                          FeatureMP,
1180                                                          FeatureHWDivThumb,
1181                                                          FeatureHWDivARM,
1182                                                          FeatureAvoidPartialCPSR,
1183                                                          FeatureAvoidMOVsShOp,
1184                                                          FeatureHasSlowFPVMLx,
1185                                                          FeatureCrypto,
1186                                                          FeatureUseMISched,
1187                                                          FeatureZCZeroing,
1188                                                          FeatureNoPostRASched]>;
1189
1190 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynos]>;
1191 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynos]>;
1192 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynos]>;
1193 def : ProcNoItin<"exynos-m4",                           [ARMv82a, ProcExynos,
1194                                                          FeatureFullFP16,
1195                                                          FeatureDotProd]>;
1196 def : ProcNoItin<"exynos-m5",                           [ARMv82a, ProcExynos,
1197                                                          FeatureFullFP16,
1198                                                          FeatureDotProd]>;
1199
1200 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
1201                                                          FeatureHWDivThumb,
1202                                                          FeatureHWDivARM,
1203                                                          FeatureCrypto,
1204                                                          FeatureCRC]>;
1205
1206 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
1207                                                          FeatureUseMISched,
1208                                                          FeatureFPAO,
1209                                                          FeatureUseAA]>;
1210
1211 //===----------------------------------------------------------------------===//
1212 // Register File Description
1213 //===----------------------------------------------------------------------===//
1214
1215 include "ARMRegisterInfo.td"
1216 include "ARMRegisterBanks.td"
1217 include "ARMCallingConv.td"
1218
1219 //===----------------------------------------------------------------------===//
1220 // Instruction Descriptions
1221 //===----------------------------------------------------------------------===//
1222
1223 include "ARMInstrInfo.td"
1224 def ARMInstrInfo : InstrInfo;
1225
1226 //===----------------------------------------------------------------------===//
1227 // Declare the target which we are implementing
1228 //===----------------------------------------------------------------------===//
1229
1230 def ARMAsmWriter : AsmWriter {
1231   string AsmWriterClassName  = "InstPrinter";
1232   int PassSubtarget = 1;
1233   int Variant = 0;
1234   bit isMCAsmWriter = 1;
1235 }
1236
1237 def ARMAsmParser : AsmParser {
1238   bit ReportMultipleNearMisses = 1;
1239 }
1240
1241 def ARMAsmParserVariant : AsmParserVariant {
1242   int Variant = 0;
1243   string Name = "ARM";
1244   string BreakCharacters = ".";
1245 }
1246
1247 def ARM : Target {
1248   // Pull in Instruction Info.
1249   let InstructionSet = ARMInstrInfo;
1250   let AssemblyWriters = [ARMAsmWriter];
1251   let AssemblyParsers = [ARMAsmParser];
1252   let AssemblyParserVariants = [ARMAsmParserVariant];
1253   let AllowRegisterRenaming = 1;
1254 }