lib/Target/ARM/ARMISelLowering.h

   1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the interfaces that ARM uses to lower LLVM code into a
  10 // selection DAG.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
  15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
  16
  17 #include "MCTargetDesc/ARMBaseInfo.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/ADT/StringRef.h"
  20 #include "llvm/CodeGen/CallingConvLower.h"
  21 #include "llvm/CodeGen/ISDOpcodes.h"
  22 #include "llvm/CodeGen/MachineFunction.h"
  23 #include "llvm/CodeGen/SelectionDAGNodes.h"
  24 #include "llvm/CodeGen/TargetLowering.h"
  25 #include "llvm/CodeGen/ValueTypes.h"
  26 #include "llvm/IR/Attributes.h"
  27 #include "llvm/IR/CallingConv.h"
  28 #include "llvm/IR/Function.h"
  29 #include "llvm/IR/IRBuilder.h"
  30 #include "llvm/IR/InlineAsm.h"
  31 #include "llvm/Support/CodeGen.h"
  32 #include "llvm/Support/MachineValueType.h"
  33 #include <utility>
  34
  35 namespace llvm {
  36
  37 class ARMSubtarget;
  38 class DataLayout;
  39 class FastISel;
  40 class FunctionLoweringInfo;
  41 class GlobalValue;
  42 class InstrItineraryData;
  43 class Instruction;
  44 class MachineBasicBlock;
  45 class MachineInstr;
  46 class SelectionDAG;
  47 class TargetLibraryInfo;
  48 class TargetMachine;
  49 class TargetRegisterInfo;
  50 class VectorType;
  51
  52   namespace ARMISD {
  53
  54     // ARM Specific DAG Nodes
  55     enum NodeType : unsigned {
  56       // Start the numbering where the builtin ops and target ops leave off.
  57       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  58
  59       Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
  60                     // TargetExternalSymbol, and TargetGlobalAddress.
  61       WrapperPIC,   // WrapperPIC - A wrapper node for TargetGlobalAddress in
  62                     // PIC mode.
  63       WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
  64
  65       // Add pseudo op to model memcpy for struct byval.
  66       COPY_STRUCT_BYVAL,
  67
  68       CALL,         // Function call.
  69       CALL_PRED,    // Function call that's predicable.
  70       CALL_NOLINK,  // Function call with branch not branch-and-link.
  71       BRCOND,       // Conditional branch.
  72       BR_JT,        // Jumptable branch.
  73       BR2_JT,       // Jumptable branch (2 level - jumptable entry is a jump).
  74       RET_FLAG,     // Return with a flag operand.
  75       INTRET_FLAG,  // Interrupt return with an LR-offset and a flag operand.
  76
  77       PIC_ADD,      // Add with a PC operand and a PIC label.
  78
  79       ASRL,         // MVE long arithmetic shift right.
  80       LSRL,         // MVE long shift right.
  81       LSLL,         // MVE long shift left.
  82
  83       CMP,          // ARM compare instructions.
  84       CMN,          // ARM CMN instructions.
  85       CMPZ,         // ARM compare that sets only Z flag.
  86       CMPFP,        // ARM VFP compare instruction, sets FPSCR.
  87       CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
  88       FMSTAT,       // ARM fmstat instruction.
  89
  90       CMOV,         // ARM conditional move instructions.
  91       SUBS,         // Flag-setting subtraction.
  92
  93       SSAT,         // Signed saturation
  94       USAT,         // Unsigned saturation
  95
  96       BCC_i64,
  97
  98       SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
  99       SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
 100       RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
 101
 102       ADDC,         // Add with carry
 103       ADDE,         // Add using carry
 104       SUBC,         // Sub with carry
 105       SUBE,         // Sub using carry
 106       LSLS,         // Shift left producing carry
 107
 108       VMOVRRD,      // double to two gprs.
 109       VMOVDRR,      // Two gprs to double.
 110       VMOVSR,       // move gpr to single, used for f32 literal constructed in a gpr
 111
 112       EH_SJLJ_SETJMP,         // SjLj exception handling setjmp.
 113       EH_SJLJ_LONGJMP,        // SjLj exception handling longjmp.
 114       EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
 115
 116       TC_RETURN,    // Tail call return pseudo.
 117
 118       THREAD_POINTER,
 119
 120       DYN_ALLOC,    // Dynamic allocation on the stack.
 121
 122       MEMBARRIER_MCR, // Memory barrier (MCR)
 123
 124       PRELOAD,      // Preload
 125
 126       WIN__CHKSTK,  // Windows' __chkstk call to do stack probing.
 127       WIN__DBZCHK,  // Windows' divide by zero check
 128
 129       WLS,          // Low-overhead loops, While Loop Start
 130       LOOP_DEC,     // Really a part of LE, performs the sub
 131       LE,           // Low-overhead loops, Loop End
 132
 133       PREDICATE_CAST, // Predicate cast for MVE i1 types
 134
 135       VCMP,         // Vector compare.
 136       VCMPZ,        // Vector compare to zero.
 137       VTST,         // Vector test bits.
 138
 139       // Vector shift by vector
 140       VSHLs,        // ...left/right by signed
 141       VSHLu,        // ...left/right by unsigned
 142
 143       // Vector shift by immediate:
 144       VSHLIMM,      // ...left
 145       VSHRsIMM,     // ...right (signed)
 146       VSHRuIMM,     // ...right (unsigned)
 147
 148       // Vector rounding shift by immediate:
 149       VRSHRsIMM,    // ...right (signed)
 150       VRSHRuIMM,    // ...right (unsigned)
 151       VRSHRNIMM,    // ...right narrow
 152
 153       // Vector saturating shift by immediate:
 154       VQSHLsIMM,    // ...left (signed)
 155       VQSHLuIMM,    // ...left (unsigned)
 156       VQSHLsuIMM,   // ...left (signed to unsigned)
 157       VQSHRNsIMM,   // ...right narrow (signed)
 158       VQSHRNuIMM,   // ...right narrow (unsigned)
 159       VQSHRNsuIMM,  // ...right narrow (signed to unsigned)
 160
 161       // Vector saturating rounding shift by immediate:
 162       VQRSHRNsIMM,  // ...right narrow (signed)
 163       VQRSHRNuIMM,  // ...right narrow (unsigned)
 164       VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
 165
 166       // Vector shift and insert:
 167       VSLIIMM,      // ...left
 168       VSRIIMM,      // ...right
 169
 170       // Vector get lane (VMOV scalar to ARM core register)
 171       // (These are used for 8- and 16-bit element types only.)
 172       VGETLANEu,    // zero-extend vector extract element
 173       VGETLANEs,    // sign-extend vector extract element
 174
 175       // Vector move immediate and move negated immediate:
 176       VMOVIMM,
 177       VMVNIMM,
 178
 179       // Vector move f32 immediate:
 180       VMOVFPIMM,
 181
 182       // Move H <-> R, clearing top 16 bits
 183       VMOVrh,
 184       VMOVhr,
 185
 186       // Vector duplicate:
 187       VDUP,
 188       VDUPLANE,
 189
 190       // Vector shuffles:
 191       VEXT,         // extract
 192       VREV64,       // reverse elements within 64-bit doublewords
 193       VREV32,       // reverse elements within 32-bit words
 194       VREV16,       // reverse elements within 16-bit halfwords
 195       VZIP,         // zip (interleave)
 196       VUZP,         // unzip (deinterleave)
 197       VTRN,         // transpose
 198       VTBL1,        // 1-register shuffle with mask
 199       VTBL2,        // 2-register shuffle with mask
 200
 201       // Vector multiply long:
 202       VMULLs,       // ...signed
 203       VMULLu,       // ...unsigned
 204
 205       SMULWB,       // Signed multiply word by half word, bottom
 206       SMULWT,       // Signed multiply word by half word, top
 207       UMLAL,        // 64bit Unsigned Accumulate Multiply
 208       SMLAL,        // 64bit Signed Accumulate Multiply
 209       UMAAL,        // 64-bit Unsigned Accumulate Accumulate Multiply
 210       SMLALBB,      // 64-bit signed accumulate multiply bottom, bottom 16
 211       SMLALBT,      // 64-bit signed accumulate multiply bottom, top 16
 212       SMLALTB,      // 64-bit signed accumulate multiply top, bottom 16
 213       SMLALTT,      // 64-bit signed accumulate multiply top, top 16
 214       SMLALD,       // Signed multiply accumulate long dual
 215       SMLALDX,      // Signed multiply accumulate long dual exchange
 216       SMLSLD,       // Signed multiply subtract long dual
 217       SMLSLDX,      // Signed multiply subtract long dual exchange
 218       SMMLAR,       // Signed multiply long, round and add
 219       SMMLSR,       // Signed multiply long, subtract and round
 220
 221       // Operands of the standard BUILD_VECTOR node are not legalized, which
 222       // is fine if BUILD_VECTORs are always lowered to shuffles or other
 223       // operations, but for ARM some BUILD_VECTORs are legal as-is and their
 224       // operands need to be legalized.  Define an ARM-specific version of
 225       // BUILD_VECTOR for this purpose.
 226       BUILD_VECTOR,
 227
 228       // Bit-field insert
 229       BFI,
 230
 231       // Vector OR with immediate
 232       VORRIMM,
 233       // Vector AND with NOT of immediate
 234       VBICIMM,
 235
 236       // Vector bitwise select
 237       VBSL,
 238
 239       // Pseudo-instruction representing a memory copy using ldm/stm
 240       // instructions.
 241       MEMCPY,
 242
 243       // Vector load N-element structure to all lanes:
 244       VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
 245       VLD2DUP,
 246       VLD3DUP,
 247       VLD4DUP,
 248
 249       // NEON loads with post-increment base updates:
 250       VLD1_UPD,
 251       VLD2_UPD,
 252       VLD3_UPD,
 253       VLD4_UPD,
 254       VLD2LN_UPD,
 255       VLD3LN_UPD,
 256       VLD4LN_UPD,
 257       VLD1DUP_UPD,
 258       VLD2DUP_UPD,
 259       VLD3DUP_UPD,
 260       VLD4DUP_UPD,
 261
 262       // NEON stores with post-increment base updates:
 263       VST1_UPD,
 264       VST2_UPD,
 265       VST3_UPD,
 266       VST4_UPD,
 267       VST2LN_UPD,
 268       VST3LN_UPD,
 269       VST4LN_UPD
 270     };
 271
 272   } // end namespace ARMISD
 273
 274   /// Define some predicates that are used for node matching.
 275   namespace ARM {
 276
 277     bool isBitFieldInvertedMask(unsigned v);
 278
 279   } // end namespace ARM
 280
 281   //===--------------------------------------------------------------------===//
 282   //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
 283
 284   class ARMTargetLowering : public TargetLowering {
 285   public:
 286     explicit ARMTargetLowering(const TargetMachine &TM,
 287                                const ARMSubtarget &STI);
 288
 289     unsigned getJumpTableEncoding() const override;
 290     bool useSoftFloat() const override;
 291
 292     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 293
 294     /// ReplaceNodeResults - Replace the results of node with an illegal result
 295     /// type with new values built out of custom code.
 296     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 297                             SelectionDAG &DAG) const override;
 298
 299     const char *getTargetNodeName(unsigned Opcode) const override;
 300
 301     bool isSelectSupported(SelectSupportKind Kind) const override {
 302       // ARM does not support scalar condition selects on vectors.
 303       return (Kind != ScalarCondVectorVal);
 304     }
 305
 306     bool isReadOnly(const GlobalValue *GV) const;
 307
 308     /// getSetCCResultType - Return the value type to use for ISD::SETCC.
 309     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 310                            EVT VT) const override;
 311
 312     MachineBasicBlock *
 313     EmitInstrWithCustomInserter(MachineInstr &MI,
 314                                 MachineBasicBlock *MBB) const override;
 315
 316     void AdjustInstrPostInstrSelection(MachineInstr &MI,
 317                                        SDNode *Node) const override;
 318
 319     SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
 320     SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
 321     SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
 322     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 323
 324     bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
 325
 326     /// allowsMisalignedMemoryAccesses - Returns true if the target allows
 327     /// unaligned memory accesses of the specified type. Returns whether it
 328     /// is "fast" by reference in the second argument.
 329     bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
 330                                         unsigned Align,
 331                                         MachineMemOperand::Flags Flags,
 332                                         bool *Fast) const override;
 333
 334     EVT getOptimalMemOpType(uint64_t Size,
 335                             unsigned DstAlign, unsigned SrcAlign,
 336                             bool IsMemset, bool ZeroMemset,
 337                             bool MemcpyStrSrc,
 338                             const AttributeList &FuncAttributes) const override;
 339
 340     bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
 341     bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
 342     bool isZExtFree(SDValue Val, EVT VT2) const override;
 343     bool shouldSinkOperands(Instruction *I,
 344                             SmallVectorImpl<Use *> &Ops) const override;
 345
 346     bool isFNegFree(EVT VT) const override;
 347
 348     bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
 349
 350     bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
 351
 352
 353     /// isLegalAddressingMode - Return true if the addressing mode represented
 354     /// by AM is legal for this target, for a load/store of the specified type.
 355     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
 356                                Type *Ty, unsigned AS,
 357                                Instruction *I = nullptr) const override;
 358
 359     /// getScalingFactorCost - Return the cost of the scaling used in
 360     /// addressing mode represented by AM.
 361     /// If the AM is supported, the return value must be >= 0.
 362     /// If the AM is not supported, the return value must be negative.
 363     int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
 364                              unsigned AS) const override;
 365
 366     bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
 367
 368     /// Returns true if the addresing mode representing by AM is legal
 369     /// for the Thumb1 target, for a load/store of the specified type.
 370     bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
 371
 372     /// isLegalICmpImmediate - Return true if the specified immediate is legal
 373     /// icmp immediate, that is the target has icmp instructions which can
 374     /// compare a register against the immediate without having to materialize
 375     /// the immediate into a register.
 376     bool isLegalICmpImmediate(int64_t Imm) const override;
 377
 378     /// isLegalAddImmediate - Return true if the specified immediate is legal
 379     /// add immediate, that is the target has add instructions which can
 380     /// add a register and the immediate without having to materialize
 381     /// the immediate into a register.
 382     bool isLegalAddImmediate(int64_t Imm) const override;
 383
 384     /// getPreIndexedAddressParts - returns true by value, base pointer and
 385     /// offset pointer and addressing mode by reference if the node's address
 386     /// can be legally represented as pre-indexed load / store address.
 387     bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
 388                                    ISD::MemIndexedMode &AM,
 389                                    SelectionDAG &DAG) const override;
 390
 391     /// getPostIndexedAddressParts - returns true by value, base pointer and
 392     /// offset pointer and addressing mode by reference if this node can be
 393     /// combined with a load / store to form a post-indexed load / store.
 394     bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
 395                                     SDValue &Offset, ISD::MemIndexedMode &AM,
 396                                     SelectionDAG &DAG) const override;
 397
 398     void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
 399                                        const APInt &DemandedElts,
 400                                        const SelectionDAG &DAG,
 401                                        unsigned Depth) const override;
 402
 403     bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
 404                                       TargetLoweringOpt &TLO) const override;
 405
 406
 407     bool ExpandInlineAsm(CallInst *CI) const override;
 408
 409     ConstraintType getConstraintType(StringRef Constraint) const override;
 410
 411     /// Examine constraint string and operand type and determine a weight value.
 412     /// The operand object must already have been set up with the operand type.
 413     ConstraintWeight getSingleConstraintMatchWeight(
 414       AsmOperandInfo &info, const char *constraint) const override;
 415
 416     std::pair<unsigned, const TargetRegisterClass *>
 417     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 418                                  StringRef Constraint, MVT VT) const override;
 419
 420     const char *LowerXConstraint(EVT ConstraintVT) const override;
 421
 422     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 423     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
 424     /// true it means one of the asm constraint of the inline asm instruction
 425     /// being processed is 'm'.
 426     void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
 427                                       std::vector<SDValue> &Ops,
 428                                       SelectionDAG &DAG) const override;
 429
 430     unsigned
 431     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
 432       if (ConstraintCode == "Q")
 433         return InlineAsm::Constraint_Q;
 434       else if (ConstraintCode == "o")
 435         return InlineAsm::Constraint_o;
 436       else if (ConstraintCode.size() == 2) {
 437         if (ConstraintCode[0] == 'U') {
 438           switch(ConstraintCode[1]) {
 439           default:
 440             break;
 441           case 'm':
 442             return InlineAsm::Constraint_Um;
 443           case 'n':
 444             return InlineAsm::Constraint_Un;
 445           case 'q':
 446             return InlineAsm::Constraint_Uq;
 447           case 's':
 448             return InlineAsm::Constraint_Us;
 449           case 't':
 450             return InlineAsm::Constraint_Ut;
 451           case 'v':
 452             return InlineAsm::Constraint_Uv;
 453           case 'y':
 454             return InlineAsm::Constraint_Uy;
 455           }
 456         }
 457       }
 458       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
 459     }
 460
 461     const ARMSubtarget* getSubtarget() const {
 462       return Subtarget;
 463     }
 464
 465     /// getRegClassFor - Return the register class that should be used for the
 466     /// specified value type.
 467     const TargetRegisterClass *
 468     getRegClassFor(MVT VT, bool isDivergent = false) const override;
 469
 470     /// Returns true if a cast between SrcAS and DestAS is a noop.
 471     bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
 472       // Addrspacecasts are always noops.
 473       return true;
 474     }
 475
 476     bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
 477                                 unsigned &PrefAlign) const override;
 478
 479     /// createFastISel - This method returns a target specific FastISel object,
 480     /// or null if the target does not support "fast" ISel.
 481     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
 482                              const TargetLibraryInfo *libInfo) const override;
 483
 484     Sched::Preference getSchedulingPreference(SDNode *N) const override;
 485
 486     bool
 487     isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
 488     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 489
 490     /// isFPImmLegal - Returns true if the target can instruction select the
 491     /// specified FP immediate natively. If false, the legalizer will
 492     /// materialize the FP immediate as a load from a constant pool.
 493     bool isFPImmLegal(const APFloat &Imm, EVT VT,
 494                       bool ForCodeSize = false) const override;
 495
 496     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
 497                             const CallInst &I,
 498                             MachineFunction &MF,
 499                             unsigned Intrinsic) const override;
 500
 501     /// Returns true if it is beneficial to convert a load of a constant
 502     /// to just the constant itself.
 503     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 504                                            Type *Ty) const override;
 505
 506     /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
 507     /// with this index.
 508     bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
 509                                  unsigned Index) const override;
 510
 511     /// Returns true if an argument of type Ty needs to be passed in a
 512     /// contiguous block of registers in calling convention CallConv.
 513     bool functionArgumentNeedsConsecutiveRegisters(
 514         Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
 515
 516     /// If a physical register, this returns the register that receives the
 517     /// exception address on entry to an EH pad.
 518     unsigned
 519     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
 520
 521     /// If a physical register, this returns the register that receives the
 522     /// exception typeid on entry to a landing pad.
 523     unsigned
 524     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
 525
 526     Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
 527     Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
 528                           AtomicOrdering Ord) const override;
 529     Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
 530                                 Value *Addr, AtomicOrdering Ord) const override;
 531
 532     void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
 533
 534     Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
 535                                   AtomicOrdering Ord) const override;
 536     Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
 537                                    AtomicOrdering Ord) const override;
 538
 539     unsigned getMaxSupportedInterleaveFactor() const override;
 540
 541     bool lowerInterleavedLoad(LoadInst *LI,
 542                               ArrayRef<ShuffleVectorInst *> Shuffles,
 543                               ArrayRef<unsigned> Indices,
 544                               unsigned Factor) const override;
 545     bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
 546                                unsigned Factor) const override;
 547
 548     bool shouldInsertFencesForAtomic(const Instruction *I) const override;
 549     TargetLoweringBase::AtomicExpansionKind
 550     shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
 551     bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
 552     TargetLoweringBase::AtomicExpansionKind
 553     shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
 554     TargetLoweringBase::AtomicExpansionKind
 555     shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
 556
 557     bool useLoadStackGuardNode() const override;
 558
 559     void insertSSPDeclarations(Module &M) const override;
 560     Value *getSDagStackGuard(const Module &M) const override;
 561     Function *getSSPStackGuardCheck(const Module &M) const override;
 562
 563     bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
 564                                    unsigned &Cost) const override;
 565
 566     bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
 567                           const SelectionDAG &DAG) const override {
 568       // Do not merge to larger than i32.
 569       return (MemVT.getSizeInBits() <= 32);
 570     }
 571
 572     bool isCheapToSpeculateCttz() const override;
 573     bool isCheapToSpeculateCtlz() const override;
 574
 575     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
 576       return VT.isScalarInteger();
 577     }
 578
 579     bool supportSwiftError() const override {
 580       return true;
 581     }
 582
 583     bool hasStandaloneRem(EVT VT) const override {
 584       return HasStandaloneRem;
 585     }
 586
 587     bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
 588
 589     CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
 590     CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
 591
 592     /// Returns true if \p VecTy is a legal interleaved access type. This
 593     /// function checks the vector element type and the overall width of the
 594     /// vector.
 595     bool isLegalInterleavedAccessType(VectorType *VecTy,
 596                                       const DataLayout &DL) const;
 597
 598     bool alignLoopsWithOptSize() const override;
 599
 600     /// Returns the number of interleaved accesses that will be generated when
 601     /// lowering accesses of the given type.
 602     unsigned getNumInterleavedAccesses(VectorType *VecTy,
 603                                        const DataLayout &DL) const;
 604
 605     void finalizeLowering(MachineFunction &MF) const override;
 606
 607     /// Return the correct alignment for the current calling convention.
 608     unsigned getABIAlignmentForCallingConv(Type *ArgTy,
 609                                            DataLayout DL) const override;
 610
 611     bool isDesirableToCommuteWithShift(const SDNode *N,
 612                                        CombineLevel Level) const override;
 613
 614     bool shouldFoldConstantShiftPairToMask(const SDNode *N,
 615                                            CombineLevel Level) const override;
 616
 617     bool preferIncOfAddToSubOfNot(EVT VT) const override;
 618
 619   protected:
 620     std::pair<const TargetRegisterClass *, uint8_t>
 621     findRepresentativeClass(const TargetRegisterInfo *TRI,
 622                             MVT VT) const override;
 623
 624   private:
 625     /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
 626     /// make the right decision when generating code for different targets.
 627     const ARMSubtarget *Subtarget;
 628
 629     const TargetRegisterInfo *RegInfo;
 630
 631     const InstrItineraryData *Itins;
 632
 633     /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
 634     unsigned ARMPCLabelIndex;
 635
 636     // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
 637     // check.
 638     bool InsertFencesForAtomic;
 639
 640     bool HasStandaloneRem = true;
 641
 642     void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
 643     void addDRTypeForNEON(MVT VT);
 644     void addQRTypeForNEON(MVT VT);
 645     std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
 646
 647     using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
 648
 649     void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
 650                           SDValue &Arg, RegsToPassVector &RegsToPass,
 651                           CCValAssign &VA, CCValAssign &NextVA,
 652                           SDValue &StackPtr,
 653                           SmallVectorImpl<SDValue> &MemOpChains,
 654                           ISD::ArgFlagsTy Flags) const;
 655     SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
 656                                  SDValue &Root, SelectionDAG &DAG,
 657                                  const SDLoc &dl) const;
 658
 659     CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
 660                                             bool isVarArg) const;
 661     CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
 662                                   bool isVarArg) const;
 663     SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
 664                              const SDLoc &dl, SelectionDAG &DAG,
 665                              const CCValAssign &VA,
 666                              ISD::ArgFlagsTy Flags) const;
 667     SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
 668     SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
 669     SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
 670     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
 671                                     const ARMSubtarget *Subtarget) const;
 672     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
 673                                     const ARMSubtarget *Subtarget) const;
 674     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 675     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 676     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 677     SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
 678     SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
 679     SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
 680     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 681     SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
 682                                             SelectionDAG &DAG) const;
 683     SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
 684                                  SelectionDAG &DAG,
 685                                  TLSModel::Model model) const;
 686     SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
 687     SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
 688     SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
 689     SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
 690     SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
 691     SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
 692     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 693     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
 694     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 695     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
 696     SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
 697     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 698     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 699     SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
 700     SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
 701     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
 702     SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
 703                             const ARMSubtarget *ST) const;
 704     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
 705                               const ARMSubtarget *ST) const;
 706     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 707     SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
 708     SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
 709     SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
 710     void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
 711                            SmallVectorImpl<SDValue> &Results) const;
 712     SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
 713                                    SDValue &Chain) const;
 714     SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
 715     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 716     SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
 717     SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
 718     SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
 719     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 720     void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
 721                   SelectionDAG &DAG) const;
 722
 723     unsigned getRegisterByName(const char* RegName, EVT VT,
 724                                SelectionDAG &DAG) const override;
 725
 726     SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
 727                           SmallVectorImpl<SDNode *> &Created) const override;
 728
 729     /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
 730     /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
 731     /// expanded to FMAs when this method returns true, otherwise fmuladd is
 732     /// expanded to fmul + fadd.
 733     ///
 734     /// ARM supports both fused and unfused multiply-add operations; we already
 735     /// lower a pair of fmul and fadd to the latter so it's not clear that there
 736     /// would be a gain or that the gain would be worthwhile enough to risk
 737     /// correctness bugs.
 738     bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
 739
 740     SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
 741
 742     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 743                             CallingConv::ID CallConv, bool isVarArg,
 744                             const SmallVectorImpl<ISD::InputArg> &Ins,
 745                             const SDLoc &dl, SelectionDAG &DAG,
 746                             SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
 747                             SDValue ThisVal) const;
 748
 749     bool supportSplitCSR(MachineFunction *MF) const override {
 750       return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
 751           MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
 752     }
 753
 754     void initializeSplitCSR(MachineBasicBlock *Entry) const override;
 755     void insertCopiesSplitCSR(
 756       MachineBasicBlock *Entry,
 757       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
 758
 759     SDValue
 760     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 761                          const SmallVectorImpl<ISD::InputArg> &Ins,
 762                          const SDLoc &dl, SelectionDAG &DAG,
 763                          SmallVectorImpl<SDValue> &InVals) const override;
 764
 765     int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
 766                        SDValue &Chain, const Value *OrigArg,
 767                        unsigned InRegsParamRecordIdx, int ArgOffset,
 768                        unsigned ArgSize) const;
 769
 770     void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
 771                               const SDLoc &dl, SDValue &Chain,
 772                               unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
 773                               bool ForceMutable = false) const;
 774
 775     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
 776                       SmallVectorImpl<SDValue> &InVals) const override;
 777
 778     /// HandleByVal - Target-specific cleanup for ByVal support.
 779     void HandleByVal(CCState *, unsigned &, unsigned) const override;
 780
 781     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
 782     /// for tail call optimization. Targets which want to do tail call
 783     /// optimization should implement this function.
 784     bool IsEligibleForTailCallOptimization(
 785         SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
 786         bool isCalleeStructRet, bool isCallerStructRet,
 787         const SmallVectorImpl<ISD::OutputArg> &Outs,
 788         const SmallVectorImpl<SDValue> &OutVals,
 789         const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
 790         const bool isIndirect) const;
 791
 792     bool CanLowerReturn(CallingConv::ID CallConv,
 793                         MachineFunction &MF, bool isVarArg,
 794                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 795                         LLVMContext &Context) const override;
 796
 797     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 798                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 799                         const SmallVectorImpl<SDValue> &OutVals,
 800                         const SDLoc &dl, SelectionDAG &DAG) const override;
 801
 802     bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
 803
 804     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
 805
 806     bool shouldConsiderGEPOffsetSplit() const override { return true; }
 807
 808     bool isUnsupportedFloatingType(EVT VT) const;
 809
 810     SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
 811                     SDValue ARMcc, SDValue CCR, SDValue Cmp,
 812                     SelectionDAG &DAG) const;
 813     SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
 814                       SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
 815     SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
 816                       const SDLoc &dl, bool InvalidOnQNaN) const;
 817     SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
 818
 819     SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
 820
 821     void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
 822                                 MachineBasicBlock *DispatchBB, int FI) const;
 823
 824     void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
 825
 826     bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
 827
 828     MachineBasicBlock *EmitStructByval(MachineInstr &MI,
 829                                        MachineBasicBlock *MBB) const;
 830
 831     MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
 832                                            MachineBasicBlock *MBB) const;
 833     MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
 834                                            MachineBasicBlock *MBB) const;
 835     void addMVEVectorTypes(bool HasMVEFP);
 836     void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
 837     void setAllExpand(MVT VT);
 838   };
 839
 840   enum VMOVModImmType {
 841     VMOVModImm,
 842     VMVNModImm,
 843     MVEVMVNModImm,
 844     OtherModImm
 845   };
 846
 847   namespace ARM {
 848
 849     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
 850                              const TargetLibraryInfo *libInfo);
 851
 852   } // end namespace ARM
 853
 854 } // end namespace llvm
 855
 856 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H