lib/Target/Lanai/LanaiISelLowering.cpp

   1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the LanaiTargetLowering class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "LanaiISelLowering.h"
  14 #include "Lanai.h"
  15 #include "LanaiCondCode.h"
  16 #include "LanaiMachineFunctionInfo.h"
  17 #include "LanaiSubtarget.h"
  18 #include "LanaiTargetObjectFile.h"
  19 #include "MCTargetDesc/LanaiBaseInfo.h"
  20 #include "llvm/ADT/APInt.h"
  21 #include "llvm/ADT/ArrayRef.h"
  22 #include "llvm/ADT/SmallVector.h"
  23 #include "llvm/ADT/StringRef.h"
  24 #include "llvm/ADT/StringSwitch.h"
  25 #include "llvm/CodeGen/CallingConvLower.h"
  26 #include "llvm/CodeGen/MachineFrameInfo.h"
  27 #include "llvm/CodeGen/MachineFunction.h"
  28 #include "llvm/CodeGen/MachineMemOperand.h"
  29 #include "llvm/CodeGen/MachineRegisterInfo.h"
  30 #include "llvm/CodeGen/RuntimeLibcalls.h"
  31 #include "llvm/CodeGen/SelectionDAG.h"
  32 #include "llvm/CodeGen/SelectionDAGNodes.h"
  33 #include "llvm/CodeGen/TargetCallingConv.h"
  34 #include "llvm/CodeGen/ValueTypes.h"
  35 #include "llvm/IR/CallingConv.h"
  36 #include "llvm/IR/DerivedTypes.h"
  37 #include "llvm/IR/Function.h"
  38 #include "llvm/IR/GlobalValue.h"
  39 #include "llvm/Support/Casting.h"
  40 #include "llvm/Support/CodeGen.h"
  41 #include "llvm/Support/CommandLine.h"
  42 #include "llvm/Support/Debug.h"
  43 #include "llvm/Support/ErrorHandling.h"
  44 #include "llvm/Support/KnownBits.h"
  45 #include "llvm/Support/MachineValueType.h"
  46 #include "llvm/Support/MathExtras.h"
  47 #include "llvm/Support/raw_ostream.h"
  48 #include "llvm/Target/TargetMachine.h"
  49 #include <cassert>
  50 #include <cmath>
  51 #include <cstdint>
  52 #include <cstdlib>
  53 #include <utility>
  54
  55 #define DEBUG_TYPE "lanai-lower"
  56
  57 using namespace llvm;
  58
  59 // Limit on number of instructions the lowered multiplication may have before a
  60 // call to the library function should be generated instead. The threshold is
  61 // currently set to 14 as this was the smallest threshold that resulted in all
  62 // constant multiplications being lowered. A threshold of 5 covered all cases
  63 // except for one multiplication which required 14. mulsi3 requires 16
  64 // instructions (including the prologue and epilogue but excluding instructions
  65 // at call site). Until we can inline mulsi3, generating at most 14 instructions
  66 // will be faster than invoking mulsi3.
  67 static cl::opt<int> LanaiLowerConstantMulThreshold(
  68     "lanai-constant-mul-threshold", cl::Hidden,
  69     cl::desc("Maximum number of instruction to generate when lowering constant "
  70              "multiplication instead of calling library function [default=14]"),
  71     cl::init(14));
  72
  73 LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
  74                                          const LanaiSubtarget &STI)
  75     : TargetLowering(TM) {
  76   // Set up the register classes.
  77   addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
  78
  79   // Compute derived properties from the register classes
  80   TRI = STI.getRegisterInfo();
  81   computeRegisterProperties(TRI);
  82
  83   setStackPointerRegisterToSaveRestore(Lanai::SP);
  84
  85   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
  86   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
  87   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
  88   setOperationAction(ISD::SETCC, MVT::i32, Custom);
  89   setOperationAction(ISD::SELECT, MVT::i32, Expand);
  90   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
  91
  92   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
  93   setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
  94   setOperationAction(ISD::JumpTable, MVT::i32, Custom);
  95   setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
  96
  97   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
  98   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
  99   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
 100
 101   setOperationAction(ISD::VASTART, MVT::Other, Custom);
 102   setOperationAction(ISD::VAARG, MVT::Other, Expand);
 103   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
 104   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 105
 106   setOperationAction(ISD::SDIV, MVT::i32, Expand);
 107   setOperationAction(ISD::UDIV, MVT::i32, Expand);
 108   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
 109   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
 110   setOperationAction(ISD::SREM, MVT::i32, Expand);
 111   setOperationAction(ISD::UREM, MVT::i32, Expand);
 112
 113   setOperationAction(ISD::MUL, MVT::i32, Custom);
 114   setOperationAction(ISD::MULHU, MVT::i32, Expand);
 115   setOperationAction(ISD::MULHS, MVT::i32, Expand);
 116   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
 117   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
 118
 119   setOperationAction(ISD::ROTR, MVT::i32, Expand);
 120   setOperationAction(ISD::ROTL, MVT::i32, Expand);
 121   setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
 122   setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
 123   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
 124
 125   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
 126   setOperationAction(ISD::CTPOP, MVT::i32, Legal);
 127   setOperationAction(ISD::CTLZ, MVT::i32, Legal);
 128   setOperationAction(ISD::CTTZ, MVT::i32, Legal);
 129
 130   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 131   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
 132   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
 133
 134   // Extended load operations for i1 types must be promoted
 135   for (MVT VT : MVT::integer_valuetypes()) {
 136     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
 137     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
 138     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
 139   }
 140
 141   setTargetDAGCombine(ISD::ADD);
 142   setTargetDAGCombine(ISD::SUB);
 143   setTargetDAGCombine(ISD::AND);
 144   setTargetDAGCombine(ISD::OR);
 145   setTargetDAGCombine(ISD::XOR);
 146
 147   // Function alignments (log2)
 148   setMinFunctionAlignment(2);
 149   setPrefFunctionAlignment(2);
 150
 151   setJumpIsExpensive(true);
 152
 153   // TODO: Setting the minimum jump table entries needed before a
 154   // switch is transformed to a jump table to 100 to avoid creating jump tables
 155   // as this was causing bad performance compared to a large group of if
 156   // statements. Re-evaluate this on new benchmarks.
 157   setMinimumJumpTableEntries(100);
 158
 159   // Use fast calling convention for library functions.
 160   for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
 161     setLibcallCallingConv(static_cast<RTLIB::Libcall>(I), CallingConv::Fast);
 162   }
 163
 164   MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
 165   MaxStoresPerMemsetOptSize = 8;
 166   MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
 167   MaxStoresPerMemcpyOptSize = 8;
 168   MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
 169   MaxStoresPerMemmoveOptSize = 8;
 170
 171   // Booleans always contain 0 or 1.
 172   setBooleanContents(ZeroOrOneBooleanContent);
 173 }
 174
 175 SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
 176                                             SelectionDAG &DAG) const {
 177   switch (Op.getOpcode()) {
 178   case ISD::MUL:
 179     return LowerMUL(Op, DAG);
 180   case ISD::BR_CC:
 181     return LowerBR_CC(Op, DAG);
 182   case ISD::ConstantPool:
 183     return LowerConstantPool(Op, DAG);
 184   case ISD::GlobalAddress:
 185     return LowerGlobalAddress(Op, DAG);
 186   case ISD::BlockAddress:
 187     return LowerBlockAddress(Op, DAG);
 188   case ISD::JumpTable:
 189     return LowerJumpTable(Op, DAG);
 190   case ISD::SELECT_CC:
 191     return LowerSELECT_CC(Op, DAG);
 192   case ISD::SETCC:
 193     return LowerSETCC(Op, DAG);
 194   case ISD::SHL_PARTS:
 195     return LowerSHL_PARTS(Op, DAG);
 196   case ISD::SRL_PARTS:
 197     return LowerSRL_PARTS(Op, DAG);
 198   case ISD::VASTART:
 199     return LowerVASTART(Op, DAG);
 200   case ISD::DYNAMIC_STACKALLOC:
 201     return LowerDYNAMIC_STACKALLOC(Op, DAG);
 202   case ISD::RETURNADDR:
 203     return LowerRETURNADDR(Op, DAG);
 204   case ISD::FRAMEADDR:
 205     return LowerFRAMEADDR(Op, DAG);
 206   default:
 207     llvm_unreachable("unimplemented operand");
 208   }
 209 }
 210
 211 //===----------------------------------------------------------------------===//
 212 //                       Lanai Inline Assembly Support
 213 //===----------------------------------------------------------------------===//
 214
 215 unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT /*VT*/,
 216                                                 SelectionDAG & /*DAG*/) const {
 217   // Only unallocatable registers should be matched here.
 218   unsigned Reg = StringSwitch<unsigned>(RegName)
 219                      .Case("pc", Lanai::PC)
 220                      .Case("sp", Lanai::SP)
 221                      .Case("fp", Lanai::FP)
 222                      .Case("rr1", Lanai::RR1)
 223                      .Case("r10", Lanai::R10)
 224                      .Case("rr2", Lanai::RR2)
 225                      .Case("r11", Lanai::R11)
 226                      .Case("rca", Lanai::RCA)
 227                      .Default(0);
 228
 229   if (Reg)
 230     return Reg;
 231   report_fatal_error("Invalid register name global variable");
 232 }
 233
 234 std::pair<unsigned, const TargetRegisterClass *>
 235 LanaiTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 236                                                   StringRef Constraint,
 237                                                   MVT VT) const {
 238   if (Constraint.size() == 1)
 239     // GCC Constraint Letters
 240     switch (Constraint[0]) {
 241     case 'r': // GENERAL_REGS
 242       return std::make_pair(0U, &Lanai::GPRRegClass);
 243     default:
 244       break;
 245     }
 246
 247   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 248 }
 249
 250 // Examine constraint type and operand type and determine a weight value.
 251 // This object must already have been set up with the operand type
 252 // and the current alternative constraint selected.
 253 TargetLowering::ConstraintWeight
 254 LanaiTargetLowering::getSingleConstraintMatchWeight(
 255     AsmOperandInfo &Info, const char *Constraint) const {
 256   ConstraintWeight Weight = CW_Invalid;
 257   Value *CallOperandVal = Info.CallOperandVal;
 258   // If we don't have a value, we can't do a match,
 259   // but allow it at the lowest weight.
 260   if (CallOperandVal == nullptr)
 261     return CW_Default;
 262   // Look at the constraint type.
 263   switch (*Constraint) {
 264   case 'I': // signed 16 bit immediate
 265   case 'J': // integer zero
 266   case 'K': // unsigned 16 bit immediate
 267   case 'L': // immediate in the range 0 to 31
 268   case 'M': // signed 32 bit immediate where lower 16 bits are 0
 269   case 'N': // signed 26 bit immediate
 270   case 'O': // integer zero
 271     if (isa<ConstantInt>(CallOperandVal))
 272       Weight = CW_Constant;
 273     break;
 274   default:
 275     Weight = TargetLowering::getSingleConstraintMatchWeight(Info, Constraint);
 276     break;
 277   }
 278   return Weight;
 279 }
 280
 281 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 282 // vector.  If it is invalid, don't add anything to Ops.
 283 void LanaiTargetLowering::LowerAsmOperandForConstraint(
 284     SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
 285     SelectionDAG &DAG) const {
 286   SDValue Result(nullptr, 0);
 287
 288   // Only support length 1 constraints for now.
 289   if (Constraint.length() > 1)
 290     return;
 291
 292   char ConstraintLetter = Constraint[0];
 293   switch (ConstraintLetter) {
 294   case 'I': // Signed 16 bit constant
 295     // If this fails, the parent routine will give an error
 296     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 297       if (isInt<16>(C->getSExtValue())) {
 298         Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
 299                                        Op.getValueType());
 300         break;
 301       }
 302     }
 303     return;
 304   case 'J': // integer zero
 305   case 'O':
 306     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 307       if (C->getZExtValue() == 0) {
 308         Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
 309         break;
 310       }
 311     }
 312     return;
 313   case 'K': // unsigned 16 bit immediate
 314     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 315       if (isUInt<16>(C->getZExtValue())) {
 316         Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
 317                                        Op.getValueType());
 318         break;
 319       }
 320     }
 321     return;
 322   case 'L': // immediate in the range 0 to 31
 323     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 324       if (C->getZExtValue() <= 31) {
 325         Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
 326                                        Op.getValueType());
 327         break;
 328       }
 329     }
 330     return;
 331   case 'M': // signed 32 bit immediate where lower 16 bits are 0
 332     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 333       int64_t Val = C->getSExtValue();
 334       if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
 335         Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
 336         break;
 337       }
 338     }
 339     return;
 340   case 'N': // signed 26 bit immediate
 341     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 342       int64_t Val = C->getSExtValue();
 343       if ((Val >= -33554432) && (Val <= 33554431)) {
 344         Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
 345         break;
 346       }
 347     }
 348     return;
 349   default:
 350     break; // This will fall through to the generic implementation
 351   }
 352
 353   if (Result.getNode()) {
 354     Ops.push_back(Result);
 355     return;
 356   }
 357
 358   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 359 }
 360
 361 //===----------------------------------------------------------------------===//
 362 //                      Calling Convention Implementation
 363 //===----------------------------------------------------------------------===//
 364
 365 #include "LanaiGenCallingConv.inc"
 366
 367 static unsigned NumFixedArgs;
 368 static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
 369                               CCValAssign::LocInfo LocInfo,
 370                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
 371   // Handle fixed arguments with default CC.
 372   // Note: Both the default and fast CC handle VarArg the same and hence the
 373   // calling convention of the function is not considered here.
 374   if (ValNo < NumFixedArgs) {
 375     return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
 376   }
 377
 378   // Promote i8/i16 args to i32
 379   if (LocVT == MVT::i8 || LocVT == MVT::i16) {
 380     LocVT = MVT::i32;
 381     if (ArgFlags.isSExt())
 382       LocInfo = CCValAssign::SExt;
 383     else if (ArgFlags.isZExt())
 384       LocInfo = CCValAssign::ZExt;
 385     else
 386       LocInfo = CCValAssign::AExt;
 387   }
 388
 389   // VarArgs get passed on stack
 390   unsigned Offset = State.AllocateStack(4, 4);
 391   State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
 392   return false;
 393 }
 394
 395 SDValue LanaiTargetLowering::LowerFormalArguments(
 396     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
 397     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
 398     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 399   switch (CallConv) {
 400   case CallingConv::C:
 401   case CallingConv::Fast:
 402     return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
 403   default:
 404     report_fatal_error("Unsupported calling convention");
 405   }
 406 }
 407
 408 SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
 409                                        SmallVectorImpl<SDValue> &InVals) const {
 410   SelectionDAG &DAG = CLI.DAG;
 411   SDLoc &DL = CLI.DL;
 412   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
 413   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
 414   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
 415   SDValue Chain = CLI.Chain;
 416   SDValue Callee = CLI.Callee;
 417   bool &IsTailCall = CLI.IsTailCall;
 418   CallingConv::ID CallConv = CLI.CallConv;
 419   bool IsVarArg = CLI.IsVarArg;
 420
 421   // Lanai target does not yet support tail call optimization.
 422   IsTailCall = false;
 423
 424   switch (CallConv) {
 425   case CallingConv::Fast:
 426   case CallingConv::C:
 427     return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
 428                           OutVals, Ins, DL, DAG, InVals);
 429   default:
 430     report_fatal_error("Unsupported calling convention");
 431   }
 432 }
 433
 434 // LowerCCCArguments - transform physical registers into virtual registers and
 435 // generate load operations for arguments places on the stack.
 436 SDValue LanaiTargetLowering::LowerCCCArguments(
 437     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
 438     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
 439     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 440   MachineFunction &MF = DAG.getMachineFunction();
 441   MachineFrameInfo &MFI = MF.getFrameInfo();
 442   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 443   LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
 444
 445   // Assign locations to all of the incoming arguments.
 446   SmallVector<CCValAssign, 16> ArgLocs;
 447   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
 448                  *DAG.getContext());
 449   if (CallConv == CallingConv::Fast) {
 450     CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
 451   } else {
 452     CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
 453   }
 454
 455   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 456     CCValAssign &VA = ArgLocs[i];
 457     if (VA.isRegLoc()) {
 458       // Arguments passed in registers
 459       EVT RegVT = VA.getLocVT();
 460       switch (RegVT.getSimpleVT().SimpleTy) {
 461       case MVT::i32: {
 462         Register VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
 463         RegInfo.addLiveIn(VA.getLocReg(), VReg);
 464         SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
 465
 466         // If this is an 8/16-bit value, it is really passed promoted to 32
 467         // bits. Insert an assert[sz]ext to capture this, then truncate to the
 468         // right size.
 469         if (VA.getLocInfo() == CCValAssign::SExt)
 470           ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
 471                                  DAG.getValueType(VA.getValVT()));
 472         else if (VA.getLocInfo() == CCValAssign::ZExt)
 473           ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
 474                                  DAG.getValueType(VA.getValVT()));
 475
 476         if (VA.getLocInfo() != CCValAssign::Full)
 477           ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
 478
 479         InVals.push_back(ArgValue);
 480         break;
 481       }
 482       default:
 483         LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
 484                           << RegVT.getEVTString() << "\n");
 485         llvm_unreachable("unhandled argument type");
 486       }
 487     } else {
 488       // Sanity check
 489       assert(VA.isMemLoc());
 490       // Load the argument to a virtual register
 491       unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
 492       // Check that the argument fits in stack slot
 493       if (ObjSize > 4) {
 494         errs() << "LowerFormalArguments Unhandled argument type: "
 495                << EVT(VA.getLocVT()).getEVTString() << "\n";
 496       }
 497       // Create the frame index object for this incoming parameter...
 498       int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
 499
 500       // Create the SelectionDAG nodes corresponding to a load
 501       // from this parameter
 502       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
 503       InVals.push_back(DAG.getLoad(
 504           VA.getLocVT(), DL, Chain, FIN,
 505           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
 506     }
 507   }
 508
 509   // The Lanai ABI for returning structs by value requires that we copy
 510   // the sret argument into rv for the return. Save the argument into
 511   // a virtual register so that we can access it from the return points.
 512   if (MF.getFunction().hasStructRetAttr()) {
 513     unsigned Reg = LanaiMFI->getSRetReturnReg();
 514     if (!Reg) {
 515       Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
 516       LanaiMFI->setSRetReturnReg(Reg);
 517     }
 518     SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
 519     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
 520   }
 521
 522   if (IsVarArg) {
 523     // Record the frame index of the first variable argument
 524     // which is a value necessary to VASTART.
 525     int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
 526     LanaiMFI->setVarArgsFrameIndex(FI);
 527   }
 528
 529   return Chain;
 530 }
 531
 532 SDValue
 533 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
 534                                  bool IsVarArg,
 535                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
 536                                  const SmallVectorImpl<SDValue> &OutVals,
 537                                  const SDLoc &DL, SelectionDAG &DAG) const {
 538   // CCValAssign - represent the assignment of the return value to a location
 539   SmallVector<CCValAssign, 16> RVLocs;
 540
 541   // CCState - Info about the registers and stack slot.
 542   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
 543                  *DAG.getContext());
 544
 545   // Analize return values.
 546   CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
 547
 548   SDValue Flag;
 549   SmallVector<SDValue, 4> RetOps(1, Chain);
 550
 551   // Copy the result values into the output registers.
 552   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 553     CCValAssign &VA = RVLocs[i];
 554     assert(VA.isRegLoc() && "Can only return in registers!");
 555
 556     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
 557
 558     // Guarantee that all emitted copies are stuck together with flags.
 559     Flag = Chain.getValue(1);
 560     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
 561   }
 562
 563   // The Lanai ABI for returning structs by value requires that we copy
 564   // the sret argument into rv for the return. We saved the argument into
 565   // a virtual register in the entry block, so now we copy the value out
 566   // and into rv.
 567   if (DAG.getMachineFunction().getFunction().hasStructRetAttr()) {
 568     MachineFunction &MF = DAG.getMachineFunction();
 569     LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
 570     unsigned Reg = LanaiMFI->getSRetReturnReg();
 571     assert(Reg &&
 572            "SRetReturnReg should have been set in LowerFormalArguments().");
 573     SDValue Val =
 574         DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
 575
 576     Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
 577     Flag = Chain.getValue(1);
 578     RetOps.push_back(
 579         DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
 580   }
 581
 582   RetOps[0] = Chain; // Update chain
 583
 584   unsigned Opc = LanaiISD::RET_FLAG;
 585   if (Flag.getNode())
 586     RetOps.push_back(Flag);
 587
 588   // Return Void
 589   return DAG.getNode(Opc, DL, MVT::Other,
 590                      ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
 591 }
 592
 593 // LowerCCCCallTo - functions arguments are copied from virtual regs to
 594 // (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
 595 SDValue LanaiTargetLowering::LowerCCCCallTo(
 596     SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
 597     bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
 598     const SmallVectorImpl<SDValue> &OutVals,
 599     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
 600     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 601   // Analyze operands of the call, assigning locations to each operand.
 602   SmallVector<CCValAssign, 16> ArgLocs;
 603   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
 604                  *DAG.getContext());
 605   GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
 606   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
 607
 608   NumFixedArgs = 0;
 609   if (IsVarArg && G) {
 610     const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
 611     if (CalleeFn)
 612       NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
 613   }
 614   if (NumFixedArgs)
 615     CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
 616   else {
 617     if (CallConv == CallingConv::Fast)
 618       CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
 619     else
 620       CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
 621   }
 622
 623   // Get a count of how many bytes are to be pushed on the stack.
 624   unsigned NumBytes = CCInfo.getNextStackOffset();
 625
 626   // Create local copies for byval args.
 627   SmallVector<SDValue, 8> ByValArgs;
 628   for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
 629     ISD::ArgFlagsTy Flags = Outs[I].Flags;
 630     if (!Flags.isByVal())
 631       continue;
 632
 633     SDValue Arg = OutVals[I];
 634     unsigned Size = Flags.getByValSize();
 635     unsigned Align = Flags.getByValAlign();
 636
 637     int FI = MFI.CreateStackObject(Size, Align, false);
 638     SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
 639     SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
 640
 641     Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
 642                           /*IsVolatile=*/false,
 643                           /*AlwaysInline=*/false,
 644                           /*isTailCall=*/false, MachinePointerInfo(),
 645                           MachinePointerInfo());
 646     ByValArgs.push_back(FIPtr);
 647   }
 648
 649   Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
 650
 651   SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
 652   SmallVector<SDValue, 12> MemOpChains;
 653   SDValue StackPtr;
 654
 655   // Walk the register/memloc assignments, inserting copies/loads.
 656   for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
 657     CCValAssign &VA = ArgLocs[I];
 658     SDValue Arg = OutVals[I];
 659     ISD::ArgFlagsTy Flags = Outs[I].Flags;
 660
 661     // Promote the value if needed.
 662     switch (VA.getLocInfo()) {
 663     case CCValAssign::Full:
 664       break;
 665     case CCValAssign::SExt:
 666       Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
 667       break;
 668     case CCValAssign::ZExt:
 669       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
 670       break;
 671     case CCValAssign::AExt:
 672       Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
 673       break;
 674     default:
 675       llvm_unreachable("Unknown loc info!");
 676     }
 677
 678     // Use local copy if it is a byval arg.
 679     if (Flags.isByVal())
 680       Arg = ByValArgs[J++];
 681
 682     // Arguments that can be passed on register must be kept at RegsToPass
 683     // vector
 684     if (VA.isRegLoc()) {
 685       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
 686     } else {
 687       assert(VA.isMemLoc());
 688
 689       if (StackPtr.getNode() == nullptr)
 690         StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
 691                                       getPointerTy(DAG.getDataLayout()));
 692
 693       SDValue PtrOff =
 694           DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
 695                       DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
 696
 697       MemOpChains.push_back(
 698           DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
 699     }
 700   }
 701
 702   // Transform all store nodes into one single node because all store nodes are
 703   // independent of each other.
 704   if (!MemOpChains.empty())
 705     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
 706                         ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
 707
 708   SDValue InFlag;
 709
 710   // Build a sequence of copy-to-reg nodes chained together with token chain and
 711   // flag operands which copy the outgoing args into registers.  The InFlag in
 712   // necessary since all emitted instructions must be stuck together.
 713   for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
 714     Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
 715                              RegsToPass[I].second, InFlag);
 716     InFlag = Chain.getValue(1);
 717   }
 718
 719   // If the callee is a GlobalAddress node (quite common, every direct call is)
 720   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
 721   // Likewise ExternalSymbol -> TargetExternalSymbol.
 722   uint8_t OpFlag = LanaiII::MO_NO_FLAG;
 723   if (G) {
 724     Callee = DAG.getTargetGlobalAddress(
 725         G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
 726   } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
 727     Callee = DAG.getTargetExternalSymbol(
 728         E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
 729   }
 730
 731   // Returns a chain & a flag for retval copy to use.
 732   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
 733   SmallVector<SDValue, 8> Ops;
 734   Ops.push_back(Chain);
 735   Ops.push_back(Callee);
 736
 737   // Add a register mask operand representing the call-preserved registers.
 738   // TODO: Should return-twice functions be handled?
 739   const uint32_t *Mask =
 740       TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
 741   assert(Mask && "Missing call preserved mask for calling convention");
 742   Ops.push_back(DAG.getRegisterMask(Mask));
 743
 744   // Add argument registers to the end of the list so that they are
 745   // known live into the call.
 746   for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
 747     Ops.push_back(DAG.getRegister(RegsToPass[I].first,
 748                                   RegsToPass[I].second.getValueType()));
 749
 750   if (InFlag.getNode())
 751     Ops.push_back(InFlag);
 752
 753   Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
 754                       ArrayRef<SDValue>(&Ops[0], Ops.size()));
 755   InFlag = Chain.getValue(1);
 756
 757   // Create the CALLSEQ_END node.
 758   Chain = DAG.getCALLSEQ_END(
 759       Chain,
 760       DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
 761       DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
 762       DL);
 763   InFlag = Chain.getValue(1);
 764
 765   // Handle result values, copying them out of physregs into vregs that we
 766   // return.
 767   return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
 768                          InVals);
 769 }
 770
 771 // LowerCallResult - Lower the result values of a call into the
 772 // appropriate copies out of appropriate physical registers.
 773 SDValue LanaiTargetLowering::LowerCallResult(
 774     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
 775     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
 776     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 777   // Assign locations to each value returned by this call.
 778   SmallVector<CCValAssign, 16> RVLocs;
 779   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
 780                  *DAG.getContext());
 781
 782   CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
 783
 784   // Copy all of the result registers out of their specified physreg.
 785   for (unsigned I = 0; I != RVLocs.size(); ++I) {
 786     Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
 787                                RVLocs[I].getValVT(), InFlag)
 788                 .getValue(1);
 789     InFlag = Chain.getValue(2);
 790     InVals.push_back(Chain.getValue(0));
 791   }
 792
 793   return Chain;
 794 }
 795
 796 //===----------------------------------------------------------------------===//
 797 //                      Custom Lowerings
 798 //===----------------------------------------------------------------------===//
 799
 800 static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL,
 801                                         SDValue &RHS, SelectionDAG &DAG) {
 802   ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
 803
 804   // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
 805   // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
 806   // and Lanai only supports integer comparisons, so only provide definitions
 807   // for them.
 808   switch (SetCCOpcode) {
 809   case ISD::SETEQ:
 810     return LPCC::ICC_EQ;
 811   case ISD::SETGT:
 812     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
 813       if (RHSC->getZExtValue() == 0xFFFFFFFF) {
 814         // X > -1 -> X >= 0 -> is_plus(X)
 815         RHS = DAG.getConstant(0, DL, RHS.getValueType());
 816         return LPCC::ICC_PL;
 817       }
 818     return LPCC::ICC_GT;
 819   case ISD::SETUGT:
 820     return LPCC::ICC_UGT;
 821   case ISD::SETLT:
 822     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
 823       if (RHSC->getZExtValue() == 0)
 824         // X < 0 -> is_minus(X)
 825         return LPCC::ICC_MI;
 826     return LPCC::ICC_LT;
 827   case ISD::SETULT:
 828     return LPCC::ICC_ULT;
 829   case ISD::SETLE:
 830     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
 831       if (RHSC->getZExtValue() == 0xFFFFFFFF) {
 832         // X <= -1 -> X < 0 -> is_minus(X)
 833         RHS = DAG.getConstant(0, DL, RHS.getValueType());
 834         return LPCC::ICC_MI;
 835       }
 836     return LPCC::ICC_LE;
 837   case ISD::SETULE:
 838     return LPCC::ICC_ULE;
 839   case ISD::SETGE:
 840     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
 841       if (RHSC->getZExtValue() == 0)
 842         // X >= 0 -> is_plus(X)
 843         return LPCC::ICC_PL;
 844     return LPCC::ICC_GE;
 845   case ISD::SETUGE:
 846     return LPCC::ICC_UGE;
 847   case ISD::SETNE:
 848     return LPCC::ICC_NE;
 849   case ISD::SETONE:
 850   case ISD::SETUNE:
 851   case ISD::SETOGE:
 852   case ISD::SETOLE:
 853   case ISD::SETOLT:
 854   case ISD::SETOGT:
 855   case ISD::SETOEQ:
 856   case ISD::SETUEQ:
 857   case ISD::SETO:
 858   case ISD::SETUO:
 859     llvm_unreachable("Unsupported comparison.");
 860   default:
 861     llvm_unreachable("Unknown integer condition code!");
 862   }
 863 }
 864
 865 SDValue LanaiTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
 866   SDValue Chain = Op.getOperand(0);
 867   SDValue Cond = Op.getOperand(1);
 868   SDValue LHS = Op.getOperand(2);
 869   SDValue RHS = Op.getOperand(3);
 870   SDValue Dest = Op.getOperand(4);
 871   SDLoc DL(Op);
 872
 873   LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
 874   SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
 875   SDValue Flag =
 876       DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
 877
 878   return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
 879                      TargetCC, Flag);
 880 }
 881
 882 SDValue LanaiTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
 883   EVT VT = Op->getValueType(0);
 884   if (VT != MVT::i32)
 885     return SDValue();
 886
 887   ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
 888   if (!C)
 889     return SDValue();
 890
 891   int64_t MulAmt = C->getSExtValue();
 892   int32_t HighestOne = -1;
 893   uint32_t NonzeroEntries = 0;
 894   int SignedDigit[32] = {0};
 895
 896   // Convert to non-adjacent form (NAF) signed-digit representation.
 897   // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
 898   // minimal Hamming weight representation of a number (on average 1/3 of the
 899   // digits will be non-zero vs 1/2 for regular binary representation). And as
 900   // the non-zero digits will be the only digits contributing to the instruction
 901   // count, this is desirable. The next loop converts it to NAF (following the
 902   // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
 903   // choosing the non-zero coefficients such that the resulting quotient is
 904   // divisible by 2 which will cause the next coefficient to be zero.
 905   int64_t E = std::abs(MulAmt);
 906   int S = (MulAmt < 0 ? -1 : 1);
 907   int I = 0;
 908   while (E > 0) {
 909     int ZI = 0;
 910     if (E % 2 == 1) {
 911       ZI = 2 - (E % 4);
 912       if (ZI != 0)
 913         ++NonzeroEntries;
 914     }
 915     SignedDigit[I] = S * ZI;
 916     if (SignedDigit[I] == 1)
 917       HighestOne = I;
 918     E = (E - ZI) / 2;
 919     ++I;
 920   }
 921
 922   // Compute number of instructions required. Due to differences in lowering
 923   // between the different processors this count is not exact.
 924   // Start by assuming a shift and a add/sub for every non-zero entry (hence
 925   // every non-zero entry requires 1 shift and 1 add/sub except for the first
 926   // entry).
 927   int32_t InstrRequired = 2 * NonzeroEntries - 1;
 928   // Correct possible over-adding due to shift by 0 (which is not emitted).
 929   if (std::abs(MulAmt) % 2 == 1)
 930     --InstrRequired;
 931   // Return if the form generated would exceed the instruction threshold.
 932   if (InstrRequired > LanaiLowerConstantMulThreshold)
 933     return SDValue();
 934
 935   SDValue Res;
 936   SDLoc DL(Op);
 937   SDValue V = Op->getOperand(0);
 938
 939   // Initialize the running sum. Set the running sum to the maximal shifted
 940   // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
 941   // term NAF).
 942   if (HighestOne == -1)
 943     Res = DAG.getConstant(0, DL, MVT::i32);
 944   else {
 945     Res = DAG.getNode(ISD::SHL, DL, VT, V,
 946                       DAG.getConstant(HighestOne, DL, MVT::i32));
 947     SignedDigit[HighestOne] = 0;
 948   }
 949
 950   // Assemble multiplication from shift, add, sub using NAF form and running
 951   // sum.
 952   for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
 953        ++I) {
 954     if (SignedDigit[I] == 0)
 955       continue;
 956
 957     // Shifted multiplicand (v<<i).
 958     SDValue Op =
 959         DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
 960     if (SignedDigit[I] == 1)
 961       Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
 962     else if (SignedDigit[I] == -1)
 963       Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
 964   }
 965   return Res;
 966 }
 967
 968 SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
 969   SDValue LHS = Op.getOperand(0);
 970   SDValue RHS = Op.getOperand(1);
 971   SDValue Cond = Op.getOperand(2);
 972   SDLoc DL(Op);
 973
 974   LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
 975   SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
 976   SDValue Flag =
 977       DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
 978
 979   return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
 980 }
 981
 982 SDValue LanaiTargetLowering::LowerSELECT_CC(SDValue Op,
 983                                             SelectionDAG &DAG) const {
 984   SDValue LHS = Op.getOperand(0);
 985   SDValue RHS = Op.getOperand(1);
 986   SDValue TrueV = Op.getOperand(2);
 987   SDValue FalseV = Op.getOperand(3);
 988   SDValue Cond = Op.getOperand(4);
 989   SDLoc DL(Op);
 990
 991   LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
 992   SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
 993   SDValue Flag =
 994       DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
 995
 996   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
 997   return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
 998                      Flag);
 999 }
1000
1001 SDValue LanaiTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1002   MachineFunction &MF = DAG.getMachineFunction();
1003   LanaiMachineFunctionInfo *FuncInfo = MF.getInfo<LanaiMachineFunctionInfo>();
1004
1005   SDLoc DL(Op);
1006   SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1007                                  getPointerTy(DAG.getDataLayout()));
1008
1009   // vastart just stores the address of the VarArgsFrameIndex slot into the
1010   // memory location argument.
1011   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1012   return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1013                       MachinePointerInfo(SV));
1014 }
1015
1016 SDValue LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1017                                                      SelectionDAG &DAG) const {
1018   SDValue Chain = Op.getOperand(0);
1019   SDValue Size = Op.getOperand(1);
1020   SDLoc DL(Op);
1021
1022   unsigned SPReg = getStackPointerRegisterToSaveRestore();
1023
1024   // Get a reference to the stack pointer.
1025   SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1026
1027   // Subtract the dynamic size from the actual stack size to
1028   // obtain the new stack size.
1029   SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1030
1031   // For Lanai, the outgoing memory arguments area should be on top of the
1032   // alloca area on the stack i.e., the outgoing memory arguments should be
1033   // at a lower address than the alloca area. Move the alloca area down the
1034   // stack by adding back the space reserved for outgoing arguments to SP
1035   // here.
1036   //
1037   // We do not know what the size of the outgoing args is at this point.
1038   // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1039   // stack pointer. We replace this instruction with on that has the correct,
1040   // known offset in emitPrologue().
1041   SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1042
1043   // The Sub result contains the new stack start address, so it
1044   // must be placed in the stack pointer register.
1045   SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1046
1047   SDValue Ops[2] = {ArgAdjust, CopyChain};
1048   return DAG.getMergeValues(Ops, DL);
1049 }
1050
1051 SDValue LanaiTargetLowering::LowerRETURNADDR(SDValue Op,
1052                                              SelectionDAG &DAG) const {
1053   MachineFunction &MF = DAG.getMachineFunction();
1054   MachineFrameInfo &MFI = MF.getFrameInfo();
1055   MFI.setReturnAddressIsTaken(true);
1056
1057   EVT VT = Op.getValueType();
1058   SDLoc DL(Op);
1059   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1060   if (Depth) {
1061     SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1062     const unsigned Offset = -4;
1063     SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1064                               DAG.getIntPtrConstant(Offset, DL));
1065     return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1066   }
1067
1068   // Return the link register, which contains the return address.
1069   // Mark it an implicit live-in.
1070   unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1071   return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1072 }
1073
1074 SDValue LanaiTargetLowering::LowerFRAMEADDR(SDValue Op,
1075                                             SelectionDAG &DAG) const {
1076   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1077   MFI.setFrameAddressIsTaken(true);
1078
1079   EVT VT = Op.getValueType();
1080   SDLoc DL(Op);
1081   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1082   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1083   while (Depth--) {
1084     const unsigned Offset = -8;
1085     SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1086                               DAG.getIntPtrConstant(Offset, DL));
1087     FrameAddr =
1088         DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1089   }
1090   return FrameAddr;
1091 }
1092
1093 const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1094   switch (Opcode) {
1095   case LanaiISD::ADJDYNALLOC:
1096     return "LanaiISD::ADJDYNALLOC";
1097   case LanaiISD::RET_FLAG:
1098     return "LanaiISD::RET_FLAG";
1099   case LanaiISD::CALL:
1100     return "LanaiISD::CALL";
1101   case LanaiISD::SELECT_CC:
1102     return "LanaiISD::SELECT_CC";
1103   case LanaiISD::SETCC:
1104     return "LanaiISD::SETCC";
1105   case LanaiISD::SUBBF:
1106     return "LanaiISD::SUBBF";
1107   case LanaiISD::SET_FLAG:
1108     return "LanaiISD::SET_FLAG";
1109   case LanaiISD::BR_CC:
1110     return "LanaiISD::BR_CC";
1111   case LanaiISD::Wrapper:
1112     return "LanaiISD::Wrapper";
1113   case LanaiISD::HI:
1114     return "LanaiISD::HI";
1115   case LanaiISD::LO:
1116     return "LanaiISD::LO";
1117   case LanaiISD::SMALL:
1118     return "LanaiISD::SMALL";
1119   default:
1120     return nullptr;
1121   }
1122 }
1123
1124 SDValue LanaiTargetLowering::LowerConstantPool(SDValue Op,
1125                                                SelectionDAG &DAG) const {
1126   SDLoc DL(Op);
1127   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1128   const Constant *C = N->getConstVal();
1129   const LanaiTargetObjectFile *TLOF =
1130       static_cast<const LanaiTargetObjectFile *>(
1131           getTargetMachine().getObjFileLowering());
1132
1133   // If the code model is small or constant will be placed in the small section,
1134   // then assume address will fit in 21-bits.
1135   if (getTargetMachine().getCodeModel() == CodeModel::Small ||
1136       TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1137     SDValue Small = DAG.getTargetConstantPool(
1138         C, MVT::i32, N->getAlignment(), N->getOffset(), LanaiII::MO_NO_FLAG);
1139     return DAG.getNode(ISD::OR, DL, MVT::i32,
1140                        DAG.getRegister(Lanai::R0, MVT::i32),
1141                        DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1142   } else {
1143     uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1144     uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1145
1146     SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1147                                            N->getOffset(), OpFlagHi);
1148     SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1149                                            N->getOffset(), OpFlagLo);
1150     Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1151     Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1152     SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1153     return Result;
1154   }
1155 }
1156
1157 SDValue LanaiTargetLowering::LowerGlobalAddress(SDValue Op,
1158                                                 SelectionDAG &DAG) const {
1159   SDLoc DL(Op);
1160   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1161   int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1162
1163   const LanaiTargetObjectFile *TLOF =
1164       static_cast<const LanaiTargetObjectFile *>(
1165           getTargetMachine().getObjFileLowering());
1166
1167   // If the code model is small or global variable will be placed in the small
1168   // section, then assume address will fit in 21-bits.
1169   const GlobalObject *GO = GV->getBaseObject();
1170   if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1171     SDValue Small = DAG.getTargetGlobalAddress(
1172         GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
1173     return DAG.getNode(ISD::OR, DL, MVT::i32,
1174                        DAG.getRegister(Lanai::R0, MVT::i32),
1175                        DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1176   } else {
1177     uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1178     uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1179
1180     // Create the TargetGlobalAddress node, folding in the constant offset.
1181     SDValue Hi = DAG.getTargetGlobalAddress(
1182         GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1183     SDValue Lo = DAG.getTargetGlobalAddress(
1184         GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1185     Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1186     Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1187     return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1188   }
1189 }
1190
1191 SDValue LanaiTargetLowering::LowerBlockAddress(SDValue Op,
1192                                                SelectionDAG &DAG) const {
1193   SDLoc DL(Op);
1194   const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1195
1196   uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1197   uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1198
1199   SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1200   SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1201   Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1202   Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1203   SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1204   return Result;
1205 }
1206
1207 SDValue LanaiTargetLowering::LowerJumpTable(SDValue Op,
1208                                             SelectionDAG &DAG) const {
1209   SDLoc DL(Op);
1210   JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1211
1212   // If the code model is small assume address will fit in 21-bits.
1213   if (getTargetMachine().getCodeModel() == CodeModel::Small) {
1214     SDValue Small = DAG.getTargetJumpTable(
1215         JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG);
1216     return DAG.getNode(ISD::OR, DL, MVT::i32,
1217                        DAG.getRegister(Lanai::R0, MVT::i32),
1218                        DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1219   } else {
1220     uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1221     uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1222
1223     SDValue Hi = DAG.getTargetJumpTable(
1224         JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1225     SDValue Lo = DAG.getTargetJumpTable(
1226         JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1227     Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1228     Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1229     SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1230     return Result;
1231   }
1232 }
1233
1234 SDValue LanaiTargetLowering::LowerSHL_PARTS(SDValue Op,
1235                                             SelectionDAG &DAG) const {
1236   EVT VT = Op.getValueType();
1237   unsigned VTBits = VT.getSizeInBits();
1238   SDLoc dl(Op);
1239   assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1240   SDValue ShOpLo = Op.getOperand(0);
1241   SDValue ShOpHi = Op.getOperand(1);
1242   SDValue ShAmt = Op.getOperand(2);
1243
1244   // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1245   //   LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1246   //   HiBitsForHi = ShOpHi << ShAmt
1247   //   Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1248   //   Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1249   //   return (Hi << 32) | Lo;
1250
1251   SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1252                                  DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1253   SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1254
1255   // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1256   // wanted 0, so CSEL it directly.
1257   SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1258   SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1259   LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1260
1261   SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1262                                    DAG.getConstant(VTBits, dl, MVT::i32));
1263   SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1264   SDValue HiForNormalShift =
1265       DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1266
1267   SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1268
1269   SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1270   SDValue Hi =
1271       DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1272
1273   // Lanai shifts of larger than register sizes are wrapped rather than
1274   // clamped, so we can't just emit "lo << b" if b is too big.
1275   SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1276   SDValue Lo = DAG.getSelect(
1277       dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1278
1279   SDValue Ops[2] = {Lo, Hi};
1280   return DAG.getMergeValues(Ops, dl);
1281 }
1282
1283 SDValue LanaiTargetLowering::LowerSRL_PARTS(SDValue Op,
1284                                             SelectionDAG &DAG) const {
1285   MVT VT = Op.getSimpleValueType();
1286   unsigned VTBits = VT.getSizeInBits();
1287   SDLoc dl(Op);
1288   SDValue ShOpLo = Op.getOperand(0);
1289   SDValue ShOpHi = Op.getOperand(1);
1290   SDValue ShAmt = Op.getOperand(2);
1291
1292   // Performs the following for a >> b:
1293   //   unsigned r_high = a_high >> b;
1294   //   r_high = (32 - b <= 0) ? 0 : r_high;
1295   //
1296   //   unsigned r_low = a_low >> b;
1297   //   r_low = (32 - b <= 0) ? r_high : r_low;
1298   //   r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1299   //   return (unsigned long long)r_high << 32 | r_low;
1300   // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1301   // mask the shift amount.
1302
1303   SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1304   SDValue NegatedPlus32 = DAG.getNode(
1305       ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1306   SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1307
1308   SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1309   Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1310
1311   SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1312   Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1313   SDValue CarryBits =
1314       DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1315   SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1316   Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1317                      DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1318
1319   SDValue Ops[2] = {Lo, Hi};
1320   return DAG.getMergeValues(Ops, dl);
1321 }
1322
1323 // Helper function that checks if N is a null or all ones constant.
1324 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1325   return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1326 }
1327
1328 // Return true if N is conditionally 0 or all ones.
1329 // Detects these expressions where cc is an i1 value:
1330 //
1331 //   (select cc 0, y)   [AllOnes=0]
1332 //   (select cc y, 0)   [AllOnes=0]
1333 //   (zext cc)          [AllOnes=0]
1334 //   (sext cc)          [AllOnes=0/1]
1335 //   (select cc -1, y)  [AllOnes=1]
1336 //   (select cc y, -1)  [AllOnes=1]
1337 //
1338 // * AllOnes determines whether to check for an all zero (AllOnes false) or an
1339 //   all ones operand (AllOnes true).
1340 // * Invert is set when N is the all zero/ones constant when CC is false.
1341 // * OtherOp is set to the alternative value of N.
1342 //
1343 // For example, for (select cc X, Y) and AllOnes = 0 if:
1344 // * X = 0, Invert = False and OtherOp = Y
1345 // * Y = 0, Invert = True and OtherOp = X
1346 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1347                                        bool &Invert, SDValue &OtherOp,
1348                                        SelectionDAG &DAG) {
1349   switch (N->getOpcode()) {
1350   default:
1351     return false;
1352   case ISD::SELECT: {
1353     CC = N->getOperand(0);
1354     SDValue N1 = N->getOperand(1);
1355     SDValue N2 = N->getOperand(2);
1356     if (isZeroOrAllOnes(N1, AllOnes)) {
1357       Invert = false;
1358       OtherOp = N2;
1359       return true;
1360     }
1361     if (isZeroOrAllOnes(N2, AllOnes)) {
1362       Invert = true;
1363       OtherOp = N1;
1364       return true;
1365     }
1366     return false;
1367   }
1368   case ISD::ZERO_EXTEND: {
1369     // (zext cc) can never be the all ones value.
1370     if (AllOnes)
1371       return false;
1372     CC = N->getOperand(0);
1373     if (CC.getValueType() != MVT::i1)
1374       return false;
1375     SDLoc dl(N);
1376     EVT VT = N->getValueType(0);
1377     OtherOp = DAG.getConstant(1, dl, VT);
1378     Invert = true;
1379     return true;
1380   }
1381   case ISD::SIGN_EXTEND: {
1382     CC = N->getOperand(0);
1383     if (CC.getValueType() != MVT::i1)
1384       return false;
1385     SDLoc dl(N);
1386     EVT VT = N->getValueType(0);
1387     Invert = !AllOnes;
1388     if (AllOnes)
1389       // When looking for an AllOnes constant, N is an sext, and the 'other'
1390       // value is 0.
1391       OtherOp = DAG.getConstant(0, dl, VT);
1392     else
1393       OtherOp =
1394           DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, VT);
1395     return true;
1396   }
1397   }
1398 }
1399
1400 // Combine a constant select operand into its use:
1401 //
1402 //   (add (select cc, 0, c), x)  -> (select cc, x, (add, x, c))
1403 //   (sub x, (select cc, 0, c))  -> (select cc, x, (sub, x, c))
1404 //   (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))  [AllOnes=1]
1405 //   (or  (select cc, 0, c), x)  -> (select cc, x, (or, x, c))
1406 //   (xor (select cc, 0, c), x)  -> (select cc, x, (xor, x, c))
1407 //
1408 // The transform is rejected if the select doesn't have a constant operand that
1409 // is null, or all ones when AllOnes is set.
1410 //
1411 // Also recognize sext/zext from i1:
1412 //
1413 //   (add (zext cc), x) -> (select cc (add x, 1), x)
1414 //   (add (sext cc), x) -> (select cc (add x, -1), x)
1415 //
1416 // These transformations eventually create predicated instructions.
1417 static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
1418                                    TargetLowering::DAGCombinerInfo &DCI,
1419                                    bool AllOnes) {
1420   SelectionDAG &DAG = DCI.DAG;
1421   EVT VT = N->getValueType(0);
1422   SDValue NonConstantVal;
1423   SDValue CCOp;
1424   bool SwapSelectOps;
1425   if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1426                                   NonConstantVal, DAG))
1427     return SDValue();
1428
1429   // Slct is now know to be the desired identity constant when CC is true.
1430   SDValue TrueVal = OtherOp;
1431   SDValue FalseVal =
1432       DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1433   // Unless SwapSelectOps says CC should be false.
1434   if (SwapSelectOps)
1435     std::swap(TrueVal, FalseVal);
1436
1437   return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1438 }
1439
1440 // Attempt combineSelectAndUse on each operand of a commutative operator N.
1441 static SDValue
1442 combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1443                                bool AllOnes) {
1444   SDValue N0 = N->getOperand(0);
1445   SDValue N1 = N->getOperand(1);
1446   if (N0.getNode()->hasOneUse())
1447     if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1448       return Result;
1449   if (N1.getNode()->hasOneUse())
1450     if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1451       return Result;
1452   return SDValue();
1453 }
1454
1455 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1456 static SDValue PerformSUBCombine(SDNode *N,
1457                                  TargetLowering::DAGCombinerInfo &DCI) {
1458   SDValue N0 = N->getOperand(0);
1459   SDValue N1 = N->getOperand(1);
1460
1461   // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1462   if (N1.getNode()->hasOneUse())
1463     if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1464       return Result;
1465
1466   return SDValue();
1467 }
1468
1469 SDValue LanaiTargetLowering::PerformDAGCombine(SDNode *N,
1470                                                DAGCombinerInfo &DCI) const {
1471   switch (N->getOpcode()) {
1472   default:
1473     break;
1474   case ISD::ADD:
1475   case ISD::OR:
1476   case ISD::XOR:
1477     return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1478   case ISD::AND:
1479     return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1480   case ISD::SUB:
1481     return PerformSUBCombine(N, DCI);
1482   }
1483
1484   return SDValue();
1485 }
1486
1487 void LanaiTargetLowering::computeKnownBitsForTargetNode(
1488     const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1489     const SelectionDAG &DAG, unsigned Depth) const {
1490   unsigned BitWidth = Known.getBitWidth();
1491   switch (Op.getOpcode()) {
1492   default:
1493     break;
1494   case LanaiISD::SETCC:
1495     Known = KnownBits(BitWidth);
1496     Known.Zero.setBits(1, BitWidth);
1497     break;
1498   case LanaiISD::SELECT_CC:
1499     KnownBits Known2;
1500     Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1501     Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
1502     Known.Zero &= Known2.Zero;
1503     Known.One &= Known2.One;
1504     break;
1505   }
1506 }