[AMDGPU] Check for immediate SrcC in mfma in AsmParser
[llvm-core.git] / lib / Target / Lanai / LanaiRegisterInfo.h
blob4e4da619d366cff9592a339b29ec5b91319e7794
1 //===- LanaiRegisterInfo.h - Lanai Register Information Impl ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Lanai implementation of the TargetRegisterInfo class.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_LANAI_LANAIREGISTERINFO_H
14 #define LLVM_LIB_TARGET_LANAI_LANAIREGISTERINFO_H
16 #include "llvm/CodeGen/TargetRegisterInfo.h"
18 #define GET_REGINFO_HEADER
19 #include "LanaiGenRegisterInfo.inc"
21 namespace llvm {
23 struct LanaiRegisterInfo : public LanaiGenRegisterInfo {
24 LanaiRegisterInfo();
26 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
27 CallingConv::ID) const override;
29 // Code Generation virtual methods.
30 const uint16_t *
31 getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
33 BitVector getReservedRegs(const MachineFunction &MF) const override;
35 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
37 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
39 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
40 unsigned FIOperandNum,
41 RegScavenger *RS = nullptr) const override;
43 // Debug information queries.
44 unsigned getRARegister() const;
45 Register getFrameRegister(const MachineFunction &MF) const override;
46 Register getBaseRegister() const;
47 bool hasBasePointer(const MachineFunction &MF) const;
49 int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
52 } // end namespace llvm
54 #endif // LLVM_LIB_TARGET_LANAI_LANAIREGISTERINFO_H