lib/Target/MSP430/MSP430ISelLowering.cpp

   1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the MSP430TargetLowering class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "MSP430ISelLowering.h"
  14 #include "MSP430.h"
  15 #include "MSP430MachineFunctionInfo.h"
  16 #include "MSP430Subtarget.h"
  17 #include "MSP430TargetMachine.h"
  18 #include "llvm/CodeGen/CallingConvLower.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/CodeGen/MachineRegisterInfo.h"
  23 #include "llvm/CodeGen/SelectionDAGISel.h"
  24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
  25 #include "llvm/CodeGen/ValueTypes.h"
  26 #include "llvm/IR/CallingConv.h"
  27 #include "llvm/IR/DerivedTypes.h"
  28 #include "llvm/IR/Function.h"
  29 #include "llvm/IR/GlobalAlias.h"
  30 #include "llvm/IR/GlobalVariable.h"
  31 #include "llvm/IR/Intrinsics.h"
  32 #include "llvm/Support/CommandLine.h"
  33 #include "llvm/Support/Debug.h"
  34 #include "llvm/Support/ErrorHandling.h"
  35 #include "llvm/Support/raw_ostream.h"
  36 using namespace llvm;
  37
  38 #define DEBUG_TYPE "msp430-lower"
  39
  40 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
  41                                            const MSP430Subtarget &STI)
  42     : TargetLowering(TM) {
  43
  44   // Set up the register classes.
  45   addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
  46   addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
  47
  48   // Compute derived properties from the register classes
  49   computeRegisterProperties(STI.getRegisterInfo());
  50
  51   // Provide all sorts of operation actions
  52   setStackPointerRegisterToSaveRestore(MSP430::SP);
  53   setBooleanContents(ZeroOrOneBooleanContent);
  54   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
  55
  56   // We have post-incremented loads / stores.
  57   setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
  58   setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
  59
  60   for (MVT VT : MVT::integer_valuetypes()) {
  61     setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);
  62     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);
  63     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);
  64     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8,  Expand);
  65     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
  66   }
  67
  68   // We don't have any truncstores
  69   setTruncStoreAction(MVT::i16, MVT::i8, Expand);
  70
  71   setOperationAction(ISD::SRA,              MVT::i8,    Custom);
  72   setOperationAction(ISD::SHL,              MVT::i8,    Custom);
  73   setOperationAction(ISD::SRL,              MVT::i8,    Custom);
  74   setOperationAction(ISD::SRA,              MVT::i16,   Custom);
  75   setOperationAction(ISD::SHL,              MVT::i16,   Custom);
  76   setOperationAction(ISD::SRL,              MVT::i16,   Custom);
  77   setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
  78   setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
  79   setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
  80   setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
  81   setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
  82   setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
  83   setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
  84   setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
  85   setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
  86   setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
  87   setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
  88   setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
  89   setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
  90   setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
  91   setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
  92   setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
  93   setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
  94   setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
  95   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
  96   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
  97   setOperationAction(ISD::STACKSAVE,        MVT::Other, Expand);
  98   setOperationAction(ISD::STACKRESTORE,     MVT::Other, Expand);
  99
 100   setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
 101   setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
 102   setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
 103   setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
 104   setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
 105   setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
 106
 107   setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
 108   setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
 109   setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
 110   setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
 111   setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
 112   setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
 113
 114   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
 115
 116   // FIXME: Implement efficiently multiplication by a constant
 117   setOperationAction(ISD::MUL,              MVT::i8,    Promote);
 118   setOperationAction(ISD::MULHS,            MVT::i8,    Promote);
 119   setOperationAction(ISD::MULHU,            MVT::i8,    Promote);
 120   setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Promote);
 121   setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Promote);
 122   setOperationAction(ISD::MUL,              MVT::i16,   LibCall);
 123   setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
 124   setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
 125   setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
 126   setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
 127
 128   setOperationAction(ISD::UDIV,             MVT::i8,    Promote);
 129   setOperationAction(ISD::UDIVREM,          MVT::i8,    Promote);
 130   setOperationAction(ISD::UREM,             MVT::i8,    Promote);
 131   setOperationAction(ISD::SDIV,             MVT::i8,    Promote);
 132   setOperationAction(ISD::SDIVREM,          MVT::i8,    Promote);
 133   setOperationAction(ISD::SREM,             MVT::i8,    Promote);
 134   setOperationAction(ISD::UDIV,             MVT::i16,   LibCall);
 135   setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
 136   setOperationAction(ISD::UREM,             MVT::i16,   LibCall);
 137   setOperationAction(ISD::SDIV,             MVT::i16,   LibCall);
 138   setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
 139   setOperationAction(ISD::SREM,             MVT::i16,   LibCall);
 140
 141   // varargs support
 142   setOperationAction(ISD::VASTART,          MVT::Other, Custom);
 143   setOperationAction(ISD::VAARG,            MVT::Other, Expand);
 144   setOperationAction(ISD::VAEND,            MVT::Other, Expand);
 145   setOperationAction(ISD::VACOPY,           MVT::Other, Expand);
 146   setOperationAction(ISD::JumpTable,        MVT::i16,   Custom);
 147
 148   // EABI Libcalls - EABI Section 6.2
 149   const struct {
 150     const RTLIB::Libcall Op;
 151     const char * const Name;
 152     const ISD::CondCode Cond;
 153   } LibraryCalls[] = {
 154     // Floating point conversions - EABI Table 6
 155     { RTLIB::FPROUND_F64_F32,   "__mspabi_cvtdf",   ISD::SETCC_INVALID },
 156     { RTLIB::FPEXT_F32_F64,     "__mspabi_cvtfd",   ISD::SETCC_INVALID },
 157     // The following is NOT implemented in libgcc
 158     //{ RTLIB::FPTOSINT_F64_I16,  "__mspabi_fixdi", ISD::SETCC_INVALID },
 159     { RTLIB::FPTOSINT_F64_I32,  "__mspabi_fixdli",  ISD::SETCC_INVALID },
 160     { RTLIB::FPTOSINT_F64_I64,  "__mspabi_fixdlli", ISD::SETCC_INVALID },
 161     // The following is NOT implemented in libgcc
 162     //{ RTLIB::FPTOUINT_F64_I16,  "__mspabi_fixdu", ISD::SETCC_INVALID },
 163     { RTLIB::FPTOUINT_F64_I32,  "__mspabi_fixdul",  ISD::SETCC_INVALID },
 164     { RTLIB::FPTOUINT_F64_I64,  "__mspabi_fixdull", ISD::SETCC_INVALID },
 165     // The following is NOT implemented in libgcc
 166     //{ RTLIB::FPTOSINT_F32_I16,  "__mspabi_fixfi", ISD::SETCC_INVALID },
 167     { RTLIB::FPTOSINT_F32_I32,  "__mspabi_fixfli",  ISD::SETCC_INVALID },
 168     { RTLIB::FPTOSINT_F32_I64,  "__mspabi_fixflli", ISD::SETCC_INVALID },
 169     // The following is NOT implemented in libgcc
 170     //{ RTLIB::FPTOUINT_F32_I16,  "__mspabi_fixfu", ISD::SETCC_INVALID },
 171     { RTLIB::FPTOUINT_F32_I32,  "__mspabi_fixful",  ISD::SETCC_INVALID },
 172     { RTLIB::FPTOUINT_F32_I64,  "__mspabi_fixfull", ISD::SETCC_INVALID },
 173     // TODO The following IS implemented in libgcc
 174     //{ RTLIB::SINTTOFP_I16_F64,  "__mspabi_fltid", ISD::SETCC_INVALID },
 175     { RTLIB::SINTTOFP_I32_F64,  "__mspabi_fltlid",  ISD::SETCC_INVALID },
 176     // TODO The following IS implemented in libgcc but is not in the EABI
 177     { RTLIB::SINTTOFP_I64_F64,  "__mspabi_fltllid", ISD::SETCC_INVALID },
 178     // TODO The following IS implemented in libgcc
 179     //{ RTLIB::UINTTOFP_I16_F64,  "__mspabi_fltud", ISD::SETCC_INVALID },
 180     { RTLIB::UINTTOFP_I32_F64,  "__mspabi_fltuld",  ISD::SETCC_INVALID },
 181     // The following IS implemented in libgcc but is not in the EABI
 182     { RTLIB::UINTTOFP_I64_F64,  "__mspabi_fltulld", ISD::SETCC_INVALID },
 183     // TODO The following IS implemented in libgcc
 184     //{ RTLIB::SINTTOFP_I16_F32,  "__mspabi_fltif", ISD::SETCC_INVALID },
 185     { RTLIB::SINTTOFP_I32_F32,  "__mspabi_fltlif",  ISD::SETCC_INVALID },
 186     // TODO The following IS implemented in libgcc but is not in the EABI
 187     { RTLIB::SINTTOFP_I64_F32,  "__mspabi_fltllif", ISD::SETCC_INVALID },
 188     // TODO The following IS implemented in libgcc
 189     //{ RTLIB::UINTTOFP_I16_F32,  "__mspabi_fltuf", ISD::SETCC_INVALID },
 190     { RTLIB::UINTTOFP_I32_F32,  "__mspabi_fltulf",  ISD::SETCC_INVALID },
 191     // The following IS implemented in libgcc but is not in the EABI
 192     { RTLIB::UINTTOFP_I64_F32,  "__mspabi_fltullf", ISD::SETCC_INVALID },
 193
 194     // Floating point comparisons - EABI Table 7
 195     { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
 196     { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE },
 197     { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE },
 198     { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
 199     { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE },
 200     { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT },
 201     { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
 202     { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE },
 203     { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE },
 204     { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
 205     { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE },
 206     { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT },
 207
 208     // Floating point arithmetic - EABI Table 8
 209     { RTLIB::ADD_F64,  "__mspabi_addd", ISD::SETCC_INVALID },
 210     { RTLIB::ADD_F32,  "__mspabi_addf", ISD::SETCC_INVALID },
 211     { RTLIB::DIV_F64,  "__mspabi_divd", ISD::SETCC_INVALID },
 212     { RTLIB::DIV_F32,  "__mspabi_divf", ISD::SETCC_INVALID },
 213     { RTLIB::MUL_F64,  "__mspabi_mpyd", ISD::SETCC_INVALID },
 214     { RTLIB::MUL_F32,  "__mspabi_mpyf", ISD::SETCC_INVALID },
 215     { RTLIB::SUB_F64,  "__mspabi_subd", ISD::SETCC_INVALID },
 216     { RTLIB::SUB_F32,  "__mspabi_subf", ISD::SETCC_INVALID },
 217     // The following are NOT implemented in libgcc
 218     // { RTLIB::NEG_F64,  "__mspabi_negd", ISD::SETCC_INVALID },
 219     // { RTLIB::NEG_F32,  "__mspabi_negf", ISD::SETCC_INVALID },
 220
 221     // Universal Integer Operations - EABI Table 9
 222     { RTLIB::SDIV_I16,   "__mspabi_divi", ISD::SETCC_INVALID },
 223     { RTLIB::SDIV_I32,   "__mspabi_divli", ISD::SETCC_INVALID },
 224     { RTLIB::SDIV_I64,   "__mspabi_divlli", ISD::SETCC_INVALID },
 225     { RTLIB::UDIV_I16,   "__mspabi_divu", ISD::SETCC_INVALID },
 226     { RTLIB::UDIV_I32,   "__mspabi_divul", ISD::SETCC_INVALID },
 227     { RTLIB::UDIV_I64,   "__mspabi_divull", ISD::SETCC_INVALID },
 228     { RTLIB::SREM_I16,   "__mspabi_remi", ISD::SETCC_INVALID },
 229     { RTLIB::SREM_I32,   "__mspabi_remli", ISD::SETCC_INVALID },
 230     { RTLIB::SREM_I64,   "__mspabi_remlli", ISD::SETCC_INVALID },
 231     { RTLIB::UREM_I16,   "__mspabi_remu", ISD::SETCC_INVALID },
 232     { RTLIB::UREM_I32,   "__mspabi_remul", ISD::SETCC_INVALID },
 233     { RTLIB::UREM_I64,   "__mspabi_remull", ISD::SETCC_INVALID },
 234
 235     // Bitwise Operations - EABI Table 10
 236     // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc
 237     { RTLIB::SRL_I32,    "__mspabi_srll", ISD::SETCC_INVALID },
 238     { RTLIB::SRA_I32,    "__mspabi_sral", ISD::SETCC_INVALID },
 239     { RTLIB::SHL_I32,    "__mspabi_slll", ISD::SETCC_INVALID },
 240     // __mspabi_[srlll/srall/sllll/rlli/rlll] are NOT implemented in libgcc
 241
 242   };
 243
 244   for (const auto &LC : LibraryCalls) {
 245     setLibcallName(LC.Op, LC.Name);
 246     if (LC.Cond != ISD::SETCC_INVALID)
 247       setCmpLibcallCC(LC.Op, LC.Cond);
 248   }
 249
 250   if (STI.hasHWMult16()) {
 251     const struct {
 252       const RTLIB::Libcall Op;
 253       const char * const Name;
 254     } LibraryCalls[] = {
 255       // Integer Multiply - EABI Table 9
 256       { RTLIB::MUL_I16,   "__mspabi_mpyi_hw" },
 257       { RTLIB::MUL_I32,   "__mspabi_mpyl_hw" },
 258       { RTLIB::MUL_I64,   "__mspabi_mpyll_hw" },
 259       // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc
 260       // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc
 261     };
 262     for (const auto &LC : LibraryCalls) {
 263       setLibcallName(LC.Op, LC.Name);
 264     }
 265   } else if (STI.hasHWMult32()) {
 266     const struct {
 267       const RTLIB::Libcall Op;
 268       const char * const Name;
 269     } LibraryCalls[] = {
 270       // Integer Multiply - EABI Table 9
 271       { RTLIB::MUL_I16,   "__mspabi_mpyi_hw" },
 272       { RTLIB::MUL_I32,   "__mspabi_mpyl_hw32" },
 273       { RTLIB::MUL_I64,   "__mspabi_mpyll_hw32" },
 274       // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc
 275       // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc
 276     };
 277     for (const auto &LC : LibraryCalls) {
 278       setLibcallName(LC.Op, LC.Name);
 279     }
 280   } else if (STI.hasHWMultF5()) {
 281     const struct {
 282       const RTLIB::Libcall Op;
 283       const char * const Name;
 284     } LibraryCalls[] = {
 285       // Integer Multiply - EABI Table 9
 286       { RTLIB::MUL_I16,   "__mspabi_mpyi_f5hw" },
 287       { RTLIB::MUL_I32,   "__mspabi_mpyl_f5hw" },
 288       { RTLIB::MUL_I64,   "__mspabi_mpyll_f5hw" },
 289       // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc
 290       // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc
 291     };
 292     for (const auto &LC : LibraryCalls) {
 293       setLibcallName(LC.Op, LC.Name);
 294     }
 295   } else { // NoHWMult
 296     const struct {
 297       const RTLIB::Libcall Op;
 298       const char * const Name;
 299     } LibraryCalls[] = {
 300       // Integer Multiply - EABI Table 9
 301       { RTLIB::MUL_I16,   "__mspabi_mpyi" },
 302       { RTLIB::MUL_I32,   "__mspabi_mpyl" },
 303       { RTLIB::MUL_I64,   "__mspabi_mpyll" },
 304       // The __mspabi_mpysl* functions are NOT implemented in libgcc
 305       // The __mspabi_mpyul* functions are NOT implemented in libgcc
 306     };
 307     for (const auto &LC : LibraryCalls) {
 308       setLibcallName(LC.Op, LC.Name);
 309     }
 310     setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::MSP430_BUILTIN);
 311   }
 312
 313   // Several of the runtime library functions use a special calling conv
 314   setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::MSP430_BUILTIN);
 315   setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::MSP430_BUILTIN);
 316   setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::MSP430_BUILTIN);
 317   setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::MSP430_BUILTIN);
 318   setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::MSP430_BUILTIN);
 319   setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::MSP430_BUILTIN);
 320   setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::MSP430_BUILTIN);
 321   setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::MSP430_BUILTIN);
 322   setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::MSP430_BUILTIN);
 323   setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::MSP430_BUILTIN);
 324   setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::MSP430_BUILTIN);
 325   setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::MSP430_BUILTIN);
 326   setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::MSP430_BUILTIN);
 327   setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::MSP430_BUILTIN);
 328   // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
 329
 330   setMinFunctionAlignment(1);
 331   setPrefFunctionAlignment(1);
 332 }
 333
 334 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
 335                                              SelectionDAG &DAG) const {
 336   switch (Op.getOpcode()) {
 337   case ISD::SHL: // FALLTHROUGH
 338   case ISD::SRL:
 339   case ISD::SRA:              return LowerShifts(Op, DAG);
 340   case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
 341   case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
 342   case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
 343   case ISD::SETCC:            return LowerSETCC(Op, DAG);
 344   case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
 345   case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
 346   case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
 347   case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
 348   case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
 349   case ISD::VASTART:          return LowerVASTART(Op, DAG);
 350   case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
 351   default:
 352     llvm_unreachable("unimplemented operand");
 353   }
 354 }
 355
 356 //===----------------------------------------------------------------------===//
 357 //                       MSP430 Inline Assembly Support
 358 //===----------------------------------------------------------------------===//
 359
 360 /// getConstraintType - Given a constraint letter, return the type of
 361 /// constraint it is for this target.
 362 TargetLowering::ConstraintType
 363 MSP430TargetLowering::getConstraintType(StringRef Constraint) const {
 364   if (Constraint.size() == 1) {
 365     switch (Constraint[0]) {
 366     case 'r':
 367       return C_RegisterClass;
 368     default:
 369       break;
 370     }
 371   }
 372   return TargetLowering::getConstraintType(Constraint);
 373 }
 374
 375 std::pair<unsigned, const TargetRegisterClass *>
 376 MSP430TargetLowering::getRegForInlineAsmConstraint(
 377     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
 378   if (Constraint.size() == 1) {
 379     // GCC Constraint Letters
 380     switch (Constraint[0]) {
 381     default: break;
 382     case 'r':   // GENERAL_REGS
 383       if (VT == MVT::i8)
 384         return std::make_pair(0U, &MSP430::GR8RegClass);
 385
 386       return std::make_pair(0U, &MSP430::GR16RegClass);
 387     }
 388   }
 389
 390   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 391 }
 392
 393 //===----------------------------------------------------------------------===//
 394 //                      Calling Convention Implementation
 395 //===----------------------------------------------------------------------===//
 396
 397 #include "MSP430GenCallingConv.inc"
 398
 399 /// For each argument in a function store the number of pieces it is composed
 400 /// of.
 401 template<typename ArgT>
 402 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
 403                               SmallVectorImpl<unsigned> &Out) {
 404   unsigned CurrentArgIndex;
 405
 406   if (Args.empty())
 407     return;
 408
 409   CurrentArgIndex = Args[0].OrigArgIndex;
 410   Out.push_back(0);
 411
 412   for (auto &Arg : Args) {
 413     if (CurrentArgIndex == Arg.OrigArgIndex) {
 414       Out.back() += 1;
 415     } else {
 416       Out.push_back(1);
 417       CurrentArgIndex = Arg.OrigArgIndex;
 418     }
 419   }
 420 }
 421
 422 static void AnalyzeVarArgs(CCState &State,
 423                            const SmallVectorImpl<ISD::OutputArg> &Outs) {
 424   State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
 425 }
 426
 427 static void AnalyzeVarArgs(CCState &State,
 428                            const SmallVectorImpl<ISD::InputArg> &Ins) {
 429   State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
 430 }
 431
 432 /// Analyze incoming and outgoing function arguments. We need custom C++ code
 433 /// to handle special constraints in the ABI like reversing the order of the
 434 /// pieces of splitted arguments. In addition, all pieces of a certain argument
 435 /// have to be passed either using registers or the stack but never mixing both.
 436 template<typename ArgT>
 437 static void AnalyzeArguments(CCState &State,
 438                              SmallVectorImpl<CCValAssign> &ArgLocs,
 439                              const SmallVectorImpl<ArgT> &Args) {
 440   static const MCPhysReg CRegList[] = {
 441     MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
 442   };
 443   static const unsigned CNbRegs = array_lengthof(CRegList);
 444   static const MCPhysReg BuiltinRegList[] = {
 445     MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
 446     MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
 447   };
 448   static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
 449
 450   ArrayRef<MCPhysReg> RegList;
 451   unsigned NbRegs;
 452
 453   bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
 454   if (Builtin) {
 455     RegList = BuiltinRegList;
 456     NbRegs = BuiltinNbRegs;
 457   } else {
 458     RegList = CRegList;
 459     NbRegs = CNbRegs;
 460   }
 461
 462   if (State.isVarArg()) {
 463     AnalyzeVarArgs(State, Args);
 464     return;
 465   }
 466
 467   SmallVector<unsigned, 4> ArgsParts;
 468   ParseFunctionArgs(Args, ArgsParts);
 469
 470   if (Builtin) {
 471     assert(ArgsParts.size() == 2 &&
 472         "Builtin calling convention requires two arguments");
 473   }
 474
 475   unsigned RegsLeft = NbRegs;
 476   bool UsedStack = false;
 477   unsigned ValNo = 0;
 478
 479   for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
 480     MVT ArgVT = Args[ValNo].VT;
 481     ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
 482     MVT LocVT = ArgVT;
 483     CCValAssign::LocInfo LocInfo = CCValAssign::Full;
 484
 485     // Promote i8 to i16
 486     if (LocVT == MVT::i8) {
 487       LocVT = MVT::i16;
 488       if (ArgFlags.isSExt())
 489           LocInfo = CCValAssign::SExt;
 490       else if (ArgFlags.isZExt())
 491           LocInfo = CCValAssign::ZExt;
 492       else
 493           LocInfo = CCValAssign::AExt;
 494     }
 495
 496     // Handle byval arguments
 497     if (ArgFlags.isByVal()) {
 498       State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
 499       continue;
 500     }
 501
 502     unsigned Parts = ArgsParts[i];
 503
 504     if (Builtin) {
 505       assert(Parts == 4 &&
 506           "Builtin calling convention requires 64-bit arguments");
 507     }
 508
 509     if (!UsedStack && Parts == 2 && RegsLeft == 1) {
 510       // Special case for 32-bit register split, see EABI section 3.3.3
 511       unsigned Reg = State.AllocateReg(RegList);
 512       State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
 513       RegsLeft -= 1;
 514
 515       UsedStack = true;
 516       CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
 517     } else if (Parts <= RegsLeft) {
 518       for (unsigned j = 0; j < Parts; j++) {
 519         unsigned Reg = State.AllocateReg(RegList);
 520         State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
 521         RegsLeft--;
 522       }
 523     } else {
 524       UsedStack = true;
 525       for (unsigned j = 0; j < Parts; j++)
 526         CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
 527     }
 528   }
 529 }
 530
 531 static void AnalyzeRetResult(CCState &State,
 532                              const SmallVectorImpl<ISD::InputArg> &Ins) {
 533   State.AnalyzeCallResult(Ins, RetCC_MSP430);
 534 }
 535
 536 static void AnalyzeRetResult(CCState &State,
 537                              const SmallVectorImpl<ISD::OutputArg> &Outs) {
 538   State.AnalyzeReturn(Outs, RetCC_MSP430);
 539 }
 540
 541 template<typename ArgT>
 542 static void AnalyzeReturnValues(CCState &State,
 543                                 SmallVectorImpl<CCValAssign> &RVLocs,
 544                                 const SmallVectorImpl<ArgT> &Args) {
 545   AnalyzeRetResult(State, Args);
 546 }
 547
 548 SDValue MSP430TargetLowering::LowerFormalArguments(
 549     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 550     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
 551     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 552
 553   switch (CallConv) {
 554   default:
 555     report_fatal_error("Unsupported calling convention");
 556   case CallingConv::C:
 557   case CallingConv::Fast:
 558     return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
 559   case CallingConv::MSP430_INTR:
 560     if (Ins.empty())
 561       return Chain;
 562     report_fatal_error("ISRs cannot have arguments");
 563   }
 564 }
 565
 566 SDValue
 567 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
 568                                 SmallVectorImpl<SDValue> &InVals) const {
 569   SelectionDAG &DAG                     = CLI.DAG;
 570   SDLoc &dl                             = CLI.DL;
 571   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
 572   SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
 573   SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
 574   SDValue Chain                         = CLI.Chain;
 575   SDValue Callee                        = CLI.Callee;
 576   bool &isTailCall                      = CLI.IsTailCall;
 577   CallingConv::ID CallConv              = CLI.CallConv;
 578   bool isVarArg                         = CLI.IsVarArg;
 579
 580   // MSP430 target does not yet support tail call optimization.
 581   isTailCall = false;
 582
 583   switch (CallConv) {
 584   default:
 585     report_fatal_error("Unsupported calling convention");
 586   case CallingConv::MSP430_BUILTIN:
 587   case CallingConv::Fast:
 588   case CallingConv::C:
 589     return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
 590                           Outs, OutVals, Ins, dl, DAG, InVals);
 591   case CallingConv::MSP430_INTR:
 592     report_fatal_error("ISRs cannot be called directly");
 593   }
 594 }
 595
 596 /// LowerCCCArguments - transform physical registers into virtual registers and
 597 /// generate load operations for arguments places on the stack.
 598 // FIXME: struct return stuff
 599 SDValue MSP430TargetLowering::LowerCCCArguments(
 600     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 601     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
 602     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 603   MachineFunction &MF = DAG.getMachineFunction();
 604   MachineFrameInfo &MFI = MF.getFrameInfo();
 605   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 606   MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
 607
 608   // Assign locations to all of the incoming arguments.
 609   SmallVector<CCValAssign, 16> ArgLocs;
 610   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
 611                  *DAG.getContext());
 612   AnalyzeArguments(CCInfo, ArgLocs, Ins);
 613
 614   // Create frame index for the start of the first vararg value
 615   if (isVarArg) {
 616     unsigned Offset = CCInfo.getNextStackOffset();
 617     FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true));
 618   }
 619
 620   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 621     CCValAssign &VA = ArgLocs[i];
 622     if (VA.isRegLoc()) {
 623       // Arguments passed in registers
 624       EVT RegVT = VA.getLocVT();
 625       switch (RegVT.getSimpleVT().SimpleTy) {
 626       default:
 627         {
 628 #ifndef NDEBUG
 629           errs() << "LowerFormalArguments Unhandled argument type: "
 630                << RegVT.getEVTString() << "\n";
 631 #endif
 632           llvm_unreachable(nullptr);
 633         }
 634       case MVT::i16:
 635         Register VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
 636         RegInfo.addLiveIn(VA.getLocReg(), VReg);
 637         SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
 638
 639         // If this is an 8-bit value, it is really passed promoted to 16
 640         // bits. Insert an assert[sz]ext to capture this, then truncate to the
 641         // right size.
 642         if (VA.getLocInfo() == CCValAssign::SExt)
 643           ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
 644                                  DAG.getValueType(VA.getValVT()));
 645         else if (VA.getLocInfo() == CCValAssign::ZExt)
 646           ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
 647                                  DAG.getValueType(VA.getValVT()));
 648
 649         if (VA.getLocInfo() != CCValAssign::Full)
 650           ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
 651
 652         InVals.push_back(ArgValue);
 653       }
 654     } else {
 655       // Sanity check
 656       assert(VA.isMemLoc());
 657
 658       SDValue InVal;
 659       ISD::ArgFlagsTy Flags = Ins[i].Flags;
 660
 661       if (Flags.isByVal()) {
 662         int FI = MFI.CreateFixedObject(Flags.getByValSize(),
 663                                        VA.getLocMemOffset(), true);
 664         InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
 665       } else {
 666         // Load the argument to a virtual register
 667         unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
 668         if (ObjSize > 2) {
 669             errs() << "LowerFormalArguments Unhandled argument type: "
 670                 << EVT(VA.getLocVT()).getEVTString()
 671                 << "\n";
 672         }
 673         // Create the frame index object for this incoming parameter...
 674         int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
 675
 676         // Create the SelectionDAG nodes corresponding to a load
 677         //from this parameter
 678         SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
 679         InVal = DAG.getLoad(
 680             VA.getLocVT(), dl, Chain, FIN,
 681             MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
 682       }
 683
 684       InVals.push_back(InVal);
 685     }
 686   }
 687
 688   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 689     if (Ins[i].Flags.isSRet()) {
 690       unsigned Reg = FuncInfo->getSRetReturnReg();
 691       if (!Reg) {
 692         Reg = MF.getRegInfo().createVirtualRegister(
 693             getRegClassFor(MVT::i16));
 694         FuncInfo->setSRetReturnReg(Reg);
 695       }
 696       SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
 697       Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
 698     }
 699   }
 700
 701   return Chain;
 702 }
 703
 704 bool
 705 MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
 706                                      MachineFunction &MF,
 707                                      bool IsVarArg,
 708                                      const SmallVectorImpl<ISD::OutputArg> &Outs,
 709                                      LLVMContext &Context) const {
 710   SmallVector<CCValAssign, 16> RVLocs;
 711   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
 712   return CCInfo.CheckReturn(Outs, RetCC_MSP430);
 713 }
 714
 715 SDValue
 716 MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
 717                                   bool isVarArg,
 718                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 719                                   const SmallVectorImpl<SDValue> &OutVals,
 720                                   const SDLoc &dl, SelectionDAG &DAG) const {
 721
 722   MachineFunction &MF = DAG.getMachineFunction();
 723
 724   // CCValAssign - represent the assignment of the return value to a location
 725   SmallVector<CCValAssign, 16> RVLocs;
 726
 727   // ISRs cannot return any value.
 728   if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
 729     report_fatal_error("ISRs cannot return any value");
 730
 731   // CCState - Info about the registers and stack slot.
 732   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
 733                  *DAG.getContext());
 734
 735   // Analize return values.
 736   AnalyzeReturnValues(CCInfo, RVLocs, Outs);
 737
 738   SDValue Flag;
 739   SmallVector<SDValue, 4> RetOps(1, Chain);
 740
 741   // Copy the result values into the output registers.
 742   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 743     CCValAssign &VA = RVLocs[i];
 744     assert(VA.isRegLoc() && "Can only return in registers!");
 745
 746     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
 747                              OutVals[i], Flag);
 748
 749     // Guarantee that all emitted copies are stuck together,
 750     // avoiding something bad.
 751     Flag = Chain.getValue(1);
 752     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
 753   }
 754
 755   if (MF.getFunction().hasStructRetAttr()) {
 756     MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
 757     unsigned Reg = FuncInfo->getSRetReturnReg();
 758
 759     if (!Reg)
 760       llvm_unreachable("sret virtual register not created in entry block");
 761
 762     SDValue Val =
 763       DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));
 764     unsigned R12 = MSP430::R12;
 765
 766     Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);
 767     Flag = Chain.getValue(1);
 768     RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout())));
 769   }
 770
 771   unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
 772                   MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
 773
 774   RetOps[0] = Chain;  // Update chain.
 775
 776   // Add the flag if we have it.
 777   if (Flag.getNode())
 778     RetOps.push_back(Flag);
 779
 780   return DAG.getNode(Opc, dl, MVT::Other, RetOps);
 781 }
 782
 783 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
 784 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
 785 SDValue MSP430TargetLowering::LowerCCCCallTo(
 786     SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
 787     bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
 788     const SmallVectorImpl<SDValue> &OutVals,
 789     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
 790     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 791   // Analyze operands of the call, assigning locations to each operand.
 792   SmallVector<CCValAssign, 16> ArgLocs;
 793   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
 794                  *DAG.getContext());
 795   AnalyzeArguments(CCInfo, ArgLocs, Outs);
 796
 797   // Get a count of how many bytes are to be pushed on the stack.
 798   unsigned NumBytes = CCInfo.getNextStackOffset();
 799   auto PtrVT = getPointerTy(DAG.getDataLayout());
 800
 801   Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
 802
 803   SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
 804   SmallVector<SDValue, 12> MemOpChains;
 805   SDValue StackPtr;
 806
 807   // Walk the register/memloc assignments, inserting copies/loads.
 808   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 809     CCValAssign &VA = ArgLocs[i];
 810
 811     SDValue Arg = OutVals[i];
 812
 813     // Promote the value if needed.
 814     switch (VA.getLocInfo()) {
 815       default: llvm_unreachable("Unknown loc info!");
 816       case CCValAssign::Full: break;
 817       case CCValAssign::SExt:
 818         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
 819         break;
 820       case CCValAssign::ZExt:
 821         Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
 822         break;
 823       case CCValAssign::AExt:
 824         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
 825         break;
 826     }
 827
 828     // Arguments that can be passed on register must be kept at RegsToPass
 829     // vector
 830     if (VA.isRegLoc()) {
 831       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
 832     } else {
 833       assert(VA.isMemLoc());
 834
 835       if (!StackPtr.getNode())
 836         StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
 837
 838       SDValue PtrOff =
 839           DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
 840                       DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
 841
 842       SDValue MemOp;
 843       ISD::ArgFlagsTy Flags = Outs[i].Flags;
 844
 845       if (Flags.isByVal()) {
 846         SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
 847         MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
 848                               Flags.getByValAlign(),
 849                               /*isVolatile*/false,
 850                               /*AlwaysInline=*/true,
 851                               /*isTailCall=*/false,
 852                               MachinePointerInfo(),
 853                               MachinePointerInfo());
 854       } else {
 855         MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
 856       }
 857
 858       MemOpChains.push_back(MemOp);
 859     }
 860   }
 861
 862   // Transform all store nodes into one single node because all store nodes are
 863   // independent of each other.
 864   if (!MemOpChains.empty())
 865     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
 866
 867   // Build a sequence of copy-to-reg nodes chained together with token chain and
 868   // flag operands which copy the outgoing args into registers.  The InFlag in
 869   // necessary since all emitted instructions must be stuck together.
 870   SDValue InFlag;
 871   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
 872     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
 873                              RegsToPass[i].second, InFlag);
 874     InFlag = Chain.getValue(1);
 875   }
 876
 877   // If the callee is a GlobalAddress node (quite common, every direct call is)
 878   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
 879   // Likewise ExternalSymbol -> TargetExternalSymbol.
 880   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
 881     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
 882   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
 883     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
 884
 885   // Returns a chain & a flag for retval copy to use.
 886   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
 887   SmallVector<SDValue, 8> Ops;
 888   Ops.push_back(Chain);
 889   Ops.push_back(Callee);
 890
 891   // Add argument registers to the end of the list so that they are
 892   // known live into the call.
 893   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
 894     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
 895                                   RegsToPass[i].second.getValueType()));
 896
 897   if (InFlag.getNode())
 898     Ops.push_back(InFlag);
 899
 900   Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
 901   InFlag = Chain.getValue(1);
 902
 903   // Create the CALLSEQ_END node.
 904   Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
 905                              DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
 906   InFlag = Chain.getValue(1);
 907
 908   // Handle result values, copying them out of physregs into vregs that we
 909   // return.
 910   return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
 911                          DAG, InVals);
 912 }
 913
 914 /// LowerCallResult - Lower the result values of a call into the
 915 /// appropriate copies out of appropriate physical registers.
 916 ///
 917 SDValue MSP430TargetLowering::LowerCallResult(
 918     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
 919     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
 920     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 921
 922   // Assign locations to each value returned by this call.
 923   SmallVector<CCValAssign, 16> RVLocs;
 924   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
 925                  *DAG.getContext());
 926
 927   AnalyzeReturnValues(CCInfo, RVLocs, Ins);
 928
 929   // Copy all of the result registers out of their specified physreg.
 930   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 931     Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
 932                                RVLocs[i].getValVT(), InFlag).getValue(1);
 933     InFlag = Chain.getValue(2);
 934     InVals.push_back(Chain.getValue(0));
 935   }
 936
 937   return Chain;
 938 }
 939
 940 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
 941                                           SelectionDAG &DAG) const {
 942   unsigned Opc = Op.getOpcode();
 943   SDNode* N = Op.getNode();
 944   EVT VT = Op.getValueType();
 945   SDLoc dl(N);
 946
 947   // Expand non-constant shifts to loops:
 948   if (!isa<ConstantSDNode>(N->getOperand(1)))
 949     return Op;
 950
 951   uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
 952
 953   // Expand the stuff into sequence of shifts.
 954   SDValue Victim = N->getOperand(0);
 955
 956   if (ShiftAmount >= 8) {
 957     assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");
 958     switch(Opc) {
 959     default:
 960       llvm_unreachable("Unknown shift");
 961     case ISD::SHL:
 962       // foo << (8 + N) => swpb(zext(foo)) << N
 963       Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
 964       Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
 965       break;
 966     case ISD::SRA:
 967     case ISD::SRL:
 968       // foo >> (8 + N) => sxt(swpb(foo)) >> N
 969       Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
 970       Victim = (Opc == ISD::SRA)
 971                    ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
 972                                  DAG.getValueType(MVT::i8))
 973                    : DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
 974       break;
 975     }
 976     ShiftAmount -= 8;
 977   }
 978
 979   if (Opc == ISD::SRL && ShiftAmount) {
 980     // Emit a special goodness here:
 981     // srl A, 1 => clrc; rrc A
 982     Victim = DAG.getNode(MSP430ISD::RRCL, dl, VT, Victim);
 983     ShiftAmount -= 1;
 984   }
 985
 986   while (ShiftAmount--)
 987     Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
 988                          dl, VT, Victim);
 989
 990   return Victim;
 991 }
 992
 993 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
 994                                                  SelectionDAG &DAG) const {
 995   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
 996   int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
 997   auto PtrVT = getPointerTy(DAG.getDataLayout());
 998
 999   // Create the TargetGlobalAddress node, folding in the constant offset.
1000   SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
1001   return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
1002 }
1003
1004 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
1005                                                   SelectionDAG &DAG) const {
1006   SDLoc dl(Op);
1007   const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
1008   auto PtrVT = getPointerTy(DAG.getDataLayout());
1009   SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
1010
1011   return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1012 }
1013
1014 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
1015                                                 SelectionDAG &DAG) const {
1016   SDLoc dl(Op);
1017   auto PtrVT = getPointerTy(DAG.getDataLayout());
1018   const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1019   SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
1020
1021   return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1022 }
1023
1024 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
1025                        ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) {
1026   // FIXME: Handle bittests someday
1027   assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
1028
1029   // FIXME: Handle jump negative someday
1030   MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
1031   switch (CC) {
1032   default: llvm_unreachable("Invalid integer condition!");
1033   case ISD::SETEQ:
1034     TCC = MSP430CC::COND_E;     // aka COND_Z
1035     // Minor optimization: if LHS is a constant, swap operands, then the
1036     // constant can be folded into comparison.
1037     if (LHS.getOpcode() == ISD::Constant)
1038       std::swap(LHS, RHS);
1039     break;
1040   case ISD::SETNE:
1041     TCC = MSP430CC::COND_NE;    // aka COND_NZ
1042     // Minor optimization: if LHS is a constant, swap operands, then the
1043     // constant can be folded into comparison.
1044     if (LHS.getOpcode() == ISD::Constant)
1045       std::swap(LHS, RHS);
1046     break;
1047   case ISD::SETULE:
1048     std::swap(LHS, RHS);
1049     LLVM_FALLTHROUGH;
1050   case ISD::SETUGE:
1051     // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
1052     // fold constant into instruction.
1053     if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1054       LHS = RHS;
1055       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1056       TCC = MSP430CC::COND_LO;
1057       break;
1058     }
1059     TCC = MSP430CC::COND_HS;    // aka COND_C
1060     break;
1061   case ISD::SETUGT:
1062     std::swap(LHS, RHS);
1063     LLVM_FALLTHROUGH;
1064   case ISD::SETULT:
1065     // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
1066     // fold constant into instruction.
1067     if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1068       LHS = RHS;
1069       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1070       TCC = MSP430CC::COND_HS;
1071       break;
1072     }
1073     TCC = MSP430CC::COND_LO;    // aka COND_NC
1074     break;
1075   case ISD::SETLE:
1076     std::swap(LHS, RHS);
1077     LLVM_FALLTHROUGH;
1078   case ISD::SETGE:
1079     // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
1080     // fold constant into instruction.
1081     if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1082       LHS = RHS;
1083       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1084       TCC = MSP430CC::COND_L;
1085       break;
1086     }
1087     TCC = MSP430CC::COND_GE;
1088     break;
1089   case ISD::SETGT:
1090     std::swap(LHS, RHS);
1091     LLVM_FALLTHROUGH;
1092   case ISD::SETLT:
1093     // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
1094     // fold constant into instruction.
1095     if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1096       LHS = RHS;
1097       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1098       TCC = MSP430CC::COND_GE;
1099       break;
1100     }
1101     TCC = MSP430CC::COND_L;
1102     break;
1103   }
1104
1105   TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
1106   return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
1107 }
1108
1109
1110 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1111   SDValue Chain = Op.getOperand(0);
1112   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1113   SDValue LHS   = Op.getOperand(2);
1114   SDValue RHS   = Op.getOperand(3);
1115   SDValue Dest  = Op.getOperand(4);
1116   SDLoc dl  (Op);
1117
1118   SDValue TargetCC;
1119   SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1120
1121   return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1122                      Chain, Dest, TargetCC, Flag);
1123 }
1124
1125 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1126   SDValue LHS   = Op.getOperand(0);
1127   SDValue RHS   = Op.getOperand(1);
1128   SDLoc dl  (Op);
1129
1130   // If we are doing an AND and testing against zero, then the CMP
1131   // will not be generated.  The AND (or BIT) will generate the condition codes,
1132   // but they are different from CMP.
1133   // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
1134   // lowering & isel wouldn't diverge.
1135   bool andCC = false;
1136   if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1137     if (RHSC->isNullValue() && LHS.hasOneUse() &&
1138         (LHS.getOpcode() == ISD::AND ||
1139          (LHS.getOpcode() == ISD::TRUNCATE &&
1140           LHS.getOperand(0).getOpcode() == ISD::AND))) {
1141       andCC = true;
1142     }
1143   }
1144   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1145   SDValue TargetCC;
1146   SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1147
1148   // Get the condition codes directly from the status register, if its easy.
1149   // Otherwise a branch will be generated.  Note that the AND and BIT
1150   // instructions generate different flags than CMP, the carry bit can be used
1151   // for NE/EQ.
1152   bool Invert = false;
1153   bool Shift = false;
1154   bool Convert = true;
1155   switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1156    default:
1157     Convert = false;
1158     break;
1159    case MSP430CC::COND_HS:
1160      // Res = SR & 1, no processing is required
1161      break;
1162    case MSP430CC::COND_LO:
1163      // Res = ~(SR & 1)
1164      Invert = true;
1165      break;
1166    case MSP430CC::COND_NE:
1167      if (andCC) {
1168        // C = ~Z, thus Res = SR & 1, no processing is required
1169      } else {
1170        // Res = ~((SR >> 1) & 1)
1171        Shift = true;
1172        Invert = true;
1173      }
1174      break;
1175    case MSP430CC::COND_E:
1176      Shift = true;
1177      // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
1178      // Res = (SR >> 1) & 1 is 1 word shorter.
1179      break;
1180   }
1181   EVT VT = Op.getValueType();
1182   SDValue One  = DAG.getConstant(1, dl, VT);
1183   if (Convert) {
1184     SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
1185                                     MVT::i16, Flag);
1186     if (Shift)
1187       // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
1188       SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1189     SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
1190     if (Invert)
1191       SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
1192     return SR;
1193   } else {
1194     SDValue Zero = DAG.getConstant(0, dl, VT);
1195     SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1196     SDValue Ops[] = {One, Zero, TargetCC, Flag};
1197     return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1198   }
1199 }
1200
1201 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
1202                                              SelectionDAG &DAG) const {
1203   SDValue LHS    = Op.getOperand(0);
1204   SDValue RHS    = Op.getOperand(1);
1205   SDValue TrueV  = Op.getOperand(2);
1206   SDValue FalseV = Op.getOperand(3);
1207   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1208   SDLoc dl   (Op);
1209
1210   SDValue TargetCC;
1211   SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1212
1213   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1214   SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1215
1216   return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1217 }
1218
1219 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
1220                                                SelectionDAG &DAG) const {
1221   SDValue Val = Op.getOperand(0);
1222   EVT VT      = Op.getValueType();
1223   SDLoc dl(Op);
1224
1225   assert(VT == MVT::i16 && "Only support i16 for now!");
1226
1227   return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1228                      DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1229                      DAG.getValueType(Val.getValueType()));
1230 }
1231
1232 SDValue
1233 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
1234   MachineFunction &MF = DAG.getMachineFunction();
1235   MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1236   int ReturnAddrIndex = FuncInfo->getRAIndex();
1237   auto PtrVT = getPointerTy(MF.getDataLayout());
1238
1239   if (ReturnAddrIndex == 0) {
1240     // Set up a frame object for the return address.
1241     uint64_t SlotSize = MF.getDataLayout().getPointerSize();
1242     ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize,
1243                                                            true);
1244     FuncInfo->setRAIndex(ReturnAddrIndex);
1245   }
1246
1247   return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1248 }
1249
1250 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
1251                                               SelectionDAG &DAG) const {
1252   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1253   MFI.setReturnAddressIsTaken(true);
1254
1255   if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1256     return SDValue();
1257
1258   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1259   SDLoc dl(Op);
1260   auto PtrVT = getPointerTy(DAG.getDataLayout());
1261
1262   if (Depth > 0) {
1263     SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1264     SDValue Offset =
1265         DAG.getConstant(DAG.getDataLayout().getPointerSize(), dl, MVT::i16);
1266     return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1267                        DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1268                        MachinePointerInfo());
1269   }
1270
1271   // Just load the return address.
1272   SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1273   return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1274                      MachinePointerInfo());
1275 }
1276
1277 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
1278                                              SelectionDAG &DAG) const {
1279   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1280   MFI.setFrameAddressIsTaken(true);
1281
1282   EVT VT = Op.getValueType();
1283   SDLoc dl(Op);  // FIXME probably not meaningful
1284   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1285   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1286                                          MSP430::FP, VT);
1287   while (Depth--)
1288     FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1289                             MachinePointerInfo());
1290   return FrameAddr;
1291 }
1292
1293 SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
1294                                            SelectionDAG &DAG) const {
1295   MachineFunction &MF = DAG.getMachineFunction();
1296   MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1297   auto PtrVT = getPointerTy(DAG.getDataLayout());
1298
1299   // Frame index of first vararg argument
1300   SDValue FrameIndex =
1301       DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1302   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1303
1304   // Create a store of the frame index to the location operand
1305   return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1),
1306                       MachinePointerInfo(SV));
1307 }
1308
1309 SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op,
1310                                              SelectionDAG &DAG) const {
1311     JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1312     auto PtrVT = getPointerTy(DAG.getDataLayout());
1313     SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1314     return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1315 }
1316
1317 /// getPostIndexedAddressParts - returns true by value, base pointer and
1318 /// offset pointer and addressing mode by reference if this node can be
1319 /// combined with a load / store to form a post-indexed load / store.
1320 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1321                                                       SDValue &Base,
1322                                                       SDValue &Offset,
1323                                                       ISD::MemIndexedMode &AM,
1324                                                       SelectionDAG &DAG) const {
1325
1326   LoadSDNode *LD = cast<LoadSDNode>(N);
1327   if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1328     return false;
1329
1330   EVT VT = LD->getMemoryVT();
1331   if (VT != MVT::i8 && VT != MVT::i16)
1332     return false;
1333
1334   if (Op->getOpcode() != ISD::ADD)
1335     return false;
1336
1337   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1338     uint64_t RHSC = RHS->getZExtValue();
1339     if ((VT == MVT::i16 && RHSC != 2) ||
1340         (VT == MVT::i8 && RHSC != 1))
1341       return false;
1342
1343     Base = Op->getOperand(0);
1344     Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1345     AM = ISD::POST_INC;
1346     return true;
1347   }
1348
1349   return false;
1350 }
1351
1352
1353 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1354   switch ((MSP430ISD::NodeType)Opcode) {
1355   case MSP430ISD::FIRST_NUMBER:       break;
1356   case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
1357   case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
1358   case MSP430ISD::RRA:                return "MSP430ISD::RRA";
1359   case MSP430ISD::RLA:                return "MSP430ISD::RLA";
1360   case MSP430ISD::RRC:                return "MSP430ISD::RRC";
1361   case MSP430ISD::RRCL:               return "MSP430ISD::RRCL";
1362   case MSP430ISD::CALL:               return "MSP430ISD::CALL";
1363   case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
1364   case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
1365   case MSP430ISD::CMP:                return "MSP430ISD::CMP";
1366   case MSP430ISD::SETCC:              return "MSP430ISD::SETCC";
1367   case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
1368   case MSP430ISD::DADD:               return "MSP430ISD::DADD";
1369   }
1370   return nullptr;
1371 }
1372
1373 bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1374                                           Type *Ty2) const {
1375   if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1376     return false;
1377
1378   return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1379 }
1380
1381 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1382   if (!VT1.isInteger() || !VT2.isInteger())
1383     return false;
1384
1385   return (VT1.getSizeInBits() > VT2.getSizeInBits());
1386 }
1387
1388 bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1389   // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1390   return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1391 }
1392
1393 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1394   // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1395   return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1396 }
1397
1398 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1399   return isZExtFree(Val.getValueType(), VT2);
1400 }
1401
1402 //===----------------------------------------------------------------------===//
1403 //  Other Lowering Code
1404 //===----------------------------------------------------------------------===//
1405
1406 MachineBasicBlock *
1407 MSP430TargetLowering::EmitShiftInstr(MachineInstr &MI,
1408                                      MachineBasicBlock *BB) const {
1409   MachineFunction *F = BB->getParent();
1410   MachineRegisterInfo &RI = F->getRegInfo();
1411   DebugLoc dl = MI.getDebugLoc();
1412   const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1413
1414   unsigned Opc;
1415   bool ClearCarry = false;
1416   const TargetRegisterClass * RC;
1417   switch (MI.getOpcode()) {
1418   default: llvm_unreachable("Invalid shift opcode!");
1419   case MSP430::Shl8:
1420     Opc = MSP430::ADD8rr;
1421     RC = &MSP430::GR8RegClass;
1422     break;
1423   case MSP430::Shl16:
1424     Opc = MSP430::ADD16rr;
1425     RC = &MSP430::GR16RegClass;
1426     break;
1427   case MSP430::Sra8:
1428     Opc = MSP430::RRA8r;
1429     RC = &MSP430::GR8RegClass;
1430     break;
1431   case MSP430::Sra16:
1432     Opc = MSP430::RRA16r;
1433     RC = &MSP430::GR16RegClass;
1434     break;
1435   case MSP430::Srl8:
1436     ClearCarry = true;
1437     Opc = MSP430::RRC8r;
1438     RC = &MSP430::GR8RegClass;
1439     break;
1440   case MSP430::Srl16:
1441     ClearCarry = true;
1442     Opc = MSP430::RRC16r;
1443     RC = &MSP430::GR16RegClass;
1444     break;
1445   case MSP430::Rrcl8:
1446   case MSP430::Rrcl16: {
1447     BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1448       .addReg(MSP430::SR).addImm(1);
1449     Register SrcReg = MI.getOperand(1).getReg();
1450     Register DstReg = MI.getOperand(0).getReg();
1451     unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16
1452                     ? MSP430::RRC16r : MSP430::RRC8r;
1453     BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1454       .addReg(SrcReg);
1455     MI.eraseFromParent(); // The pseudo instruction is gone now.
1456     return BB;
1457   }
1458   }
1459
1460   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1461   MachineFunction::iterator I = ++BB->getIterator();
1462
1463   // Create loop block
1464   MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1465   MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1466
1467   F->insert(I, LoopBB);
1468   F->insert(I, RemBB);
1469
1470   // Update machine-CFG edges by transferring all successors of the current
1471   // block to the block containing instructions after shift.
1472   RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1473                 BB->end());
1474   RemBB->transferSuccessorsAndUpdatePHIs(BB);
1475
1476   // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1477   BB->addSuccessor(LoopBB);
1478   BB->addSuccessor(RemBB);
1479   LoopBB->addSuccessor(RemBB);
1480   LoopBB->addSuccessor(LoopBB);
1481
1482   Register ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1483   Register ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1484   Register ShiftReg = RI.createVirtualRegister(RC);
1485   Register ShiftReg2 = RI.createVirtualRegister(RC);
1486   Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1487   Register SrcReg = MI.getOperand(1).getReg();
1488   Register DstReg = MI.getOperand(0).getReg();
1489
1490   // BB:
1491   // cmp 0, N
1492   // je RemBB
1493   BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1494     .addReg(ShiftAmtSrcReg).addImm(0);
1495   BuildMI(BB, dl, TII.get(MSP430::JCC))
1496     .addMBB(RemBB)
1497     .addImm(MSP430CC::COND_E);
1498
1499   // LoopBB:
1500   // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1501   // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1502   // ShiftReg2 = shift ShiftReg
1503   // ShiftAmt2 = ShiftAmt - 1;
1504   BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1505     .addReg(SrcReg).addMBB(BB)
1506     .addReg(ShiftReg2).addMBB(LoopBB);
1507   BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1508     .addReg(ShiftAmtSrcReg).addMBB(BB)
1509     .addReg(ShiftAmtReg2).addMBB(LoopBB);
1510   if (ClearCarry)
1511     BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1512       .addReg(MSP430::SR).addImm(1);
1513   if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1514     BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1515       .addReg(ShiftReg)
1516       .addReg(ShiftReg);
1517   else
1518     BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1519       .addReg(ShiftReg);
1520   BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1521     .addReg(ShiftAmtReg).addImm(1);
1522   BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1523     .addMBB(LoopBB)
1524     .addImm(MSP430CC::COND_NE);
1525
1526   // RemBB:
1527   // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1528   BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1529     .addReg(SrcReg).addMBB(BB)
1530     .addReg(ShiftReg2).addMBB(LoopBB);
1531
1532   MI.eraseFromParent(); // The pseudo instruction is gone now.
1533   return RemBB;
1534 }
1535
1536 MachineBasicBlock *
1537 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1538                                                   MachineBasicBlock *BB) const {
1539   unsigned Opc = MI.getOpcode();
1540
1541   if (Opc == MSP430::Shl8  || Opc == MSP430::Shl16 ||
1542       Opc == MSP430::Sra8  || Opc == MSP430::Sra16 ||
1543       Opc == MSP430::Srl8  || Opc == MSP430::Srl16 ||
1544       Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1545     return EmitShiftInstr(MI, BB);
1546
1547   const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1548   DebugLoc dl = MI.getDebugLoc();
1549
1550   assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1551          "Unexpected instr type to insert");
1552
1553   // To "insert" a SELECT instruction, we actually have to insert the diamond
1554   // control-flow pattern.  The incoming instruction knows the destination vreg
1555   // to set, the condition code register to branch on, the true/false values to
1556   // select between, and a branch opcode to use.
1557   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1558   MachineFunction::iterator I = ++BB->getIterator();
1559
1560   //  thisMBB:
1561   //  ...
1562   //   TrueVal = ...
1563   //   cmpTY ccX, r1, r2
1564   //   jCC copy1MBB
1565   //   fallthrough --> copy0MBB
1566   MachineBasicBlock *thisMBB = BB;
1567   MachineFunction *F = BB->getParent();
1568   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1569   MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1570   F->insert(I, copy0MBB);
1571   F->insert(I, copy1MBB);
1572   // Update machine-CFG edges by transferring all successors of the current
1573   // block to the new block which will contain the Phi node for the select.
1574   copy1MBB->splice(copy1MBB->begin(), BB,
1575                    std::next(MachineBasicBlock::iterator(MI)), BB->end());
1576   copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1577   // Next, add the true and fallthrough blocks as its successors.
1578   BB->addSuccessor(copy0MBB);
1579   BB->addSuccessor(copy1MBB);
1580
1581   BuildMI(BB, dl, TII.get(MSP430::JCC))
1582       .addMBB(copy1MBB)
1583       .addImm(MI.getOperand(3).getImm());
1584
1585   //  copy0MBB:
1586   //   %FalseValue = ...
1587   //   # fallthrough to copy1MBB
1588   BB = copy0MBB;
1589
1590   // Update machine-CFG edges
1591   BB->addSuccessor(copy1MBB);
1592
1593   //  copy1MBB:
1594   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1595   //  ...
1596   BB = copy1MBB;
1597   BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1598       .addReg(MI.getOperand(2).getReg())
1599       .addMBB(copy0MBB)
1600       .addReg(MI.getOperand(1).getReg())
1601       .addMBB(thisMBB);
1602
1603   MI.eraseFromParent(); // The pseudo instruction is gone now.
1604   return BB;
1605 }