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[AMDGPU] Check for immediate SrcC in mfma in AsmParser
[llvm-core.git] / lib / Target / Mips / Disassembler / MipsDisassembler.cpp
blobef13507fe63a6253c7e21421704ce9bb1bd96ece
1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the Mips Disassembler.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/MipsMCTargetDesc.h"
14 #include "Mips.h"
15 #include "TargetInfo/MipsTargetInfo.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/Compiler.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include <cassert>
30 #include <cstdint>
31
32 using namespace llvm;
33
34 #define DEBUG_TYPE "mips-disassembler"
35
36 using DecodeStatus = MCDisassembler::DecodeStatus;
37
38 namespace {
39
40 class MipsDisassembler : public MCDisassembler {
41 bool IsMicroMips;
42 bool IsBigEndian;
43
44 public:
45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
46 : MCDisassembler(STI, Ctx),
47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
48 IsBigEndian(IsBigEndian) {}
49
50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
53
54 bool hasMips32r6() const {
55 return STI.getFeatureBits()[Mips::FeatureMips32r6];
56 }
57
58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
59
60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
61
62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
63
64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
65
66 bool hasCOP3() const {
67 // Only present in MIPS-I and MIPS-II
68 return !hasMips32() && !hasMips3();
69 }
70
71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
72 ArrayRef<uint8_t> Bytes, uint64_t Address,
73 raw_ostream &VStream,
74 raw_ostream &CStream) const override;
75 };
76
77 } // end anonymous namespace
78
79 // Forward declare these because the autogenerated code will reference them.
80 // Definitions are further down.
81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
82 unsigned RegNo,
83 uint64_t Address,
84 const void *Decoder);
85
86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
87 unsigned RegNo,
88 uint64_t Address,
89 const void *Decoder);
90
91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
92 unsigned RegNo,
93 uint64_t Address,
94 const void *Decoder);
95
96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
97 unsigned RegNo,
98 uint64_t Address,
99 const void *Decoder);
100
101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
102 unsigned RegNo,
103 uint64_t Address,
104 const void *Decoder);
105
106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
107 unsigned RegNo,
108 uint64_t Address,
109 const void *Decoder);
110
111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
112 unsigned Insn,
113 uint64_t Address,
114 const void *Decoder);
115
116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
117 unsigned RegNo,
118 uint64_t Address,
119 const void *Decoder);
120
121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
122 unsigned RegNo,
123 uint64_t Address,
124 const void *Decoder);
125
126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
127 unsigned RegNo,
128 uint64_t Address,
129 const void *Decoder);
130
131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
132 unsigned RegNo,
133 uint64_t Address,
134 const void *Decoder);
135
136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
137 unsigned RegNo,
138 uint64_t Address,
139 const void *Decoder);
140
141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
142 uint64_t Address,
143 const void *Decoder);
144
145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
146 unsigned Insn,
147 uint64_t Address,
148 const void *Decoder);
149
150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
151 unsigned RegNo,
152 uint64_t Address,
153 const void *Decoder);
154
155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
156 unsigned RegNo,
157 uint64_t Address,
158 const void *Decoder);
159
160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
161 unsigned RegNo,
162 uint64_t Address,
163 const void *Decoder);
164
165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
166 unsigned RegNo,
167 uint64_t Address,
168 const void *Decoder);
169
170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
171 unsigned RegNo,
172 uint64_t Address,
173 const void *Decoder);
174
175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
176 unsigned RegNo,
177 uint64_t Address,
178 const void *Decoder);
179
180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
181 unsigned RegNo,
182 uint64_t Address,
183 const void *Decoder);
184
185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
186 unsigned RegNo,
187 uint64_t Address,
188 const void *Decoder);
189
190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
191 unsigned RegNo,
192 uint64_t Address,
193 const void *Decoder);
194
195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
196 unsigned RegNo,
197 uint64_t Address,
198 const void *Decoder);
199
200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
201 unsigned RegNo,
202 uint64_t Address,
203 const void *Decoder);
204
205 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
206 unsigned Offset,
207 uint64_t Address,
208 const void *Decoder);
209
210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
211 unsigned Offset,
212 uint64_t Address,
213 const void *Decoder);
214
215 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
216 unsigned Insn,
217 uint64_t Address,
218 const void *Decoder);
219
220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
221 unsigned Offset,
222 uint64_t Address,
223 const void *Decoder);
224
225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
226 unsigned Offset,
227 uint64_t Address,
228 const void *Decoder);
229
230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
231 unsigned Offset,
232 uint64_t Address,
233 const void *Decoder);
234
235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
236 // shifted left by 1 bit.
237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
238 unsigned Offset,
239 uint64_t Address,
240 const void *Decoder);
241
242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
243 // shifted left by 1 bit.
244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
245 unsigned Offset,
246 uint64_t Address,
247 const void *Decoder);
248
249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
250 // shifted left by 1 bit.
251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
252 unsigned Offset,
253 uint64_t Address,
254 const void *Decoder);
255
256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
257 // shifted left by 1 bit.
258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
259 unsigned Offset,
260 uint64_t Address,
261 const void *Decoder);
262
263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
264 // shifted left by 1 bit.
265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
266 unsigned Insn,
267 uint64_t Address,
268 const void *Decoder);
269
270 static DecodeStatus DecodeMem(MCInst &Inst,
271 unsigned Insn,
272 uint64_t Address,
273 const void *Decoder);
274
275 static DecodeStatus DecodeMemEVA(MCInst &Inst,
276 unsigned Insn,
277 uint64_t Address,
278 const void *Decoder);
279
280 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
281 unsigned Insn,
282 uint64_t Address,
283 const void *Decoder);
284
285 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
286 const void *Decoder);
287
288 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
289 unsigned Insn,
290 uint64_t Address,
291 const void *Decoder);
292
293 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
294 unsigned Insn,
295 uint64_t Address,
296 const void *Decoder);
297
298 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
299 unsigned Insn,
300 uint64_t Address,
301 const void *Decoder);
302
303 static DecodeStatus DecodeSyncI(MCInst &Inst,
304 unsigned Insn,
305 uint64_t Address,
306 const void *Decoder);
307
308 static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
309 unsigned Insn,
310 uint64_t Address,
311 const void *Decoder);
312
313 static DecodeStatus DecodeSynciR6(MCInst &Inst,
314 unsigned Insn,
315 uint64_t Address,
316 const void *Decoder);
317
318 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320
321 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
322 unsigned Insn,
323 uint64_t Address,
324 const void *Decoder);
325
326 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
327 unsigned Insn,
328 uint64_t Address,
329 const void *Decoder);
330
331 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
332 unsigned Insn,
333 uint64_t Address,
334 const void *Decoder);
335
336 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
337 unsigned Insn,
338 uint64_t Address,
339 const void *Decoder);
340
341 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
342 unsigned Insn,
343 uint64_t Address,
344 const void *Decoder);
345
346 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
347 unsigned Insn,
348 uint64_t Address,
349 const void *Decoder);
350
351 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
352 unsigned Insn,
353 uint64_t Address,
354 const void *Decoder);
355
356 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
357 uint64_t Address,
358 const void *Decoder);
359
360 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
361 uint64_t Address,
362 const void *Decoder);
363
364 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
365 const void *Decoder);
366
367 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
368 const void *Decoder);
369
370 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
372
373 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
374 uint64_t Address,
375 const void *Decoder);
376
377 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
378 unsigned Insn,
379 uint64_t Address,
380 const void *Decoder);
381
382 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
383 unsigned Value,
384 uint64_t Address,
385 const void *Decoder);
386
387 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
388 unsigned Value,
389 uint64_t Address,
390 const void *Decoder);
391
392 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
393 unsigned Value,
394 uint64_t Address,
395 const void *Decoder);
396
397 template <unsigned Bits, int Offset, int Scale>
398 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
399 uint64_t Address,
400 const void *Decoder);
401
402 template <unsigned Bits, int Offset>
403 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
404 uint64_t Address,
405 const void *Decoder) {
406 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
407 Decoder);
408 }
409
410 template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
411 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
412 uint64_t Address,
413 const void *Decoder);
414
415 static DecodeStatus DecodeInsSize(MCInst &Inst,
416 unsigned Insn,
417 uint64_t Address,
418 const void *Decoder);
419
420 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
421 uint64_t Address, const void *Decoder);
422
423 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
424 uint64_t Address, const void *Decoder);
425
426 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
427 uint64_t Address, const void *Decoder);
428
429 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
430 uint64_t Address, const void *Decoder);
431
432 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
433 uint64_t Address, const void *Decoder);
434
435 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
436 /// handle.
437 template <typename InsnType>
438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
439 const void *Decoder);
440
441 template <typename InsnType>
442 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
443 const void *Decoder);
444
445 template <typename InsnType>
446 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
447 const void *Decoder);
448
449 template <typename InsnType>
450 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
451 const void *Decoder);
452
453 template <typename InsnType>
454 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
455 const void *Decoder);
456
457 template <typename InsnType>
458 static DecodeStatus
459 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
460 const void *Decoder);
461
462 template <typename InsnType>
463 static DecodeStatus
464 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
465 const void *Decoder);
466
467 template <typename InsnType>
468 static DecodeStatus
469 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
470 const void *Decoder);
471
472 template <typename InsnType>
473 static DecodeStatus
474 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
475 const void *Decoder);
476
477 template <typename InsnType>
478 static DecodeStatus
479 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
480 const void *Decoder);
481
482 template <typename InsnType>
483 static DecodeStatus
484 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
485 const void *Decoder);
486
487 template <typename InsnType>
488 static DecodeStatus
489 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
490 const void *Decoder);
491
492 template <typename InsnType>
493 static DecodeStatus
494 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
495 const void *Decoder);
496
497 template <typename InsnType>
498 static DecodeStatus
499 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
500 const void *Decoder);
501
502 template <typename InsnType>
503 static DecodeStatus
504 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
505 const void *Decoder);
506
507 template <typename InsnType>
508 static DecodeStatus
509 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
510 const void *Decoder);
511
512 template <typename InsnType>
513 static DecodeStatus
514 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
515 const void *Decoder);
516
517 template <typename InsnType>
518 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
519 const void *Decoder);
520
521 template <typename InsnType>
522 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
523 const void *Decoder);
524
525 template <typename InsnType>
526 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
527 const void *Decoder);
528
529 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
530 uint64_t Address,
531 const void *Decoder);
532
533 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
534 uint64_t Address,
535 const void *Decoder);
536
537 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
538 uint64_t Address,
539 const void *Decoder);
540
541 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
542 uint64_t Address, const void *Decoder);
543
544 static MCDisassembler *createMipsDisassembler(
545 const Target &T,
546 const MCSubtargetInfo &STI,
547 MCContext &Ctx) {
548 return new MipsDisassembler(STI, Ctx, true);
549 }
550
551 static MCDisassembler *createMipselDisassembler(
552 const Target &T,
553 const MCSubtargetInfo &STI,
554 MCContext &Ctx) {
555 return new MipsDisassembler(STI, Ctx, false);
556 }
557
558 extern "C" void LLVMInitializeMipsDisassembler() {
559 // Register the disassembler.
560 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(),
561 createMipsDisassembler);
562 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(),
563 createMipselDisassembler);
564 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(),
565 createMipsDisassembler);
566 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(),
567 createMipselDisassembler);
568 }
569
570 #include "MipsGenDisassemblerTables.inc"
571
572 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
573 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
574 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
575 return *(RegInfo->getRegClass(RC).begin() + RegNo);
576 }
577
578 template <typename InsnType>
579 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
580 const void *Decoder) {
581 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);
582
583 // The size of the n field depends on the element size
584 // The register class also depends on this.
585 InsnType tmp = fieldFromInstruction(insn, 17, 5);
586 unsigned NSize = 0;
587 DecodeFN RegDecoder = nullptr;
588 if ((tmp & 0x18) == 0x00) { // INSVE_B
589 NSize = 4;
590 RegDecoder = DecodeMSA128BRegisterClass;
591 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
592 NSize = 3;
593 RegDecoder = DecodeMSA128HRegisterClass;
594 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
595 NSize = 2;
596 RegDecoder = DecodeMSA128WRegisterClass;
597 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
598 NSize = 1;
599 RegDecoder = DecodeMSA128DRegisterClass;
600 } else
601 llvm_unreachable("Invalid encoding");
602
603 assert(NSize != 0 && RegDecoder != nullptr);
604
605 // $wd
606 tmp = fieldFromInstruction(insn, 6, 5);
607 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
608 return MCDisassembler::Fail;
609 // $wd_in
610 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
611 return MCDisassembler::Fail;
612 // $n
613 tmp = fieldFromInstruction(insn, 16, NSize);
614 MI.addOperand(MCOperand::createImm(tmp));
615 // $ws
616 tmp = fieldFromInstruction(insn, 11, 5);
617 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
618 return MCDisassembler::Fail;
619 // $n2
620 MI.addOperand(MCOperand::createImm(0));
621
622 return MCDisassembler::Success;
623 }
624
625 template <typename InsnType>
626 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
627 const void *Decoder) {
628 InsnType Rs = fieldFromInstruction(insn, 16, 5);
629 InsnType Imm = fieldFromInstruction(insn, 0, 16);
630 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
631 Rs)));
632 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
633 Rs)));
634 MI.addOperand(MCOperand::createImm(Imm));
635
636 return MCDisassembler::Success;
637 }
638
639 template <typename InsnType>
640 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
641 const void *Decoder) {
642 InsnType Rs = fieldFromInstruction(insn, 21, 5);
643 InsnType Imm = fieldFromInstruction(insn, 0, 16);
644 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
645 Rs)));
646 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
647 Rs)));
648 MI.addOperand(MCOperand::createImm(Imm));
649
650 return MCDisassembler::Success;
651 }
652
653 template <typename InsnType>
654 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
655 uint64_t Address,
656 const void *Decoder) {
657 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
658 // (otherwise we would have matched the ADDI instruction from the earlier
659 // ISA's instead).
660 //
661 // We have:
662 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
663 // BOVC if rs >= rt
664 // BEQZALC if rs == 0 && rt != 0
665 // BEQC if rs < rt && rs != 0
666
667 InsnType Rs = fieldFromInstruction(insn, 21, 5);
668 InsnType Rt = fieldFromInstruction(insn, 16, 5);
669 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
670 bool HasRs = false;
671
672 if (Rs >= Rt) {
673 MI.setOpcode(Mips::BOVC);
674 HasRs = true;
675 } else if (Rs != 0 && Rs < Rt) {
676 MI.setOpcode(Mips::BEQC);
677 HasRs = true;
678 } else
679 MI.setOpcode(Mips::BEQZALC);
680
681 if (HasRs)
682 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
683 Rs)));
684
685 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
686 Rt)));
687 MI.addOperand(MCOperand::createImm(Imm));
688
689 return MCDisassembler::Success;
690 }
691
692 template <typename InsnType>
693 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
694 uint64_t Address,
695 const void *Decoder) {
696 InsnType Rt = fieldFromInstruction(insn, 21, 5);
697 InsnType Rs = fieldFromInstruction(insn, 16, 5);
698 int64_t Imm = 0;
699
700 if (Rs >= Rt) {
701 MI.setOpcode(Mips::BOVC_MMR6);
702 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
703 Rt)));
704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
705 Rs)));
706 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
707 } else if (Rs != 0 && Rs < Rt) {
708 MI.setOpcode(Mips::BEQC_MMR6);
709 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
710 Rs)));
711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
712 Rt)));
713 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
714 } else {
715 MI.setOpcode(Mips::BEQZALC_MMR6);
716 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
717 Rt)));
718 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
719 }
720
721 MI.addOperand(MCOperand::createImm(Imm));
722
723 return MCDisassembler::Success;
724 }
725
726 template <typename InsnType>
727 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
728 uint64_t Address,
729 const void *Decoder) {
730 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
731 // (otherwise we would have matched the ADDI instruction from the earlier
732 // ISA's instead).
733 //
734 // We have:
735 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
736 // BNVC if rs >= rt
737 // BNEZALC if rs == 0 && rt != 0
738 // BNEC if rs < rt && rs != 0
739
740 InsnType Rs = fieldFromInstruction(insn, 21, 5);
741 InsnType Rt = fieldFromInstruction(insn, 16, 5);
742 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
743 bool HasRs = false;
744
745 if (Rs >= Rt) {
746 MI.setOpcode(Mips::BNVC);
747 HasRs = true;
748 } else if (Rs != 0 && Rs < Rt) {
749 MI.setOpcode(Mips::BNEC);
750 HasRs = true;
751 } else
752 MI.setOpcode(Mips::BNEZALC);
753
754 if (HasRs)
755 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
756 Rs)));
757
758 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
759 Rt)));
760 MI.addOperand(MCOperand::createImm(Imm));
761
762 return MCDisassembler::Success;
763 }
764
765 template <typename InsnType>
766 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
767 uint64_t Address,
768 const void *Decoder) {
769 InsnType Rt = fieldFromInstruction(insn, 21, 5);
770 InsnType Rs = fieldFromInstruction(insn, 16, 5);
771 int64_t Imm = 0;
772
773 if (Rs >= Rt) {
774 MI.setOpcode(Mips::BNVC_MMR6);
775 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
776 Rt)));
777 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
778 Rs)));
779 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
780 } else if (Rs != 0 && Rs < Rt) {
781 MI.setOpcode(Mips::BNEC_MMR6);
782 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
783 Rs)));
784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
785 Rt)));
786 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
787 } else {
788 MI.setOpcode(Mips::BNEZALC_MMR6);
789 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
790 Rt)));
791 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
792 }
793
794 MI.addOperand(MCOperand::createImm(Imm));
795
796 return MCDisassembler::Success;
797 }
798
799 template <typename InsnType>
800 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
801 uint64_t Address,
802 const void *Decoder) {
803 // We have:
804 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
805 // Invalid if rt == 0
806 // BGTZC_MMR6 if rs == 0 && rt != 0
807 // BLTZC_MMR6 if rs == rt && rt != 0
808 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
809
810 InsnType Rt = fieldFromInstruction(insn, 21, 5);
811 InsnType Rs = fieldFromInstruction(insn, 16, 5);
812 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
813 bool HasRs = false;
814
815 if (Rt == 0)
816 return MCDisassembler::Fail;
817 else if (Rs == 0)
818 MI.setOpcode(Mips::BGTZC_MMR6);
819 else if (Rs == Rt)
820 MI.setOpcode(Mips::BLTZC_MMR6);
821 else {
822 MI.setOpcode(Mips::BLTC_MMR6);
823 HasRs = true;
824 }
825
826 if (HasRs)
827 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
828 Rs)));
829
830 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
831 Rt)));
832
833 MI.addOperand(MCOperand::createImm(Imm));
834
835 return MCDisassembler::Success;
836 }
837
838 template <typename InsnType>
839 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
840 uint64_t Address,
841 const void *Decoder) {
842 // We have:
843 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
844 // Invalid if rt == 0
845 // BLEZC_MMR6 if rs == 0 && rt != 0
846 // BGEZC_MMR6 if rs == rt && rt != 0
847 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
848
849 InsnType Rt = fieldFromInstruction(insn, 21, 5);
850 InsnType Rs = fieldFromInstruction(insn, 16, 5);
851 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
852 bool HasRs = false;
853
854 if (Rt == 0)
855 return MCDisassembler::Fail;
856 else if (Rs == 0)
857 MI.setOpcode(Mips::BLEZC_MMR6);
858 else if (Rs == Rt)
859 MI.setOpcode(Mips::BGEZC_MMR6);
860 else {
861 HasRs = true;
862 MI.setOpcode(Mips::BGEC_MMR6);
863 }
864
865 if (HasRs)
866 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
867 Rs)));
868
869 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
870 Rt)));
871
872 MI.addOperand(MCOperand::createImm(Imm));
873
874 return MCDisassembler::Success;
875 }
876
877 template <typename InsnType>
878 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
879 uint64_t Address,
880 const void *Decoder) {
881 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
882 // (otherwise we would have matched the BLEZL instruction from the earlier
883 // ISA's instead).
884 //
885 // We have:
886 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
887 // Invalid if rs == 0
888 // BLEZC if rs == 0 && rt != 0
889 // BGEZC if rs == rt && rt != 0
890 // BGEC if rs != rt && rs != 0 && rt != 0
891
892 InsnType Rs = fieldFromInstruction(insn, 21, 5);
893 InsnType Rt = fieldFromInstruction(insn, 16, 5);
894 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
895 bool HasRs = false;
896
897 if (Rt == 0)
898 return MCDisassembler::Fail;
899 else if (Rs == 0)
900 MI.setOpcode(Mips::BLEZC);
901 else if (Rs == Rt)
902 MI.setOpcode(Mips::BGEZC);
903 else {
904 HasRs = true;
905 MI.setOpcode(Mips::BGEC);
906 }
907
908 if (HasRs)
909 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
910 Rs)));
911
912 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
913 Rt)));
914
915 MI.addOperand(MCOperand::createImm(Imm));
916
917 return MCDisassembler::Success;
918 }
919
920 template <typename InsnType>
921 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
922 uint64_t Address,
923 const void *Decoder) {
924 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
925 // (otherwise we would have matched the BGTZL instruction from the earlier
926 // ISA's instead).
927 //
928 // We have:
929 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
930 // Invalid if rs == 0
931 // BGTZC if rs == 0 && rt != 0
932 // BLTZC if rs == rt && rt != 0
933 // BLTC if rs != rt && rs != 0 && rt != 0
934
935 bool HasRs = false;
936
937 InsnType Rs = fieldFromInstruction(insn, 21, 5);
938 InsnType Rt = fieldFromInstruction(insn, 16, 5);
939 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
940
941 if (Rt == 0)
942 return MCDisassembler::Fail;
943 else if (Rs == 0)
944 MI.setOpcode(Mips::BGTZC);
945 else if (Rs == Rt)
946 MI.setOpcode(Mips::BLTZC);
947 else {
948 MI.setOpcode(Mips::BLTC);
949 HasRs = true;
950 }
951
952 if (HasRs)
953 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
954 Rs)));
955
956 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
957 Rt)));
958
959 MI.addOperand(MCOperand::createImm(Imm));
960
961 return MCDisassembler::Success;
962 }
963
964 template <typename InsnType>
965 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
966 uint64_t Address,
967 const void *Decoder) {
968 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
969 // (otherwise we would have matched the BGTZ instruction from the earlier
970 // ISA's instead).
971 //
972 // We have:
973 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
974 // BGTZ if rt == 0
975 // BGTZALC if rs == 0 && rt != 0
976 // BLTZALC if rs != 0 && rs == rt
977 // BLTUC if rs != 0 && rs != rt
978
979 InsnType Rs = fieldFromInstruction(insn, 21, 5);
980 InsnType Rt = fieldFromInstruction(insn, 16, 5);
981 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
982 bool HasRs = false;
983 bool HasRt = false;
984
985 if (Rt == 0) {
986 MI.setOpcode(Mips::BGTZ);
987 HasRs = true;
988 } else if (Rs == 0) {
989 MI.setOpcode(Mips::BGTZALC);
990 HasRt = true;
991 } else if (Rs == Rt) {
992 MI.setOpcode(Mips::BLTZALC);
993 HasRs = true;
994 } else {
995 MI.setOpcode(Mips::BLTUC);
996 HasRs = true;
997 HasRt = true;
998 }
999
1000 if (HasRs)
1001 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1002 Rs)));
1003
1004 if (HasRt)
1005 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1006 Rt)));
1007
1008 MI.addOperand(MCOperand::createImm(Imm));
1009
1010 return MCDisassembler::Success;
1011 }
1012
1013 template <typename InsnType>
1014 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
1015 uint64_t Address,
1016 const void *Decoder) {
1017 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
1018 // (otherwise we would have matched the BLEZL instruction from the earlier
1019 // ISA's instead).
1020 //
1021 // We have:
1022 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
1023 // Invalid if rs == 0
1024 // BLEZALC if rs == 0 && rt != 0
1025 // BGEZALC if rs == rt && rt != 0
1026 // BGEUC if rs != rt && rs != 0 && rt != 0
1027
1028 InsnType Rs = fieldFromInstruction(insn, 21, 5);
1029 InsnType Rt = fieldFromInstruction(insn, 16, 5);
1030 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1031 bool HasRs = false;
1032
1033 if (Rt == 0)
1034 return MCDisassembler::Fail;
1035 else if (Rs == 0)
1036 MI.setOpcode(Mips::BLEZALC);
1037 else if (Rs == Rt)
1038 MI.setOpcode(Mips::BGEZALC);
1039 else {
1040 HasRs = true;
1041 MI.setOpcode(Mips::BGEUC);
1042 }
1043
1044 if (HasRs)
1045 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1046 Rs)));
1047 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1048 Rt)));
1049
1050 MI.addOperand(MCOperand::createImm(Imm));
1051
1052 return MCDisassembler::Success;
1053 }
1054
1055 // Override the generated disassembler to produce DEXT all the time. This is
1056 // for feature / behaviour parity with binutils.
1057 template <typename InsnType>
1058 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
1059 const void *Decoder) {
1060 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1061 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1062 unsigned Size = 0;
1063 unsigned Pos = 0;
1064
1065 switch (MI.getOpcode()) {
1066 case Mips::DEXT:
1067 Pos = Lsb;
1068 Size = Msbd + 1;
1069 break;
1070 case Mips::DEXTM:
1071 Pos = Lsb;
1072 Size = Msbd + 1 + 32;
1073 break;
1074 case Mips::DEXTU:
1075 Pos = Lsb + 32;
1076 Size = Msbd + 1;
1077 break;
1078 default:
1079 llvm_unreachable("Unknown DEXT instruction!");
1080 }
1081
1082 MI.setOpcode(Mips::DEXT);
1083
1084 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1085 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1086
1087 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1088 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1089 MI.addOperand(MCOperand::createImm(Pos));
1090 MI.addOperand(MCOperand::createImm(Size));
1091
1092 return MCDisassembler::Success;
1093 }
1094
1095 // Override the generated disassembler to produce DINS all the time. This is
1096 // for feature / behaviour parity with binutils.
1097 template <typename InsnType>
1098 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
1099 const void *Decoder) {
1100 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1101 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1102 unsigned Size = 0;
1103 unsigned Pos = 0;
1104
1105 switch (MI.getOpcode()) {
1106 case Mips::DINS:
1107 Pos = Lsb;
1108 Size = Msbd + 1 - Pos;
1109 break;
1110 case Mips::DINSM:
1111 Pos = Lsb;
1112 Size = Msbd + 33 - Pos;
1113 break;
1114 case Mips::DINSU:
1115 Pos = Lsb + 32;
1116 // mbsd = pos + size - 33
1117 // mbsd - pos + 33 = size
1118 Size = Msbd + 33 - Pos;
1119 break;
1120 default:
1121 llvm_unreachable("Unknown DINS instruction!");
1122 }
1123
1124 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1125 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1126
1127 MI.setOpcode(Mips::DINS);
1128 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1129 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1130 MI.addOperand(MCOperand::createImm(Pos));
1131 MI.addOperand(MCOperand::createImm(Size));
1132
1133 return MCDisassembler::Success;
1134 }
1135
1136 // Auto-generated decoder wouldn't add the third operand for CRC32*.
1137 template <typename InsnType>
1138 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
1139 const void *Decoder) {
1140 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1141 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1142 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1143 Rt)));
1144 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1145 Rs)));
1146 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1147 Rt)));
1148 return MCDisassembler::Success;
1149 }
1150
1151 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1152 /// according to the given endianness.
1153 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
1154 uint64_t &Size, uint32_t &Insn,
1155 bool IsBigEndian) {
1156 // We want to read exactly 2 Bytes of data.
1157 if (Bytes.size() < 2) {
1158 Size = 0;
1159 return MCDisassembler::Fail;
1160 }
1161
1162 if (IsBigEndian) {
1163 Insn = (Bytes[0] << 8) | Bytes[1];
1164 } else {
1165 Insn = (Bytes[1] << 8) | Bytes[0];
1166 }
1167
1168 return MCDisassembler::Success;
1169 }
1170
1171 /// Read four bytes from the ArrayRef and return 32 bit word sorted
1172 /// according to the given endianness.
1173 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
1174 uint64_t &Size, uint32_t &Insn,
1175 bool IsBigEndian, bool IsMicroMips) {
1176 // We want to read exactly 4 Bytes of data.
1177 if (Bytes.size() < 4) {
1178 Size = 0;
1179 return MCDisassembler::Fail;
1180 }
1181
1182 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1183 // always precede the low 16 bits in the instruction stream (that is, they
1184 // are placed at lower addresses in the instruction stream).
1185 //
1186 // microMIPS byte ordering:
1187 // Big-endian: 0 | 1 | 2 | 3
1188 // Little-endian: 1 | 0 | 3 | 2
1189
1190 if (IsBigEndian) {
1191 // Encoded as a big-endian 32-bit word in the stream.
1192 Insn =
1193 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1194 } else {
1195 if (IsMicroMips) {
1196 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1197 (Bytes[1] << 24);
1198 } else {
1199 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1200 (Bytes[3] << 24);
1201 }
1202 }
1203
1204 return MCDisassembler::Success;
1205 }
1206
1207 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1208 ArrayRef<uint8_t> Bytes,
1209 uint64_t Address,
1210 raw_ostream &VStream,
1211 raw_ostream &CStream) const {
1212 uint32_t Insn;
1213 DecodeStatus Result;
1214 Size = 0;
1215
1216 if (IsMicroMips) {
1217 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1218 if (Result == MCDisassembler::Fail)
1219 return MCDisassembler::Fail;
1220
1221 if (hasMips32r6()) {
1222 LLVM_DEBUG(
1223 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1224 // Calling the auto-generated decoder function for microMIPS32R6
1225 // 16-bit instructions.
1226 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1227 Address, this, STI);
1228 if (Result != MCDisassembler::Fail) {
1229 Size = 2;
1230 return Result;
1231 }
1232 }
1233
1234 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1235 // Calling the auto-generated decoder function for microMIPS 16-bit
1236 // instructions.
1237 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1238 this, STI);
1239 if (Result != MCDisassembler::Fail) {
1240 Size = 2;
1241 return Result;
1242 }
1243
1244 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1245 if (Result == MCDisassembler::Fail)
1246 return MCDisassembler::Fail;
1247
1248 if (hasMips32r6()) {
1249 LLVM_DEBUG(
1250 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1251 // Calling the auto-generated decoder function.
1252 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
1253 this, STI);
1254 if (Result != MCDisassembler::Fail) {
1255 Size = 4;
1256 return Result;
1257 }
1258 }
1259
1260 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1261 // Calling the auto-generated decoder function.
1262 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1263 this, STI);
1264 if (Result != MCDisassembler::Fail) {
1265 Size = 4;
1266 return Result;
1267 }
1268
1269 if (isFP64()) {
1270 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
1271 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
1272 Address, this, STI);
1273 if (Result != MCDisassembler::Fail) {
1274 Size = 4;
1275 return Result;
1276 }
1277 }
1278
1279 // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1280 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1281 // could form a valid instruction. The two bytes we rejected as an
1282 // instruction could have actually beeen an inline constant pool that is
1283 // unconditionally branched over.
1284 Size = 2;
1285 return MCDisassembler::Fail;
1286 }
1287
1288 // Attempt to read the instruction so that we can attempt to decode it. If
1289 // the buffer is not 4 bytes long, let the higher level logic figure out
1290 // what to do with a size of zero and MCDisassembler::Fail.
1291 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
1292 if (Result == MCDisassembler::Fail)
1293 return MCDisassembler::Fail;
1294
1295 // The only instruction size for standard encoded MIPS.
1296 Size = 4;
1297
1298 if (hasCOP3()) {
1299 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1300 Result =
1301 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1302 if (Result != MCDisassembler::Fail)
1303 return Result;
1304 }
1305
1306 if (hasMips32r6() && isGP64()) {
1307 LLVM_DEBUG(
1308 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1309 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1310 Address, this, STI);
1311 if (Result != MCDisassembler::Fail)
1312 return Result;
1313 }
1314
1315 if (hasMips32r6() && isPTR64()) {
1316 LLVM_DEBUG(
1317 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1318 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1319 Address, this, STI);
1320 if (Result != MCDisassembler::Fail)
1321 return Result;
1322 }
1323
1324 if (hasMips32r6()) {
1325 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1326 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
1327 Address, this, STI);
1328 if (Result != MCDisassembler::Fail)
1329 return Result;
1330 }
1331
1332 if (hasMips2() && isPTR64()) {
1333 LLVM_DEBUG(
1334 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1335 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1336 Address, this, STI);
1337 if (Result != MCDisassembler::Fail)
1338 return Result;
1339 }
1340
1341 if (hasCnMips()) {
1342 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1343 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
1344 Address, this, STI);
1345 if (Result != MCDisassembler::Fail)
1346 return Result;
1347 }
1348
1349 if (isGP64()) {
1350 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1351 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
1352 Address, this, STI);
1353 if (Result != MCDisassembler::Fail)
1354 return Result;
1355 }
1356
1357 if (isFP64()) {
1358 LLVM_DEBUG(
1359 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
1360 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn,
1361 Address, this, STI);
1362 if (Result != MCDisassembler::Fail)
1363 return Result;
1364 }
1365
1366 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1367 // Calling the auto-generated decoder function.
1368 Result =
1369 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
1370 if (Result != MCDisassembler::Fail)
1371 return Result;
1372
1373 return MCDisassembler::Fail;
1374 }
1375
1376 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
1377 unsigned RegNo,
1378 uint64_t Address,
1379 const void *Decoder) {
1380 return MCDisassembler::Fail;
1381 }
1382
1383 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
1384 unsigned RegNo,
1385 uint64_t Address,
1386 const void *Decoder) {
1387 if (RegNo > 31)
1388 return MCDisassembler::Fail;
1389
1390 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1391 Inst.addOperand(MCOperand::createReg(Reg));
1392 return MCDisassembler::Success;
1393 }
1394
1395 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
1396 unsigned RegNo,
1397 uint64_t Address,
1398 const void *Decoder) {
1399 if (RegNo > 7)
1400 return MCDisassembler::Fail;
1401 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1402 Inst.addOperand(MCOperand::createReg(Reg));
1403 return MCDisassembler::Success;
1404 }
1405
1406 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
1407 unsigned RegNo,
1408 uint64_t Address,
1409 const void *Decoder) {
1410 if (RegNo > 7)
1411 return MCDisassembler::Fail;
1412 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1413 Inst.addOperand(MCOperand::createReg(Reg));
1414 return MCDisassembler::Success;
1415 }
1416
1417 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1418 unsigned RegNo,
1419 uint64_t Address,
1420 const void *Decoder) {
1421 if (RegNo > 7)
1422 return MCDisassembler::Fail;
1423 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1424 Inst.addOperand(MCOperand::createReg(Reg));
1425 return MCDisassembler::Success;
1426 }
1427
1428 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1429 unsigned RegNo,
1430 uint64_t Address,
1431 const void *Decoder) {
1432 if (RegNo > 31)
1433 return MCDisassembler::Fail;
1434 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1435 Inst.addOperand(MCOperand::createReg(Reg));
1436 return MCDisassembler::Success;
1437 }
1438
1439 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1440 unsigned RegNo,
1441 uint64_t Address,
1442 const void *Decoder) {
1443 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1444 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1445
1446 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1447 }
1448
1449 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1450 unsigned RegNo,
1451 uint64_t Address,
1452 const void *Decoder) {
1453 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1454 }
1455
1456 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1457 unsigned RegNo,
1458 uint64_t Address,
1459 const void *Decoder) {
1460 if (RegNo > 31)
1461 return MCDisassembler::Fail;
1462
1463 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1464 Inst.addOperand(MCOperand::createReg(Reg));
1465 return MCDisassembler::Success;
1466 }
1467
1468 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1469 unsigned RegNo,
1470 uint64_t Address,
1471 const void *Decoder) {
1472 if (RegNo > 31)
1473 return MCDisassembler::Fail;
1474
1475 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1476 Inst.addOperand(MCOperand::createReg(Reg));
1477 return MCDisassembler::Success;
1478 }
1479
1480 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1481 unsigned RegNo,
1482 uint64_t Address,
1483 const void *Decoder) {
1484 if (RegNo > 31)
1485 return MCDisassembler::Fail;
1486 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1487 Inst.addOperand(MCOperand::createReg(Reg));
1488 return MCDisassembler::Success;
1489 }
1490
1491 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1492 unsigned RegNo,
1493 uint64_t Address,
1494 const void *Decoder) {
1495 if (RegNo > 7)
1496 return MCDisassembler::Fail;
1497 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1498 Inst.addOperand(MCOperand::createReg(Reg));
1499 return MCDisassembler::Success;
1500 }
1501
1502 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1503 uint64_t Address,
1504 const void *Decoder) {
1505 if (RegNo > 31)
1506 return MCDisassembler::Fail;
1507
1508 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1509 Inst.addOperand(MCOperand::createReg(Reg));
1510 return MCDisassembler::Success;
1511 }
1512
1513 static DecodeStatus DecodeMem(MCInst &Inst,
1514 unsigned Insn,
1515 uint64_t Address,
1516 const void *Decoder) {
1517 int Offset = SignExtend32<16>(Insn & 0xffff);
1518 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1519 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1520
1521 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1522 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1523
1524 if (Inst.getOpcode() == Mips::SC ||
1525 Inst.getOpcode() == Mips::SCD)
1526 Inst.addOperand(MCOperand::createReg(Reg));
1527
1528 Inst.addOperand(MCOperand::createReg(Reg));
1529 Inst.addOperand(MCOperand::createReg(Base));
1530 Inst.addOperand(MCOperand::createImm(Offset));
1531
1532 return MCDisassembler::Success;
1533 }
1534
1535 static DecodeStatus DecodeMemEVA(MCInst &Inst,
1536 unsigned Insn,
1537 uint64_t Address,
1538 const void *Decoder) {
1539 int Offset = SignExtend32<9>(Insn >> 7);
1540 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1541 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1542
1543 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1544 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1545
1546 if (Inst.getOpcode() == Mips::SCE)
1547 Inst.addOperand(MCOperand::createReg(Reg));
1548
1549 Inst.addOperand(MCOperand::createReg(Reg));
1550 Inst.addOperand(MCOperand::createReg(Base));
1551 Inst.addOperand(MCOperand::createImm(Offset));
1552
1553 return MCDisassembler::Success;
1554 }
1555
1556 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
1557 unsigned Insn,
1558 uint64_t Address,
1559 const void *Decoder) {
1560 int Offset = SignExtend32<16>(Insn & 0xffff);
1561 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1562 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1563
1564 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1565 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1566
1567 Inst.addOperand(MCOperand::createReg(Reg));
1568 Inst.addOperand(MCOperand::createReg(Base));
1569 Inst.addOperand(MCOperand::createImm(Offset));
1570
1571 return MCDisassembler::Success;
1572 }
1573
1574 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1575 unsigned Insn,
1576 uint64_t Address,
1577 const void *Decoder) {
1578 int Offset = SignExtend32<16>(Insn & 0xffff);
1579 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1580 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1581
1582 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1583
1584 Inst.addOperand(MCOperand::createReg(Base));
1585 Inst.addOperand(MCOperand::createImm(Offset));
1586 Inst.addOperand(MCOperand::createImm(Hint));
1587
1588 return MCDisassembler::Success;
1589 }
1590
1591 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1592 unsigned Insn,
1593 uint64_t Address,
1594 const void *Decoder) {
1595 int Offset = SignExtend32<12>(Insn & 0xfff);
1596 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1597 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1598
1599 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1600
1601 Inst.addOperand(MCOperand::createReg(Base));
1602 Inst.addOperand(MCOperand::createImm(Offset));
1603 Inst.addOperand(MCOperand::createImm(Hint));
1604
1605 return MCDisassembler::Success;
1606 }
1607
1608 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
1609 unsigned Insn,
1610 uint64_t Address,
1611 const void *Decoder) {
1612 int Offset = SignExtend32<9>(Insn & 0x1ff);
1613 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1614 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1615
1616 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1617
1618 Inst.addOperand(MCOperand::createReg(Base));
1619 Inst.addOperand(MCOperand::createImm(Offset));
1620 Inst.addOperand(MCOperand::createImm(Hint));
1621
1622 return MCDisassembler::Success;
1623 }
1624
1625 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
1626 unsigned Insn,
1627 uint64_t Address,
1628 const void *Decoder) {
1629 int Offset = SignExtend32<9>(Insn >> 7);
1630 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1631 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1632
1633 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1634
1635 Inst.addOperand(MCOperand::createReg(Base));
1636 Inst.addOperand(MCOperand::createImm(Offset));
1637 Inst.addOperand(MCOperand::createImm(Hint));
1638
1639 return MCDisassembler::Success;
1640 }
1641
1642 static DecodeStatus DecodeSyncI(MCInst &Inst,
1643 unsigned Insn,
1644 uint64_t Address,
1645 const void *Decoder) {
1646 int Offset = SignExtend32<16>(Insn & 0xffff);
1647 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1648
1649 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1650
1651 Inst.addOperand(MCOperand::createReg(Base));
1652 Inst.addOperand(MCOperand::createImm(Offset));
1653
1654 return MCDisassembler::Success;
1655 }
1656
1657 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1658 uint64_t Address, const void *Decoder) {
1659 int Offset = SignExtend32<16>(Insn & 0xffff);
1660 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1661
1662 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1663
1664 Inst.addOperand(MCOperand::createReg(Base));
1665 Inst.addOperand(MCOperand::createImm(Offset));
1666
1667 return MCDisassembler::Success;
1668 }
1669
1670 static DecodeStatus DecodeSynciR6(MCInst &Inst,
1671 unsigned Insn,
1672 uint64_t Address,
1673 const void *Decoder) {
1674 int Immediate = SignExtend32<16>(Insn & 0xffff);
1675 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1676
1677 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1678
1679 Inst.addOperand(MCOperand::createReg(Base));
1680 Inst.addOperand(MCOperand::createImm(Immediate));
1681
1682 return MCDisassembler::Success;
1683 }
1684
1685 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1686 uint64_t Address, const void *Decoder) {
1687 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1688 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1689 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1690
1691 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1692 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1693
1694 Inst.addOperand(MCOperand::createReg(Reg));
1695 Inst.addOperand(MCOperand::createReg(Base));
1696
1697 // The immediate field of an LD/ST instruction is scaled which means it must
1698 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1699 // data format.
1700 // .b - 1 byte
1701 // .h - 2 bytes
1702 // .w - 4 bytes
1703 // .d - 8 bytes
1704 switch(Inst.getOpcode())
1705 {
1706 default:
1707 assert(false && "Unexpected instruction");
1708 return MCDisassembler::Fail;
1709 break;
1710 case Mips::LD_B:
1711 case Mips::ST_B:
1712 Inst.addOperand(MCOperand::createImm(Offset));
1713 break;
1714 case Mips::LD_H:
1715 case Mips::ST_H:
1716 Inst.addOperand(MCOperand::createImm(Offset * 2));
1717 break;
1718 case Mips::LD_W:
1719 case Mips::ST_W:
1720 Inst.addOperand(MCOperand::createImm(Offset * 4));
1721 break;
1722 case Mips::LD_D:
1723 case Mips::ST_D:
1724 Inst.addOperand(MCOperand::createImm(Offset * 8));
1725 break;
1726 }
1727
1728 return MCDisassembler::Success;
1729 }
1730
1731 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1732 unsigned Insn,
1733 uint64_t Address,
1734 const void *Decoder) {
1735 unsigned Offset = Insn & 0xf;
1736 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1737 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1738
1739 switch (Inst.getOpcode()) {
1740 case Mips::LBU16_MM:
1741 case Mips::LHU16_MM:
1742 case Mips::LW16_MM:
1743 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1744 == MCDisassembler::Fail)
1745 return MCDisassembler::Fail;
1746 break;
1747 case Mips::SB16_MM:
1748 case Mips::SB16_MMR6:
1749 case Mips::SH16_MM:
1750 case Mips::SH16_MMR6:
1751 case Mips::SW16_MM:
1752 case Mips::SW16_MMR6:
1753 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1754 == MCDisassembler::Fail)
1755 return MCDisassembler::Fail;
1756 break;
1757 }
1758
1759 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1760 == MCDisassembler::Fail)
1761 return MCDisassembler::Fail;
1762
1763 switch (Inst.getOpcode()) {
1764 case Mips::LBU16_MM:
1765 if (Offset == 0xf)
1766 Inst.addOperand(MCOperand::createImm(-1));
1767 else
1768 Inst.addOperand(MCOperand::createImm(Offset));
1769 break;
1770 case Mips::SB16_MM:
1771 case Mips::SB16_MMR6:
1772 Inst.addOperand(MCOperand::createImm(Offset));
1773 break;
1774 case Mips::LHU16_MM:
1775 case Mips::SH16_MM:
1776 case Mips::SH16_MMR6:
1777 Inst.addOperand(MCOperand::createImm(Offset << 1));
1778 break;
1779 case Mips::LW16_MM:
1780 case Mips::SW16_MM:
1781 case Mips::SW16_MMR6:
1782 Inst.addOperand(MCOperand::createImm(Offset << 2));
1783 break;
1784 }
1785
1786 return MCDisassembler::Success;
1787 }
1788
1789 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1790 unsigned Insn,
1791 uint64_t Address,
1792 const void *Decoder) {
1793 unsigned Offset = Insn & 0x1F;
1794 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1795
1796 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1797
1798 Inst.addOperand(MCOperand::createReg(Reg));
1799 Inst.addOperand(MCOperand::createReg(Mips::SP));
1800 Inst.addOperand(MCOperand::createImm(Offset << 2));
1801
1802 return MCDisassembler::Success;
1803 }
1804
1805 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1806 unsigned Insn,
1807 uint64_t Address,
1808 const void *Decoder) {
1809 unsigned Offset = Insn & 0x7F;
1810 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1811
1812 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1813
1814 Inst.addOperand(MCOperand::createReg(Reg));
1815 Inst.addOperand(MCOperand::createReg(Mips::GP));
1816 Inst.addOperand(MCOperand::createImm(Offset << 2));
1817
1818 return MCDisassembler::Success;
1819 }
1820
1821 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1822 unsigned Insn,
1823 uint64_t Address,
1824 const void *Decoder) {
1825 int Offset;
1826 switch (Inst.getOpcode()) {
1827 case Mips::LWM16_MMR6:
1828 case Mips::SWM16_MMR6:
1829 Offset = fieldFromInstruction(Insn, 4, 4);
1830 break;
1831 default:
1832 Offset = SignExtend32<4>(Insn & 0xf);
1833 break;
1834 }
1835
1836 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1837 == MCDisassembler::Fail)
1838 return MCDisassembler::Fail;
1839
1840 Inst.addOperand(MCOperand::createReg(Mips::SP));
1841 Inst.addOperand(MCOperand::createImm(Offset << 2));
1842
1843 return MCDisassembler::Success;
1844 }
1845
1846 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1847 unsigned Insn,
1848 uint64_t Address,
1849 const void *Decoder) {
1850 int Offset = SignExtend32<9>(Insn & 0x1ff);
1851 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1852 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1853
1854 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1855 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1856
1857 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1858 Inst.addOperand(MCOperand::createReg(Reg));
1859
1860 Inst.addOperand(MCOperand::createReg(Reg));
1861 Inst.addOperand(MCOperand::createReg(Base));
1862 Inst.addOperand(MCOperand::createImm(Offset));
1863
1864 return MCDisassembler::Success;
1865 }
1866
1867 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1868 unsigned Insn,
1869 uint64_t Address,
1870 const void *Decoder) {
1871 int Offset = SignExtend32<12>(Insn & 0x0fff);
1872 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1873 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1874
1875 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1876 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1877
1878 switch (Inst.getOpcode()) {
1879 case Mips::SWM32_MM:
1880 case Mips::LWM32_MM:
1881 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1882 == MCDisassembler::Fail)
1883 return MCDisassembler::Fail;
1884 Inst.addOperand(MCOperand::createReg(Base));
1885 Inst.addOperand(MCOperand::createImm(Offset));
1886 break;
1887 case Mips::SC_MM:
1888 Inst.addOperand(MCOperand::createReg(Reg));
1889 LLVM_FALLTHROUGH;
1890 default:
1891 Inst.addOperand(MCOperand::createReg(Reg));
1892 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1893 Inst.addOperand(MCOperand::createReg(Reg+1));
1894
1895 Inst.addOperand(MCOperand::createReg(Base));
1896 Inst.addOperand(MCOperand::createImm(Offset));
1897 }
1898
1899 return MCDisassembler::Success;
1900 }
1901
1902 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1903 unsigned Insn,
1904 uint64_t Address,
1905 const void *Decoder) {
1906 int Offset = SignExtend32<16>(Insn & 0xffff);
1907 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1908 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1909
1910 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1911 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1912
1913 Inst.addOperand(MCOperand::createReg(Reg));
1914 Inst.addOperand(MCOperand::createReg(Base));
1915 Inst.addOperand(MCOperand::createImm(Offset));
1916
1917 return MCDisassembler::Success;
1918 }
1919
1920 static DecodeStatus DecodeFMem(MCInst &Inst,
1921 unsigned Insn,
1922 uint64_t Address,
1923 const void *Decoder) {
1924 int Offset = SignExtend32<16>(Insn & 0xffff);
1925 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1926 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1927
1928 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1929 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1930
1931 Inst.addOperand(MCOperand::createReg(Reg));
1932 Inst.addOperand(MCOperand::createReg(Base));
1933 Inst.addOperand(MCOperand::createImm(Offset));
1934
1935 return MCDisassembler::Success;
1936 }
1937
1938 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1939 uint64_t Address, const void *Decoder) {
1940 // This function is the same as DecodeFMem but with the Reg and Base fields
1941 // swapped according to microMIPS spec.
1942 int Offset = SignExtend32<16>(Insn & 0xffff);
1943 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1944 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1945
1946 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1947 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1948
1949 Inst.addOperand(MCOperand::createReg(Reg));
1950 Inst.addOperand(MCOperand::createReg(Base));
1951 Inst.addOperand(MCOperand::createImm(Offset));
1952
1953 return MCDisassembler::Success;
1954 }
1955
1956 static DecodeStatus DecodeFMem2(MCInst &Inst,
1957 unsigned Insn,
1958 uint64_t Address,
1959 const void *Decoder) {
1960 int Offset = SignExtend32<16>(Insn & 0xffff);
1961 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1962 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1963
1964 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1965 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1966
1967 Inst.addOperand(MCOperand::createReg(Reg));
1968 Inst.addOperand(MCOperand::createReg(Base));
1969 Inst.addOperand(MCOperand::createImm(Offset));
1970
1971 return MCDisassembler::Success;
1972 }
1973
1974 static DecodeStatus DecodeFMem3(MCInst &Inst,
1975 unsigned Insn,
1976 uint64_t Address,
1977 const void *Decoder) {
1978 int Offset = SignExtend32<16>(Insn & 0xffff);
1979 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1980 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1981
1982 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1983 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1984
1985 Inst.addOperand(MCOperand::createReg(Reg));
1986 Inst.addOperand(MCOperand::createReg(Base));
1987 Inst.addOperand(MCOperand::createImm(Offset));
1988
1989 return MCDisassembler::Success;
1990 }
1991
1992 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1993 unsigned Insn,
1994 uint64_t Address,
1995 const void *Decoder) {
1996 int Offset = SignExtend32<11>(Insn & 0x07ff);
1997 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1998 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1999
2000 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2001 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2002
2003 Inst.addOperand(MCOperand::createReg(Reg));
2004 Inst.addOperand(MCOperand::createReg(Base));
2005 Inst.addOperand(MCOperand::createImm(Offset));
2006
2007 return MCDisassembler::Success;
2008 }
2009
2010 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
2011 uint64_t Address, const void *Decoder) {
2012 int Offset = SignExtend32<11>(Insn & 0x07ff);
2013 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
2014 unsigned Base = fieldFromInstruction(Insn, 16, 5);
2015
2016 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2017 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2018
2019 Inst.addOperand(MCOperand::createReg(Reg));
2020 Inst.addOperand(MCOperand::createReg(Base));
2021 Inst.addOperand(MCOperand::createImm(Offset));
2022
2023 return MCDisassembler::Success;
2024 }
2025
2026 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
2027 unsigned Insn,
2028 uint64_t Address,
2029 const void *Decoder) {
2030 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
2031 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
2032 unsigned Base = fieldFromInstruction(Insn, 21, 5);
2033
2034 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
2035 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2036
2037 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
2038 Inst.addOperand(MCOperand::createReg(Rt));
2039 }
2040
2041 Inst.addOperand(MCOperand::createReg(Rt));
2042 Inst.addOperand(MCOperand::createReg(Base));
2043 Inst.addOperand(MCOperand::createImm(Offset));
2044
2045 return MCDisassembler::Success;
2046 }
2047
2048 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
2049 unsigned RegNo,
2050 uint64_t Address,
2051 const void *Decoder) {
2052 // Currently only hardware register 29 is supported.
2053 if (RegNo != 29)
2054 return MCDisassembler::Fail;
2055 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
2056 return MCDisassembler::Success;
2057 }
2058
2059 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
2060 unsigned RegNo,
2061 uint64_t Address,
2062 const void *Decoder) {
2063 if (RegNo > 30 || RegNo %2)
2064 return MCDisassembler::Fail;
2065
2066 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
2067 Inst.addOperand(MCOperand::createReg(Reg));
2068 return MCDisassembler::Success;
2069 }
2070
2071 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
2072 unsigned RegNo,
2073 uint64_t Address,
2074 const void *Decoder) {
2075 if (RegNo >= 4)
2076 return MCDisassembler::Fail;
2077
2078 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
2079 Inst.addOperand(MCOperand::createReg(Reg));
2080 return MCDisassembler::Success;
2081 }
2082
2083 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
2084 unsigned RegNo,
2085 uint64_t Address,
2086 const void *Decoder) {
2087 if (RegNo >= 4)
2088 return MCDisassembler::Fail;
2089
2090 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2091 Inst.addOperand(MCOperand::createReg(Reg));
2092 return MCDisassembler::Success;
2093 }
2094
2095 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
2096 unsigned RegNo,
2097 uint64_t Address,
2098 const void *Decoder) {
2099 if (RegNo >= 4)
2100 return MCDisassembler::Fail;
2101
2102 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2103 Inst.addOperand(MCOperand::createReg(Reg));
2104 return MCDisassembler::Success;
2105 }
2106
2107 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
2108 unsigned RegNo,
2109 uint64_t Address,
2110 const void *Decoder) {
2111 if (RegNo > 31)
2112 return MCDisassembler::Fail;
2113
2114 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2115 Inst.addOperand(MCOperand::createReg(Reg));
2116 return MCDisassembler::Success;
2117 }
2118
2119 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
2120 unsigned RegNo,
2121 uint64_t Address,
2122 const void *Decoder) {
2123 if (RegNo > 31)
2124 return MCDisassembler::Fail;
2125
2126 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2127 Inst.addOperand(MCOperand::createReg(Reg));
2128 return MCDisassembler::Success;
2129 }
2130
2131 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
2132 unsigned RegNo,
2133 uint64_t Address,
2134 const void *Decoder) {
2135 if (RegNo > 31)
2136 return MCDisassembler::Fail;
2137
2138 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2139 Inst.addOperand(MCOperand::createReg(Reg));
2140 return MCDisassembler::Success;
2141 }
2142
2143 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
2144 unsigned RegNo,
2145 uint64_t Address,
2146 const void *Decoder) {
2147 if (RegNo > 31)
2148 return MCDisassembler::Fail;
2149
2150 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2151 Inst.addOperand(MCOperand::createReg(Reg));
2152 return MCDisassembler::Success;
2153 }
2154
2155 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
2156 unsigned RegNo,
2157 uint64_t Address,
2158 const void *Decoder) {
2159 if (RegNo > 7)
2160 return MCDisassembler::Fail;
2161
2162 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2163 Inst.addOperand(MCOperand::createReg(Reg));
2164 return MCDisassembler::Success;
2165 }
2166
2167 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
2168 unsigned RegNo,
2169 uint64_t Address,
2170 const void *Decoder) {
2171 if (RegNo > 31)
2172 return MCDisassembler::Fail;
2173
2174 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
2175 Inst.addOperand(MCOperand::createReg(Reg));
2176 return MCDisassembler::Success;
2177 }
2178
2179 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
2180 unsigned RegNo,
2181 uint64_t Address,
2182 const void *Decoder) {
2183 if (RegNo > 31)
2184 return MCDisassembler::Fail;
2185
2186 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
2187 Inst.addOperand(MCOperand::createReg(Reg));
2188 return MCDisassembler::Success;
2189 }
2190
2191 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
2192 unsigned Offset,
2193 uint64_t Address,
2194 const void *Decoder) {
2195 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2196 Inst.addOperand(MCOperand::createImm(BranchOffset));
2197 return MCDisassembler::Success;
2198 }
2199
2200 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
2201 unsigned Offset,
2202 uint64_t Address,
2203 const void *Decoder) {
2204 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2205 Inst.addOperand(MCOperand::createImm(BranchOffset));
2206 return MCDisassembler::Success;
2207 }
2208
2209 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
2210 unsigned Insn,
2211 uint64_t Address,
2212 const void *Decoder) {
2213 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2214 Inst.addOperand(MCOperand::createImm(JumpOffset));
2215 return MCDisassembler::Success;
2216 }
2217
2218 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
2219 unsigned Offset,
2220 uint64_t Address,
2221 const void *Decoder) {
2222 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2223
2224 Inst.addOperand(MCOperand::createImm(BranchOffset));
2225 return MCDisassembler::Success;
2226 }
2227
2228 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
2229 unsigned Offset,
2230 uint64_t Address,
2231 const void *Decoder) {
2232 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2233
2234 Inst.addOperand(MCOperand::createImm(BranchOffset));
2235 return MCDisassembler::Success;
2236 }
2237
2238 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
2239 unsigned Offset,
2240 uint64_t Address,
2241 const void *Decoder) {
2242 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2243
2244 Inst.addOperand(MCOperand::createImm(BranchOffset));
2245 return MCDisassembler::Success;
2246 }
2247
2248 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
2249 unsigned Offset,
2250 uint64_t Address,
2251 const void *Decoder) {
2252 int32_t BranchOffset = SignExtend32<8>(Offset << 1);
2253 Inst.addOperand(MCOperand::createImm(BranchOffset));
2254 return MCDisassembler::Success;
2255 }
2256
2257 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
2258 unsigned Offset,
2259 uint64_t Address,
2260 const void *Decoder) {
2261 int32_t BranchOffset = SignExtend32<11>(Offset << 1);
2262 Inst.addOperand(MCOperand::createImm(BranchOffset));
2263 return MCDisassembler::Success;
2264 }
2265
2266 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
2267 unsigned Offset,
2268 uint64_t Address,
2269 const void *Decoder) {
2270 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2271 Inst.addOperand(MCOperand::createImm(BranchOffset));
2272 return MCDisassembler::Success;
2273 }
2274
2275 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
2276 unsigned Offset,
2277 uint64_t Address,
2278 const void *Decoder) {
2279 int32_t BranchOffset = SignExtend32<27>(Offset << 1);
2280
2281 Inst.addOperand(MCOperand::createImm(BranchOffset));
2282 return MCDisassembler::Success;
2283 }
2284
2285 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
2286 unsigned Insn,
2287 uint64_t Address,
2288 const void *Decoder) {
2289 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2290 Inst.addOperand(MCOperand::createImm(JumpOffset));
2291 return MCDisassembler::Success;
2292 }
2293
2294 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
2295 unsigned Value,
2296 uint64_t Address,
2297 const void *Decoder) {
2298 if (Value == 0)
2299 Inst.addOperand(MCOperand::createImm(1));
2300 else if (Value == 0x7)
2301 Inst.addOperand(MCOperand::createImm(-1));
2302 else
2303 Inst.addOperand(MCOperand::createImm(Value << 2));
2304 return MCDisassembler::Success;
2305 }
2306
2307 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
2308 unsigned Value,
2309 uint64_t Address,
2310 const void *Decoder) {
2311 if (Value == 0x7F)
2312 Inst.addOperand(MCOperand::createImm(-1));
2313 else
2314 Inst.addOperand(MCOperand::createImm(Value));
2315 return MCDisassembler::Success;
2316 }
2317
2318 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
2319 unsigned Value,
2320 uint64_t Address,
2321 const void *Decoder) {
2322 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2323 return MCDisassembler::Success;
2324 }
2325
2326 template <unsigned Bits, int Offset, int Scale>
2327 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2328 uint64_t Address,
2329 const void *Decoder) {
2330 Value &= ((1 << Bits) - 1);
2331 Value *= Scale;
2332 Inst.addOperand(MCOperand::createImm(Value + Offset));
2333 return MCDisassembler::Success;
2334 }
2335
2336 template <unsigned Bits, int Offset, int ScaleBy>
2337 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2338 uint64_t Address,
2339 const void *Decoder) {
2340 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2341 Inst.addOperand(MCOperand::createImm(Imm + Offset));
2342 return MCDisassembler::Success;
2343 }
2344
2345 static DecodeStatus DecodeInsSize(MCInst &Inst,
2346 unsigned Insn,
2347 uint64_t Address,
2348 const void *Decoder) {
2349 // First we need to grab the pos(lsb) from MCInst.
2350 // This function only handles the 32 bit variants of ins, as dins
2351 // variants are handled differently.
2352 int Pos = Inst.getOperand(2).getImm();
2353 int Size = (int) Insn - Pos + 1;
2354 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2355 return MCDisassembler::Success;
2356 }
2357
2358 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2359 uint64_t Address, const void *Decoder) {
2360 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2361 return MCDisassembler::Success;
2362 }
2363
2364 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2365 uint64_t Address, const void *Decoder) {
2366 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2367 return MCDisassembler::Success;
2368 }
2369
2370 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
2371 uint64_t Address, const void *Decoder) {
2372 int32_t DecodedValue;
2373 switch (Insn) {
2374 case 0: DecodedValue = 256; break;
2375 case 1: DecodedValue = 257; break;
2376 case 510: DecodedValue = -258; break;
2377 case 511: DecodedValue = -257; break;
2378 default: DecodedValue = SignExtend32<9>(Insn); break;
2379 }
2380 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2381 return MCDisassembler::Success;
2382 }
2383
2384 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2385 uint64_t Address, const void *Decoder) {
2386 // Insn must be >= 0, since it is unsigned that condition is always true.
2387 assert(Insn < 16);
2388 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2389 255, 32768, 65535};
2390 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2391 return MCDisassembler::Success;
2392 }
2393
2394 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
2395 unsigned Insn,
2396 uint64_t Address,
2397 const void *Decoder) {
2398 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2399 Mips::S6, Mips::S7, Mips::FP};
2400 unsigned RegNum;
2401
2402 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2403
2404 // Empty register lists are not allowed.
2405 if (RegLst == 0)
2406 return MCDisassembler::Fail;
2407
2408 RegNum = RegLst & 0xf;
2409
2410 // RegLst values 10-15, and 26-31 are reserved.
2411 if (RegNum > 9)
2412 return MCDisassembler::Fail;
2413
2414 for (unsigned i = 0; i < RegNum; i++)
2415 Inst.addOperand(MCOperand::createReg(Regs[i]));
2416
2417 if (RegLst & 0x10)
2418 Inst.addOperand(MCOperand::createReg(Mips::RA));
2419
2420 return MCDisassembler::Success;
2421 }
2422
2423 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2424 uint64_t Address,
2425 const void *Decoder) {
2426 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2427 unsigned RegLst;
2428 switch(Inst.getOpcode()) {
2429 default:
2430 RegLst = fieldFromInstruction(Insn, 4, 2);
2431 break;
2432 case Mips::LWM16_MMR6:
2433 case Mips::SWM16_MMR6:
2434 RegLst = fieldFromInstruction(Insn, 8, 2);
2435 break;
2436 }
2437 unsigned RegNum = RegLst & 0x3;
2438
2439 for (unsigned i = 0; i <= RegNum; i++)
2440 Inst.addOperand(MCOperand::createReg(Regs[i]));
2441
2442 Inst.addOperand(MCOperand::createReg(Mips::RA));
2443
2444 return MCDisassembler::Success;
2445 }
2446
2447 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
2448 uint64_t Address,
2449 const void *Decoder) {
2450 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2451 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
2452 MCDisassembler::Fail)
2453 return MCDisassembler::Fail;
2454
2455 unsigned RegRs;
2456 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6())
2457 RegRs = fieldFromInstruction(Insn, 0, 2) |
2458 (fieldFromInstruction(Insn, 3, 1) << 2);
2459 else
2460 RegRs = fieldFromInstruction(Insn, 1, 3);
2461 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
2462 MCDisassembler::Fail)
2463 return MCDisassembler::Fail;
2464
2465 unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
2466 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
2467 MCDisassembler::Fail)
2468 return MCDisassembler::Fail;
2469
2470 return MCDisassembler::Success;
2471 }
2472
2473 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2474 uint64_t Address, const void *Decoder) {
2475 switch (RegPair) {
2476 default:
2477 return MCDisassembler::Fail;
2478 case 0:
2479 Inst.addOperand(MCOperand::createReg(Mips::A1));
2480 Inst.addOperand(MCOperand::createReg(Mips::A2));
2481 break;
2482 case 1:
2483 Inst.addOperand(MCOperand::createReg(Mips::A1));
2484 Inst.addOperand(MCOperand::createReg(Mips::A3));
2485 break;
2486 case 2:
2487 Inst.addOperand(MCOperand::createReg(Mips::A2));
2488 Inst.addOperand(MCOperand::createReg(Mips::A3));
2489 break;
2490 case 3:
2491 Inst.addOperand(MCOperand::createReg(Mips::A0));
2492 Inst.addOperand(MCOperand::createReg(Mips::S5));
2493 break;
2494 case 4:
2495 Inst.addOperand(MCOperand::createReg(Mips::A0));
2496 Inst.addOperand(MCOperand::createReg(Mips::S6));
2497 break;
2498 case 5:
2499 Inst.addOperand(MCOperand::createReg(Mips::A0));
2500 Inst.addOperand(MCOperand::createReg(Mips::A1));
2501 break;
2502 case 6:
2503 Inst.addOperand(MCOperand::createReg(Mips::A0));
2504 Inst.addOperand(MCOperand::createReg(Mips::A2));
2505 break;
2506 case 7:
2507 Inst.addOperand(MCOperand::createReg(Mips::A0));
2508 Inst.addOperand(MCOperand::createReg(Mips::A3));
2509 break;
2510 }
2511
2512 return MCDisassembler::Success;
2513 }
2514
2515 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2516 uint64_t Address, const void *Decoder) {
2517 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2518 return MCDisassembler::Success;
2519 }
2520
2521 template <typename InsnType>
2522 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
2523 uint64_t Address,
2524 const void *Decoder) {
2525 // We have:
2526 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
2527 // Invalid if rt == 0
2528 // BGTZALC_MMR6 if rs == 0 && rt != 0
2529 // BLTZALC_MMR6 if rs != 0 && rs == rt
2530 // BLTUC_MMR6 if rs != 0 && rs != rt
2531
2532 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2533 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2534 InsnType Imm = 0;
2535 bool HasRs = false;
2536 bool HasRt = false;
2537
2538 if (Rt == 0)
2539 return MCDisassembler::Fail;
2540 else if (Rs == 0) {
2541 MI.setOpcode(Mips::BGTZALC_MMR6);
2542 HasRt = true;
2543 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2544 }
2545 else if (Rs == Rt) {
2546 MI.setOpcode(Mips::BLTZALC_MMR6);
2547 HasRs = true;
2548 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2549 }
2550 else {
2551 MI.setOpcode(Mips::BLTUC_MMR6);
2552 HasRs = true;
2553 HasRt = true;
2554 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2555 }
2556
2557 if (HasRs)
2558 MI.addOperand(
2559 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2560
2561 if (HasRt)
2562 MI.addOperand(
2563 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2564
2565 MI.addOperand(MCOperand::createImm(Imm));
2566
2567 return MCDisassembler::Success;
2568 }
2569
2570 template <typename InsnType>
2571 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
2572 uint64_t Address,
2573 const void *Decoder) {
2574 // We have:
2575 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
2576 // Invalid if rt == 0
2577 // BLEZALC_MMR6 if rs == 0 && rt != 0
2578 // BGEZALC_MMR6 if rs == rt && rt != 0
2579 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
2580
2581 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2582 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2583 InsnType Imm = 0;
2584 bool HasRs = false;
2585
2586 if (Rt == 0)
2587 return MCDisassembler::Fail;
2588 else if (Rs == 0) {
2589 MI.setOpcode(Mips::BLEZALC_MMR6);
2590 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2591 }
2592 else if (Rs == Rt) {
2593 MI.setOpcode(Mips::BGEZALC_MMR6);
2594 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2595 }
2596 else {
2597 HasRs = true;
2598 MI.setOpcode(Mips::BGEUC_MMR6);
2599 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2600 }
2601
2602 if (HasRs)
2603 MI.addOperand(
2604 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2605 MI.addOperand(
2606 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2607
2608 MI.addOperand(MCOperand::createImm(Imm));
2609
2610 return MCDisassembler::Success;
2611 }
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