1 //===- P9InstrResources.td - P9 Instruction Resource Defs -*- tablegen -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the resources required by P9 instructions. This is part of
10 // the P9 processor model used for instruction scheduling. This file should
11 // contain all the instructions that may be used on Power 9. This is not
12 // just instructions that are new on Power 9 but also instructions that were
13 // available on earlier architectures and are still used in Power 9.
15 // The makeup of the P9 CPU is modeled as follows:
16 // - Each CPU is made up of two superslices.
17 // - Each superslice is made up of two slices. Therefore, there are 4 slices
19 // - Up to 6 instructions can be dispatched to each CPU. Three per superslice.
21 // - One CY (Crypto) unit P9_CY_*
22 // - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_*
23 // - Two PM (Permute) units. One on each superslice. P9_PM_*
24 // - Two DIV (Fixed Point Divide) units. One on each superslize. P9_DIV_*
25 // - Four ALU (Fixed Point Arithmetic) units. One on each slice. P9_ALU_*
26 // - Four DP (Floating Point) units. One on each slice. P9_DP_*
27 // This also includes fixed point multiply add.
28 // - Four AGEN (Address Generation) units. One for each slice. P9_AGEN_*
29 // - Four Load/Store Queues. P9_LS_*
30 // - Each set of instructions will require a number of these resources.
31 //===----------------------------------------------------------------------===//
33 // Two cycle ALU vector operation that uses an entire superslice.
34 // Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
35 // (EXECE, EXECO) and 1 dispatch (DISP) to the given superslice.
36 def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
38 (instregex "VADDU(B|H|W|D)M$"),
39 (instregex "VAND(C)?$"),
40 (instregex "VEXTS(B|H|W)2(D|W)(s)?$"),
41 (instregex "V_SET0(B|H)?$"),
42 (instregex "VS(R|L)(B|H|W|D)$"),
43 (instregex "VSUBU(B|H|W|D)M$"),
44 (instregex "VPOPCNT(B|H)$"),
45 (instregex "VRL(B|H|W|D)$"),
46 (instregex "VSRA(B|H|W|D)$"),
47 (instregex "XV(N)?ABS(D|S)P$"),
48 (instregex "XVCPSGN(D|S)P$"),
49 (instregex "XV(I|X)EXP(D|S)P$"),
50 (instregex "VRL(D|W)(MI|NM)$"),
51 (instregex "VMRG(E|O)W$"),
86 // Restricted Dispatch ALU operation for 3 cycles. The operation runs on a
87 // single slice. However, since it is Restricted, it requires all 3 dispatches
88 // (DISP) for that superslice.
89 def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_3SLOTS_1C],
91 (instregex "TABORT(D|W)C(I)?$"),
92 (instregex "MTFSB(0|1)$"),
93 (instregex "MFFSC(D)?RN(I)?$"),
94 (instregex "CMPRB(8)?$"),
95 (instregex "TD(I)?$"),
96 (instregex "TW(I)?$"),
97 (instregex "FCMPU(S|D)$"),
98 (instregex "XSTSTDC(S|D)P$"),
104 // Standard Dispatch ALU operation for 3 cycles. Only one slice used.
105 def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C],
107 (instregex "XSMAX(C|J)?DP$"),
108 (instregex "XSMIN(C|J)?DP$"),
109 (instregex "XSCMP(EQ|EXP|GE|GT|O|U)DP$"),
110 (instregex "CNT(L|T)Z(D|W)(8)?(o)?$"),
111 (instregex "POPCNT(D|W)$"),
112 (instregex "CMPB(8)?$"),
113 (instregex "SETB(8)?$"),
121 // Standard Dispatch ALU operation for 2 cycles. Only one slice used.
122 def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
124 (instregex "S(L|R)D$"),
125 (instregex "SRAD(I)?$"),
126 (instregex "EXTSWSLI_32_64$"),
127 (instregex "MFV(S)?RD$"),
128 (instregex "MTVSRD$"),
129 (instregex "MTVSRW(A|Z)$"),
130 (instregex "CMP(WI|LWI|W|LW)(8)?$"),
131 (instregex "CMP(L)?D(I)?$"),
132 (instregex "SUBF(I)?C(8)?$"),
133 (instregex "ANDI(S)?o(8)?$"),
134 (instregex "ADDC(8)?$"),
135 (instregex "ADDIC(8)?(o)?$"),
136 (instregex "ADD(8|4)(o)?$"),
137 (instregex "ADD(E|ME|ZE)(8)?(o)?$"),
138 (instregex "SUBF(E|ME|ZE)?(8)?(o)?$"),
139 (instregex "NEG(8)?(o)?$"),
140 (instregex "POPCNTB$"),
141 (instregex "ADD(I|IS)?(8)?$"),
142 (instregex "LI(S)?(8)?$"),
143 (instregex "(X)?OR(I|IS)?(8)?(o)?$"),
144 (instregex "NAND(8)?(o)?$"),
145 (instregex "AND(C)?(8)?(o)?$"),
146 (instregex "NOR(8)?(o)?$"),
147 (instregex "OR(C)?(8)?(o)?$"),
148 (instregex "EQV(8)?(o)?$"),
149 (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(o)?$"),
150 (instregex "ADD(4|8)(TLS)?(_)?$"),
151 (instregex "NEG(8)?$"),
152 (instregex "ADDI(S)?toc(HA|L)(8)?$"),
173 // Restricted Dispatch ALU operation for 2 cycles. The operation runs on a
174 // single slice. However, since it is Restricted, it requires all 3 dispatches
175 // (DISP) for that superslice.
176 def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_3SLOTS_1C],
178 (instregex "RLDC(L|R)$"),
179 (instregex "RLWIMI(8)?$"),
180 (instregex "RLDIC(L|R)(_32)?(_64)?$"),
181 (instregex "M(F|T)OCRF(8)?$"),
182 (instregex "CR(6)?(UN)?SET$"),
183 (instregex "CR(N)?(OR|AND)(C)?$"),
184 (instregex "S(L|R)W(8)?$"),
185 (instregex "RLW(INM|NM)(8)?$"),
186 (instregex "F(N)?ABS(D|S)$"),
187 (instregex "FNEG(D|S)$"),
188 (instregex "FCPSGN(D|S)$"),
189 (instregex "SRAW(I)?$"),
190 (instregex "ISEL(8)?$"),
201 // Three cycle ALU vector operation that uses an entire superslice.
202 // Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
203 // (EXECE, EXECO) and 1 dispatch (DISP) to the given superslice.
204 def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
206 (instregex "M(T|F)VSCR$"),
207 (instregex "VCMPNEZ(B|H|W)$"),
208 (instregex "VCMPEQU(B|H|W|D)$"),
209 (instregex "VCMPNE(B|H|W)$"),
210 (instregex "VABSDU(B|H|W)$"),
211 (instregex "VADDU(B|H|W)S$"),
212 (instregex "VAVG(S|U)(B|H|W)$"),
213 (instregex "VCMP(EQ|GE|GT)FP(o)?$"),
214 (instregex "VCMPBFP(o)?$"),
215 (instregex "VC(L|T)Z(B|H|W|D)$"),
216 (instregex "VADDS(B|H|W)S$"),
217 (instregex "V(MIN|MAX)FP$"),
218 (instregex "V(MIN|MAX)(S|U)(B|H|W|D)$"),
286 // 7 cycle DP vector operation that uses an entire superslice.
287 // Uses both DP units (the even DPE and odd DPO units), two pipelines (EXECE,
288 // EXECO) and all three dispatches (DISP) to the given superslice.
289 def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
396 // 5 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
397 // dispatch units for the superslice.
398 def : InstRW<[P9_DP_5C, IP_EXEC_1C, DISP_3SLOTS_1C],
400 (instregex "MADD(HD|HDU|LD|LD8)$"),
401 (instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?$")
404 // 7 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
405 // dispatch units for the superslice.
406 def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_3SLOTS_1C],
409 (instregex "FRI(N|P|Z|M)(D|S)$"),
410 (instregex "FRE(S)?$"),
411 (instregex "FADD(S)?$"),
412 (instregex "FMSUB(S)?$"),
413 (instregex "FMADD(S)?$"),
414 (instregex "FSUB(S)?$"),
415 (instregex "FCFID(U)?(S)?$"),
416 (instregex "FCTID(U)?(Z)?$"),
417 (instregex "FCTIW(U)?(Z)?$"),
418 (instregex "FRSQRTE(S)?$"),
447 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
448 // These operations can be done in parallel. The DP is restricted so we need a
449 // full 4 dispatches.
450 def : InstRW<[P9_DP_7C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
451 DISP_3SLOTS_1C, DISP_1C],
453 (instregex "FSEL(D|S)o$")
456 // 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
457 def : InstRW<[P9_DPOpAndALUOp_7C, IP_EXEC_1C, IP_EXEC_1C,
458 DISP_3SLOTS_1C, DISP_1C],
460 (instregex "MUL(H|L)(D|W)(U)?o$")
463 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
464 // These operations must be done sequentially.The DP is restricted so we need a
465 // full 4 dispatches.
466 def : InstRW<[P9_DPOpAndALU2Op_10C, IP_EXEC_1C, IP_EXEC_1C,
467 DISP_3SLOTS_1C, DISP_1C],
469 (instregex "FRI(N|P|Z|M)(D|S)o$"),
470 (instregex "FRE(S)?o$"),
471 (instregex "FADD(S)?o$"),
472 (instregex "FSUB(S)?o$"),
473 (instregex "F(N)?MSUB(S)?o$"),
474 (instregex "F(N)?MADD(S)?o$"),
475 (instregex "FCFID(U)?(S)?o$"),
476 (instregex "FCTID(U)?(Z)?o$"),
477 (instregex "FCTIW(U)?(Z)?o$"),
478 (instregex "FMUL(S)?o$"),
479 (instregex "FRSQRTE(S)?o$"),
483 // 7 cycle DP operation. One DP unit, one EXEC pipeline and 1 dispatch units.
484 def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C],
519 // Three Cycle PM operation. Only one PM unit per superslice so we use the whole
520 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
522 def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C],
524 (instregex "LVS(L|R)$"),
525 (instregex "VSPLTIS(W|H|B)$"),
526 (instregex "VSPLT(W|H|B)(s)?$"),
527 (instregex "V_SETALLONES(B|H)?$"),
528 (instregex "VEXTRACTU(B|H|W)$"),
529 (instregex "VINSERT(B|H|W|D)$"),
627 // 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
628 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
630 def : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
651 // 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
652 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
654 def : InstRW<[P9_DFU_23C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
659 // 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
660 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
662 def : InstRW<[P9_DFU_24C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
676 // 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
677 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
679 def : InstRW<[P9_DFU_37C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
684 // 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
685 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
687 def : InstRW<[P9_DFU_58C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
693 // 76 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
694 // superslice. That includes both exec pipelines (EXECO, EXECE) and all three
696 def : InstRW<[P9_DFU_76C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
702 // 6 Cycle Load uses a single slice.
703 def : InstRW<[P9_LS_6C, IP_AGEN_1C, DISP_1C],
705 (instregex "LXVL(L)?")
708 // 5 Cycle Load uses a single slice.
709 def : InstRW<[P9_LS_5C, IP_AGEN_1C, DISP_1C],
711 (instregex "LVE(B|H|W)X$"),
712 (instregex "LVX(L)?"),
713 (instregex "LXSI(B|H)ZX$"),
727 // 4 Cycle Load uses a single slice.
728 def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_1C],
730 (instregex "DCB(F|T|ST)(EP)?$"),
731 (instregex "DCBZ(L)?(EP)?$"),
732 (instregex "DCBTST(EP)?$"),
733 (instregex "CP_COPY(8)?$"),
734 (instregex "CP_PASTE(8)?$"),
735 (instregex "ICBI(EP)?$"),
736 (instregex "ICBT(LS)?$"),
737 (instregex "LBARX(L)?$"),
738 (instregex "LBZ(CIX|8|X|X8|XTLS|XTLS_32)?(_)?$"),
739 (instregex "LD(ARX|ARXL|BRX|CIX|X|XTLS)?(_)?$"),
740 (instregex "LH(A|B)RX(L)?(8)?$"),
741 (instregex "LHZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"),
742 (instregex "LWARX(L)?$"),
743 (instregex "LWBRX(8)?$"),
744 (instregex "LWZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"),
756 // 4 Cycle Restricted load uses a single slice but the dispatch for the whole
758 def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_3SLOTS_1C],
765 // Cracked Load Instructions.
766 // Load instructions that can be done in parallel.
767 def : InstRW<[P9_LS_4C, P9_LS_4C, IP_AGEN_1C, IP_AGEN_1C,
778 // Cracked Load Instruction.
779 // Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
780 // operations can be run in parallel.
781 def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_EXEC_1C, IP_AGEN_1C,
782 DISP_PAIR_1C, DISP_PAIR_1C],
784 (instregex "L(W|H)ZU(X)?(8)?$")
787 // Cracked TEND Instruction.
788 // Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
789 // operations can be run in parallel.
790 def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_EXEC_1C, IP_AGEN_1C,
797 // Cracked Store Instruction
798 // Consecutive Store and ALU instructions. The store is restricted and requires
800 def : InstRW<[P9_StoreAndALUOp_3C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
801 DISP_3SLOTS_1C, DISP_1C],
803 (instregex "ST(B|H|W|D)CX$")
806 // Cracked Load Instruction.
807 // Two consecutive load operations for a total of 8 cycles.
808 def : InstRW<[P9_LoadAndLoadOp_8C, IP_AGEN_1C, IP_AGEN_1C,
814 // Cracked Load instruction.
815 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
816 // operations cannot be done at the same time and so their latencies are added.
817 def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
820 (instregex "LHA(X)?(8)?$"),
821 (instregex "CP_PASTE(8)?o$"),
822 (instregex "LWA(X)?(_32)?$"),
826 // Cracked Restricted Load instruction.
827 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
828 // operations cannot be done at the same time and so their latencies are added.
829 // Full 6 dispatches are required as this is both cracked and restricted.
830 def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
831 DISP_3SLOTS_1C, DISP_3SLOTS_1C],
836 // Cracked Load instruction.
837 // Requires consecutive Load and ALU pieces totaling 7 cycles. The Load and ALU
838 // operations cannot be done at the same time and so their latencies are added.
839 // Full 4 dispatches are required as this is a cracked instruction.
840 def : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
846 // Cracked Load instruction.
847 // Requires consecutive Load (4 cycles) and ALU (3 cycles) pieces totaling 7
848 // cycles. The Load and ALU operations cannot be done at the same time and so
849 // their latencies are added.
850 // Full 6 dispatches are required as this is a restricted instruction.
851 def : InstRW<[P9_LoadAndALU2Op_7C, IP_AGEN_1C, IP_EXEC_1C,
852 DISP_3SLOTS_1C, DISP_3SLOTS_1C],
858 // Cracked Load instruction.
859 // Requires consecutive Load and ALU pieces totaling 8 cycles. The Load and ALU
860 // operations cannot be done at the same time and so their latencies are added.
861 // Full 4 dispatches are required as this is a cracked instruction.
862 def : InstRW<[P9_LoadAndALU2Op_8C, IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
870 // Cracked 3-Way Load Instruction
871 // Load with two ALU operations that depend on each other
872 def : InstRW<[P9_LoadAndALUOp_6C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
873 DISP_PAIR_1C, DISP_PAIR_1C, DISP_1C],
875 (instregex "LHAU(X)?(8)?$"),
879 // Cracked Load that requires the PM resource.
880 // Since the Load and the PM cannot be done at the same time the latencies are
881 // added. Requires 8 cycles. Since the PM requires the full superslice we need
882 // both EXECE, EXECO pipelines as well as 1 dispatch for the PM. The Load
883 // requires the remaining 1 dispatch.
884 def : InstRW<[P9_LoadAndPMOp_8C, IP_AGEN_1C, IP_EXECE_1C, IP_EXECO_1C,
892 // Single slice Restricted store operation. The restricted operation requires
893 // all three dispatches for the superslice.
894 def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_3SLOTS_1C],
896 (instregex "STF(S|D|IWX|SX|DX)$"),
897 (instregex "STXS(D|DX|SPX|IWX|IBX|IHX|SP)(v)?$"),
898 (instregex "STW(8)?$"),
899 (instregex "(D|X)FSTORE(f32|f64)$"),
900 (instregex "ST(W|H|D)BRX$"),
901 (instregex "ST(B|H|D)(8)?$"),
902 (instregex "ST(B|W|H|D)(CI)?X(TLS|TLS_32)?(8)?(_)?$"),
910 // Vector Store Instruction
911 // Requires the whole superslice and therefore requires one dispatch
912 // as well as both the Even and Odd exec pipelines.
913 def : InstRW<[P9_LS_1C, IP_EXECE_1C, IP_EXECO_1C, IP_AGEN_1C, DISP_1C],
915 (instregex "STVE(B|H|W)X$"),
916 (instregex "STVX(L)?$"),
917 (instregex "STXV(B16X|H8X|W4X|D2X|L|LL|X)?$")
920 // 5 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
921 // superslice. That includes both exec pipelines (EXECO, EXECE) and two
923 def : InstRW<[P9_DIV_5C, IP_EXECE_1C, IP_EXECO_1C, DISP_EVEN_1C],
925 (instregex "MTCTR(8)?(loop)?$"),
926 (instregex "MTLR(8)?$")
929 // 12 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
930 // superslice. That includes both exec pipelines (EXECO, EXECE) and two
932 def : InstRW<[P9_DIV_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_EVEN_1C],
934 (instregex "M(T|F)VRSAVE(v)?$"),
935 (instregex "M(T|F)PMR$"),
936 (instregex "M(T|F)TB(8)?$"),
937 (instregex "MF(SPR|CTR|LR)(8)?$"),
938 (instregex "M(T|F)MSR(D)?$"),
939 (instregex "MTSPR(8)?$")
942 // 16 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
943 // superslice. That includes both exec pipelines (EXECO, EXECE) and two
945 def : InstRW<[P9_DIV_16C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
952 // 24 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
953 // superslice. That includes both exec pipelines (EXECO, EXECE) and two
955 def : InstRW<[P9_DIV_24C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
966 // 40 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
967 // superslice. That includes both exec pipelines (EXECO, EXECE) and all three
969 def : InstRW<[P9_DIV_40C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
975 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
976 // and one full superslice for the DIV operation since there is only one DIV per
977 // superslice. Latency of DIV plus ALU is 26.
978 def : InstRW<[P9_IntDivAndALUOp_18C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
979 DISP_EVEN_1C, DISP_1C],
981 (instregex "DIVW(U)?(O)?o$")
984 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
985 // and one full superslice for the DIV operation since there is only one DIV per
986 // superslice. Latency of DIV plus ALU is 26.
987 def : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
988 DISP_EVEN_1C, DISP_1C],
996 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
997 // and one full superslice for the DIV operation since there is only one DIV per
998 // superslice. Latency of DIV plus ALU is 42.
999 def : InstRW<[P9_IntDivAndALUOp_42C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
1000 DISP_EVEN_1C, DISP_1C],
1006 // CR access instructions in _BrMCR, IIC_BrMCRX.
1008 // Cracked, restricted, ALU operations.
1009 // Here the two ALU ops can actually be done in parallel and therefore the
1010 // latencies are not added together. Otherwise this is like having two
1011 // instructions running together on two pipelines and 6 dispatches. ALU ops are
1013 def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
1014 DISP_3SLOTS_1C, DISP_3SLOTS_1C],
1020 // Cracked ALU operations.
1021 // Here the two ALU ops can actually be done in parallel and therefore the
1022 // latencies are not added together. Otherwise this is like having two
1023 // instructions running together on two pipelines and 2 dispatches. ALU ops are
1025 def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
1028 (instregex "ADDC(8)?o$"),
1029 (instregex "SUBFC(8)?o$")
1032 // Cracked ALU operations.
1033 // Two ALU ops can be done in parallel.
1034 // One is three cycle ALU the ohter is a two cycle ALU.
1035 // One of the ALU ops is restricted the other is not so we have a total of
1037 def : InstRW<[P9_ALU_2C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
1038 DISP_3SLOTS_1C, DISP_1C],
1040 (instregex "F(N)?ABS(D|S)o$"),
1041 (instregex "FCPSGN(D|S)o$"),
1042 (instregex "FNEG(D|S)o$"),
1046 // Cracked ALU operations.
1047 // Here the two ALU ops can actually be done in parallel and therefore the
1048 // latencies are not added together. Otherwise this is like having two
1049 // instructions running together on two pipelines and 2 dispatches.
1050 // ALU ops are 3 cycles each.
1051 def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
1057 // Cracked Restricted ALU operations.
1058 // Here the two ALU ops can actually be done in parallel and therefore the
1059 // latencies are not added together. Otherwise this is like having two
1060 // instructions running together on two pipelines and 6 dispatches.
1061 // ALU ops are 3 cycles each.
1062 def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
1063 DISP_3SLOTS_1C, DISP_3SLOTS_1C],
1065 (instregex "MTFSF(b|o)?$"),
1066 (instregex "MTFSFI(o)?$")
1069 // Cracked instruction made of two ALU ops.
1070 // The two ops cannot be done in parallel.
1071 // One of the ALU ops is restricted and takes 3 dispatches.
1072 def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C,
1073 DISP_3SLOTS_1C, DISP_1C],
1075 (instregex "RLD(I)?C(R|L)o$"),
1076 (instregex "RLW(IMI|INM|NM)(8)?o$"),
1077 (instregex "SLW(8)?o$"),
1078 (instregex "SRAW(I)?o$"),
1079 (instregex "SRW(8)?o$"),
1084 // Cracked instruction made of two ALU ops.
1085 // The two ops cannot be done in parallel.
1086 // Both of the ALU ops are restricted and take 3 dispatches.
1087 def : InstRW<[P9_ALU2OpAndALU2Op_6C, IP_EXEC_1C, IP_EXEC_1C,
1088 DISP_3SLOTS_1C, DISP_3SLOTS_1C],
1090 (instregex "MFFS(L|CE|o)?$")
1093 // Cracked ALU instruction composed of three consecutive 2 cycle loads for a
1094 // total of 6 cycles. All of the ALU operations are also restricted so each
1095 // takes 3 dispatches for a total of 9.
1096 def : InstRW<[P9_ALUOpAndALUOpAndALUOp_6C, IP_EXEC_1C, IP_EXEC_1C, IP_EXEC_1C,
1097 DISP_3SLOTS_1C, DISP_3SLOTS_1C, DISP_3SLOTS_1C],
1099 (instregex "MFCR(8)?$")
1102 // Cracked instruction made of two ALU ops.
1103 // The two ops cannot be done in parallel.
1104 def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
1106 (instregex "EXTSWSLI_32_64o$"),
1107 (instregex "SRAD(I)?o$"),
1114 // 33 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1115 def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_3SLOTS_1C],
1120 // 33 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1121 def : InstRW<[P9_DPOpAndALU2Op_36C_8, IP_EXEC_1C, IP_EXEC_1C,
1122 DISP_3SLOTS_1C, DISP_1C],
1127 // 36 Cycle DP Instruction.
1128 // Instruction can be done on a single slice.
1129 def : InstRW<[P9_DP_36C_10, IP_EXEC_1C, DISP_1C],
1134 // 36 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1135 def : InstRW<[P9_DP_36C_10, IP_EXEC_1C, DISP_3SLOTS_1C],
1140 // 36 Cycle DP Vector Instruction.
1141 def : InstRW<[P9_DPE_36C_10, P9_DPO_36C_10, IP_EXECE_1C, IP_EXECO_1C,
1147 // 27 Cycle DP Vector Instruction.
1148 def : InstRW<[P9_DPE_27C_10, P9_DPO_27C_10, IP_EXECE_1C, IP_EXECO_1C,
1154 // 36 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1155 def : InstRW<[P9_DPOpAndALU2Op_39C_10, IP_EXEC_1C, IP_EXEC_1C,
1156 DISP_3SLOTS_1C, DISP_1C],
1161 // 26 Cycle DP Instruction.
1162 def : InstRW<[P9_DP_26C_5, IP_EXEC_1C, DISP_1C],
1167 // 26 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1168 def : InstRW<[P9_DP_26C_5, IP_EXEC_1C, DISP_3SLOTS_1C],
1173 // 26 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1174 def : InstRW<[P9_DPOpAndALU2Op_29C_5, IP_EXEC_1C, IP_EXEC_1C,
1175 DISP_3SLOTS_1C, DISP_1C],
1180 // 33 Cycle DP Instruction. Takes one slice and 1 dispatch.
1181 def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_1C],
1186 // 22 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1187 def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_3SLOTS_1C],
1192 // 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
1193 def : InstRW<[P9_DPOpAndALU2Op_25C_5, IP_EXEC_1C, IP_EXEC_1C,
1194 DISP_3SLOTS_1C, DISP_1C],
1199 // 22 Cycle DP Instruction. Takes one slice and 1 dispatch.
1200 def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_1C],
1205 // 24 Cycle DP Vector Instruction. Takes one full superslice.
1206 // Includes both EXECE, EXECO pipelines and 1 dispatch for the given
1208 def : InstRW<[P9_DPE_24C_8, P9_DPO_24C_8, IP_EXECE_1C, IP_EXECO_1C,
1214 // 33 Cycle DP Vector Instruction. Takes one full superslice.
1215 // Includes both EXECE, EXECO pipelines and 1 dispatch for the given
1217 def : InstRW<[P9_DPE_33C_8, P9_DPO_33C_8, IP_EXECE_1C, IP_EXECO_1C,
1223 // Instruction cracked into three pieces. One Load and two ALU operations.
1224 // The Load and one of the ALU ops cannot be run at the same time and so the
1225 // latencies are added together for 6 cycles. The remainaing ALU is 2 cycles.
1226 // Both the load and the ALU that depends on it are restricted and so they take
1227 // a total of 7 dispatches. The final 2 dispatches come from the second ALU op.
1228 // The two EXEC pipelines are for the 2 ALUs while the AGEN is for the load.
1229 def : InstRW<[P9_LoadAndALU2Op_7C, P9_ALU_2C,
1230 IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
1231 DISP_3SLOTS_1C, DISP_3SLOTS_1C, DISP_1C],
1233 (instregex "LF(SU|SUX)$")
1236 // Cracked instruction made up of a Store and an ALU. The ALU does not depend on
1237 // the store and so it can be run at the same time as the store. The store is
1239 def : InstRW<[P9_LS_1C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
1240 DISP_3SLOTS_1C, DISP_1C],
1242 (instregex "STF(S|D)U(X)?$"),
1243 (instregex "ST(B|H|W|D)U(X)?(8)?$")
1246 // Cracked instruction made up of a Load and an ALU. The ALU does not depend on
1247 // the load and so it can be run at the same time as the load.
1248 def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C,
1249 DISP_PAIR_1C, DISP_PAIR_1C],
1251 (instregex "LBZU(X)?(8)?$"),
1252 (instregex "LDU(X)?$")
1255 // Cracked instruction made up of a Load and an ALU. The ALU does not depend on
1256 // the load and so it can be run at the same time as the load. The load is also
1257 // restricted. 3 dispatches are from the restricted load while the other two
1258 // are from the ALU. The AGEN pipeline is from the load and the EXEC pipeline
1259 // is required for the ALU.
1260 def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C,
1261 DISP_3SLOTS_1C, DISP_1C],
1263 (instregex "LF(DU|DUX)$")
1266 // Crypto Instructions
1268 // 6 Cycle CY operation. Only one CY unit per CPU so we use a whole
1269 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
1271 def : InstRW<[P9_CY_6C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C],
1273 (instregex "VPMSUM(B|H|W|D)$"),
1274 (instregex "V(N)?CIPHER(LAST)?$"),
1278 // Branch Instructions
1281 def : InstRW<[P9_BR_2C, DISP_BR_1C],
1283 (instregex "BCCCTR(L)?(8)?$"),
1284 (instregex "BCCL(A|R|RL)?$"),
1285 (instregex "BCCTR(L)?(8)?(n)?$"),
1286 (instregex "BD(N)?Z(8|A|Am|Ap|m|p)?$"),
1287 (instregex "BD(N)?ZL(A|Am|Ap|R|R8|RL|RLm|RLp|Rm|Rp|m|p)?$"),
1288 (instregex "BL(_TLS|_NOP)?$"),
1289 (instregex "BL8(_TLS|_NOP|_NOP_TLS|_TLS_)?$"),
1290 (instregex "BLA(8|8_NOP)?$"),
1291 (instregex "BLR(8|L)?$"),
1292 (instregex "TAILB(A)?(8)?$"),
1293 (instregex "TAILBCTR(8)?$"),
1294 (instregex "gBC(A|Aat|CTR|CTRL|L|LA|LAat|LR|LRL|Lat|at)?$"),
1295 (instregex "BCLR(L)?(n)?$"),
1296 (instregex "BCTR(L)?(8)?$"),
1310 // Five Cycle Branch with a 2 Cycle ALU Op
1311 // Operations must be done consecutively and not in parallel.
1312 def : InstRW<[P9_BROpAndALUOp_7C, IP_EXEC_1C, DISP_BR_1C, DISP_1C],
1317 // Special Extracted Instructions For Atomics
1320 def : InstRW<[P9_LS_1C, P9_LS_1C, P9_LS_4C, P9_LS_4C, P9_LS_4C,
1321 IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C, IP_AGEN_1C, IP_AGEN_1C,
1322 IP_AGEN_1C, IP_AGEN_1C, DISP_1C, DISP_3SLOTS_1C,
1323 DISP_3SLOTS_1C, DISP_1C, DISP_1C, DISP_1C],
1325 (instregex "L(D|W)AT$")
1329 def : InstRW<[P9_LS_1C, P9_LS_4C, P9_LS_4C, IP_EXEC_1C, IP_AGEN_1C, IP_AGEN_1C,
1330 IP_AGEN_1C, DISP_1C, DISP_3SLOTS_1C, DISP_1C],
1332 (instregex "ST(D|W)AT$")
1335 // Signal Processing Engine (SPE) Instructions
1336 // These instructions are not supported on Power 9
1345 (instregex "EVADD(I)?W$"),
1346 (instregex "EVADD(SM|SS|UM|US)IAAW$"),
1347 (instregex "EVAND(C)?$"),
1348 (instregex "EVCMP(EQ|GTS|GTU|LTS|LTU)$"),
1349 (instregex "EVCNTL(S|Z)W$"),
1350 (instregex "EVDIVW(S|U)$"),
1351 (instregex "EVEXTS(B|H)$"),
1352 (instregex "EVLD(H|W|D)(X)?$"),
1353 (instregex "EVLHH(E|OS|OU)SPLAT(X)?$"),
1354 (instregex "EVLWHE(X)?$"),
1355 (instregex "EVLWHO(S|U)(X)?$"),
1356 (instregex "EVLW(H|W)SPLAT(X)?$"),
1357 (instregex "EVMERGE(HI|LO|HILO|LOHI)$"),
1358 (instregex "EVMHEG(S|U)M(F|I)A(A|N)$"),
1359 (instregex "EVMHES(M|S)(F|I)(A|AA|AAW|ANW)?$"),
1360 (instregex "EVMHEU(M|S)I(A|AA|AAW|ANW)?$"),
1361 (instregex "EVMHOG(U|S)M(F|I)A(A|N)$"),
1362 (instregex "EVMHOS(M|S)(F|I)(A|AA|AAW|ANW)?$"),
1363 (instregex "EVMHOU(M|S)I(A|AA|ANW|AAW)?$"),
1364 (instregex "EVMWHS(M|S)(F|FA|I|IA)$"),
1365 (instregex "EVMWHUMI(A)?$"),
1366 (instregex "EVMWLS(M|S)IA(A|N)W$"),
1367 (instregex "EVMWLU(M|S)I(A|AA|AAW|ANW)?$"),
1368 (instregex "EVMWSM(F|I)(A|AA|AN)?$"),
1369 (instregex "EVMWSSF(A|AA|AN)?$"),
1370 (instregex "EVMWUMI(A|AA|AN)?$"),
1371 (instregex "EV(N|X)?OR(C)?$"),
1372 (instregex "EVR(LW|LWI|NDW)$"),
1373 (instregex "EVSLW(I)?$"),
1374 (instregex "EVSPLAT(F)?I$"),
1375 (instregex "EVSRW(I)?(S|U)$"),
1376 (instregex "EVST(DD|DH|DW|WHE|WHO|WWE|WWO)(X)?$"),
1377 (instregex "EVSUBF(S|U)(M|S)IAAW$"),
1378 (instregex "EVSUB(I)?FW$")
1379 )> { let Unsupported = 1; }
1381 // General Instructions without scheduling support.
1384 (instregex "(H)?RFI(D)?$"),
1385 (instregex "DSS(ALL)?$"),
1386 (instregex "DST(ST)?(T)?(64)?$"),
1387 (instregex "ICBL(C|Q)$"),
1388 (instregex "L(W|H|B)EPX$"),
1389 (instregex "ST(W|H|B)EPX$"),
1390 (instregex "(L|ST)FDEPX$"),
1391 (instregex "M(T|F)SR(IN)?$"),
1392 (instregex "M(T|F)DCR$"),
1393 (instregex "NOP_GT_PWR(6|7)$"),
1394 (instregex "TLB(IA|IVAX|SX|SX2|SX2D|LD|LI|RE|RE2|WE|WE2)$"),
1395 (instregex "WRTEE(I)?$"),
1414 )> { let Unsupported = 1; }