lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This is a target description file for the Intel i386 architecture, referred
  10 // to here as the "X86" architecture.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing...
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // X86 Subtarget state
  20 //
  21
  22 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  23                                   "64-bit mode (x86_64)">;
  24 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  25                                   "32-bit mode (80386)">;
  26 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  27                                   "16-bit mode (i8086)">;
  28
  29 //===----------------------------------------------------------------------===//
  30 // X86 Subtarget features
  31 //===----------------------------------------------------------------------===//
  32
  33 def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
  34                                       "Enable X87 float instructions">;
  35
  36 def FeatureNOPL    : SubtargetFeature<"nopl", "HasNOPL", "true",
  37                                       "Enable NOPL instruction">;
  38
  39 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  40                                       "Enable conditional move instructions">;
  41
  42 def FeatureCMPXCHG8B : SubtargetFeature<"cx8", "HasCmpxchg8b", "true",
  43                                         "Support CMPXCHG8B instructions">;
  44
  45 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  46                                        "Support POPCNT instruction">;
  47
  48 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  49                                       "Support fxsave/fxrestore instructions">;
  50
  51 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  52                                        "Support xsave instructions">;
  53
  54 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  55                                        "Support xsaveopt instructions">;
  56
  57 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  58                                        "Support xsavec instructions">;
  59
  60 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  61                                        "Support xsaves instructions">;
  62
  63 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  64                                       "Enable SSE instructions">;
  65 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  66                                       "Enable SSE2 instructions",
  67                                       [FeatureSSE1]>;
  68 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  69                                       "Enable SSE3 instructions",
  70                                       [FeatureSSE2]>;
  71 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  72                                       "Enable SSSE3 instructions",
  73                                       [FeatureSSE3]>;
  74 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  75                                       "Enable SSE 4.1 instructions",
  76                                       [FeatureSSSE3]>;
  77 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  78                                       "Enable SSE 4.2 instructions",
  79                                       [FeatureSSE41]>;
  80 // The MMX subtarget feature is separate from the rest of the SSE features
  81 // because it's important (for odd compatibility reasons) to be able to
  82 // turn it off explicitly while allowing SSE+ to be on.
  83 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  84                                       "Enable MMX instructions">;
  85 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  86                                       "Enable 3DNow! instructions",
  87                                       [FeatureMMX]>;
  88 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  89                                       "Enable 3DNow! Athlon instructions",
  90                                       [Feature3DNow]>;
  91 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  92 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  93 // without disabling 64-bit mode. Nothing should imply this feature bit. It
  94 // is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.
  95 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  96                                       "Support 64-bit instructions">;
  97 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  98                                       "64-bit with cmpxchg16b",
  99                                       [FeatureCMPXCHG8B]>;
 100 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
 101                                        "SHLD instruction is slow">;
 102 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
 103                                         "PMULLD instruction is slow">;
 104 def FeatureSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
 105                                           "true",
 106                                           "PMADDWD is slower than PMULLD">;
 107 // FIXME: This should not apply to CPUs that do not have SSE.
 108 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 109                                 "IsUAMem16Slow", "true",
 110                                 "Slow unaligned 16-byte memory access">;
 111 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 112                                 "IsUAMem32Slow", "true",
 113                                 "Slow unaligned 32-byte memory access">;
 114 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 115                                       "Support SSE 4a instructions",
 116                                       [FeatureSSE3]>;
 117
 118 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 119                                       "Enable AVX instructions",
 120                                       [FeatureSSE42]>;
 121 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 122                                       "Enable AVX2 instructions",
 123                                       [FeatureAVX]>;
 124 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 125                                       "Enable three-operand fused multiple-add",
 126                                       [FeatureAVX]>;
 127 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 128                        "Support 16-bit floating point conversion instructions",
 129                        [FeatureAVX]>;
 130 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 131                                       "Enable AVX-512 instructions",
 132                                       [FeatureAVX2, FeatureFMA, FeatureF16C]>;
 133 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 134                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 135                                       [FeatureAVX512]>;
 136 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 137                       "Enable AVX-512 Conflict Detection Instructions",
 138                                       [FeatureAVX512]>;
 139 def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
 140                        "true", "Enable AVX-512 Population Count Instructions",
 141                                       [FeatureAVX512]>;
 142 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 143                       "Enable AVX-512 PreFetch Instructions",
 144                                       [FeatureAVX512]>;
 145 def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1",
 146                                    "true",
 147                                    "Prefetch with Intent to Write and T1 Hint">;
 148 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 149                       "Enable AVX-512 Doubleword and Quadword Instructions",
 150                                       [FeatureAVX512]>;
 151 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 152                       "Enable AVX-512 Byte and Word Instructions",
 153                                       [FeatureAVX512]>;
 154 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 155                       "Enable AVX-512 Vector Length eXtensions",
 156                                       [FeatureAVX512]>;
 157 def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
 158                       "Enable AVX-512 Vector Byte Manipulation Instructions",
 159                                       [FeatureBWI]>;
 160 def FeatureVBMI2    : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",
 161                       "Enable AVX-512 further Vector Byte Manipulation Instructions",
 162                                       [FeatureBWI]>;
 163 def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
 164                       "Enable AVX-512 Integer Fused Multiple-Add",
 165                                       [FeatureAVX512]>;
 166 def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
 167                       "Enable protection keys">;
 168 def FeatureVNNI    : SubtargetFeature<"avx512vnni", "HasVNNI", "true",
 169                           "Enable AVX-512 Vector Neural Network Instructions",
 170                                       [FeatureAVX512]>;
 171 def FeatureBF16    : SubtargetFeature<"avx512bf16", "HasBF16", "true",
 172                            "Support bfloat16 floating point",
 173                                       [FeatureBWI]>;
 174 def FeatureBITALG  : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
 175                        "Enable AVX-512 Bit Algorithms",
 176                         [FeatureBWI]>;
 177 def FeatureVP2INTERSECT  : SubtargetFeature<"avx512vp2intersect",
 178                                             "HasVP2INTERSECT", "true",
 179                                             "Enable AVX-512 vp2intersect",
 180                                             [FeatureAVX512]>;
 181 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 182                          "Enable packed carry-less multiplication instructions",
 183                                [FeatureSSE2]>;
 184 def FeatureGFNI    : SubtargetFeature<"gfni", "HasGFNI", "true",
 185                          "Enable Galois Field Arithmetic Instructions",
 186                                [FeatureSSE2]>;
 187 def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true",
 188                                          "Enable vpclmulqdq instructions",
 189                                          [FeatureAVX, FeaturePCLMUL]>;
 190 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 191                                       "Enable four-operand fused multiple-add",
 192                                       [FeatureAVX, FeatureSSE4A]>;
 193 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 194                                       "Enable XOP instructions",
 195                                       [FeatureFMA4]>;
 196 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 197                                           "HasSSEUnalignedMem", "true",
 198                       "Allow unaligned memory operands with SSE instructions">;
 199 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 200                                       "Enable AES instructions",
 201                                       [FeatureSSE2]>;
 202 def FeatureVAES    : SubtargetFeature<"vaes", "HasVAES", "true",
 203                        "Promote selected AES instructions to AVX512/AVX registers",
 204                         [FeatureAVX, FeatureAES]>;
 205 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 206                                       "Enable TBM instructions">;
 207 def FeatureLWP     : SubtargetFeature<"lwp", "HasLWP", "true",
 208                                       "Enable LWP instructions">;
 209 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 210                                       "Support MOVBE instruction">;
 211 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 212                                       "Support RDRAND instruction">;
 213 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 214                                        "Support FS/GS Base instructions">;
 215 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 216                                       "Support LZCNT instruction">;
 217 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 218                                       "Support BMI instructions">;
 219 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 220                                       "Support BMI2 instructions">;
 221 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 222                                       "Support RTM instructions">;
 223 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 224                                       "Support ADX instructions">;
 225 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 226                                       "Enable SHA instructions",
 227                                       [FeatureSSE2]>;
 228 def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
 229                        "Support CET Shadow-Stack instructions">;
 230 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 231                                       "Support PRFCHW instructions">;
 232 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 233                                       "Support RDSEED instruction">;
 234 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 235                                        "Support LAHF and SAHF instructions">;
 236 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
 237                                       "Enable MONITORX/MWAITX timer functionality">;
 238 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
 239                                       "Enable Cache Line Zero">;
 240 def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
 241                                       "Enable Cache Demote">;
 242 def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
 243                                       "Support ptwrite instruction">;
 244 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 245                                       "Support MPX instructions">;
 246 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 247                                      "Use LEA for adjusting the stack pointer">;
 248 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 249                                      "HasSlowDivide32", "true",
 250                                      "Use 8-bit divide for positive values less than 256">;
 251 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
 252                                      "HasSlowDivide64", "true",
 253                                      "Use 32-bit divide for positive values less than 2^32">;
 254 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 255                                      "PadShortFunctions", "true",
 256                                      "Pad short functions">;
 257 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
 258                                       "Invalidate Process-Context Identifier">;
 259 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 260                                       "Enable Software Guard Extensions">;
 261 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
 262                                       "Flush A Cache Line Optimized">;
 263 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
 264                                       "Cache Line Write Back">;
 265 def FeatureWBNOINVD    : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
 266                                       "Write Back No Invalidate">;
 267 def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
 268                                     "Support RDPID instructions">;
 269 def FeatureWAITPKG  : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
 270                                       "Wait and pause enhancements">;
 271 def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
 272                                      "Has ENQCMD instructions">;
 273 // On some processors, instructions that implicitly take two memory operands are
 274 // slow. In practice, this means that CALL, PUSH, and POP with memory operands
 275 // should be avoided in favor of a MOV + register CALL/PUSH/POP.
 276 def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
 277                                      "SlowTwoMemOps", "true",
 278                                      "Two memory operand instructions are slow">;
 279 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 280                                    "LEA instruction needs inputs at AG stage">;
 281 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 282                                    "LEA instruction with certain arguments is slow">;
 283 def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
 284                                    "LEA instruction with 3 ops or certain registers is slow">;
 285 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 286                                    "INC and DEC instructions are slower than ADD and SUB">;
 287 def FeatureSoftFloat
 288     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 289                        "Use software floating point features">;
 290 def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
 291                                      "HasPOPCNTFalseDeps", "true",
 292                                      "POPCNT has a false dependency on dest register">;
 293 def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
 294                                      "HasLZCNTFalseDeps", "true",
 295                                      "LZCNT/TZCNT have a false dependency on dest register">;
 296 def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
 297                                       "platform configuration instruction">;
 298 // On recent X86 (port bound) processors, its preferable to combine to a single shuffle
 299 // using a variable mask over multiple fixed shuffles.
 300 def FeatureFastVariableShuffle
 301     : SubtargetFeature<"fast-variable-shuffle",
 302                        "HasFastVariableShuffle",
 303                        "true", "Shuffles with variable masks are fast">;
 304 // On some X86 processors, there is no performance hazard to writing only the
 305 // lower parts of a YMM or ZMM register without clearing the upper part.
 306 def FeatureFastPartialYMMorZMMWrite
 307     : SubtargetFeature<"fast-partial-ymm-or-zmm-write",
 308                        "HasFastPartialYMMorZMMWrite",
 309                        "true", "Partial writes to YMM/ZMM registers are fast">;
 310 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
 311 // than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
 312 // vector FSQRT has higher throughput than the corresponding NR code.
 313 // The idea is that throughput bound code is likely to be vectorized, so for
 314 // vectorized code we should care about the throughput of SQRT operations.
 315 // But if the code is scalar that probably means that the code has some kind of
 316 // dependency and we should care more about reducing the latency.
 317 def FeatureFastScalarFSQRT
 318     : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
 319                        "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
 320 def FeatureFastVectorFSQRT
 321     : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
 322                        "true", "Vector SQRT is fast (disable Newton-Raphson)">;
 323 // If lzcnt has equivalent latency/throughput to most simple integer ops, it can
 324 // be used to replace test/set sequences.
 325 def FeatureFastLZCNT
 326     : SubtargetFeature<
 327           "fast-lzcnt", "HasFastLZCNT", "true",
 328           "LZCNT instructions are as fast as most simple integer ops">;
 329 // If the target can efficiently decode NOPs upto 11-bytes in length.
 330 def FeatureFast11ByteNOP
 331     : SubtargetFeature<
 332           "fast-11bytenop", "HasFast11ByteNOP", "true",
 333           "Target can quickly decode up to 11 byte NOPs">;
 334 // If the target can efficiently decode NOPs upto 15-bytes in length.
 335 def FeatureFast15ByteNOP
 336     : SubtargetFeature<
 337           "fast-15bytenop", "HasFast15ByteNOP", "true",
 338           "Target can quickly decode up to 15 byte NOPs">;
 339 // Sandy Bridge and newer processors can use SHLD with the same source on both
 340 // inputs to implement rotate to avoid the partial flag update of the normal
 341 // rotate instructions.
 342 def FeatureFastSHLDRotate
 343     : SubtargetFeature<
 344           "fast-shld-rotate", "HasFastSHLDRotate", "true",
 345           "SHLD can be used as a faster rotate">;
 346
 347 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
 348 // "string operations"). See "REP String Enhancement" in the Intel Software
 349 // Development Manual. This feature essentially means that REP MOVSB will copy
 350 // using the largest available size instead of copying bytes one by one, making
 351 // it at least as fast as REPMOVS{W,D,Q}.
 352 def FeatureERMSB
 353     : SubtargetFeature<
 354           "ermsb", "HasERMSB", "true",
 355           "REP MOVS/STOS are fast">;
 356
 357 // Bulldozer and newer processors can merge CMP/TEST (but not other
 358 // instructions) with conditional branches.
 359 def FeatureBranchFusion
 360     : SubtargetFeature<"branchfusion", "HasBranchFusion", "true",
 361                  "CMP/TEST can be fused with conditional branches">;
 362
 363 // Sandy Bridge and newer processors have many instructions that can be
 364 // fused with conditional branches and pass through the CPU as a single
 365 // operation.
 366 def FeatureMacroFusion
 367     : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
 368                  "Various instructions can be fused with conditional branches">;
 369
 370 // Gather is available since Haswell (AVX2 set). So technically, we can
 371 // generate Gathers on all AVX2 processors. But the overhead on HSW is high.
 372 // Skylake Client processor has faster Gathers than HSW and performance is
 373 // similar to Skylake Server (AVX-512).
 374 def FeatureHasFastGather
 375     : SubtargetFeature<"fast-gather", "HasFastGather", "true",
 376                        "Indicates if gather is reasonably fast">;
 377
 378 def FeaturePrefer256Bit
 379     : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
 380                        "Prefer 256-bit AVX instructions">;
 381
 382 // Lower indirect calls using a special construct called a `retpoline` to
 383 // mitigate potential Spectre v2 attacks against them.
 384 def FeatureRetpolineIndirectCalls
 385     : SubtargetFeature<
 386           "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true",
 387           "Remove speculation of indirect calls from the generated code">;
 388
 389 // Lower indirect branches and switches either using conditional branch trees
 390 // or using a special construct called a `retpoline` to mitigate potential
 391 // Spectre v2 attacks against them.
 392 def FeatureRetpolineIndirectBranches
 393     : SubtargetFeature<
 394           "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true",
 395           "Remove speculation of indirect branches from the generated code">;
 396
 397 // Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and
 398 // `retpoline-indirect-branches` above.
 399 def FeatureRetpoline
 400     : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true",
 401                        "Remove speculation of indirect branches from the "
 402                        "generated code, either by avoiding them entirely or "
 403                        "lowering them with a speculation blocking construct",
 404                        [FeatureRetpolineIndirectCalls,
 405                         FeatureRetpolineIndirectBranches]>;
 406
 407 // Rely on external thunks for the emitted retpoline calls. This allows users
 408 // to provide their own custom thunk definitions in highly specialized
 409 // environments such as a kernel that does boot-time hot patching.
 410 def FeatureRetpolineExternalThunk
 411     : SubtargetFeature<
 412           "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
 413           "When lowering an indirect call or branch using a `retpoline`, rely "
 414           "on the specified user provided thunk rather than emitting one "
 415           "ourselves. Only has effect when combined with some other retpoline "
 416           "feature", [FeatureRetpolineIndirectCalls]>;
 417
 418 // Direct Move instructions.
 419 def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
 420                                        "Support movdiri instruction">;
 421 def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
 422                                         "Support movdir64b instruction">;
 423
 424 def FeatureFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",
 425           "Indicates that the BEXTR instruction is implemented as a single uop "
 426           "with good throughput">;
 427
 428 // Combine vector math operations with shuffles into horizontal math
 429 // instructions if a CPU implements horizontal operations (introduced with
 430 // SSE3) with better latency/throughput than the alternative sequence.
 431 def FeatureFastHorizontalOps
 432     : SubtargetFeature<
 433         "fast-hops", "HasFastHorizontalOps", "true",
 434         "Prefer horizontal vector math instructions (haddp, phsub, etc.) over "
 435         "normal vector instructions with shuffles", [FeatureSSE3]>;
 436
 437 def FeatureFastScalarShiftMasks
 438     : SubtargetFeature<
 439         "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
 440         "Prefer a left/right scalar logical shift pair over a shift+and pair">;
 441
 442 def FeatureFastVectorShiftMasks
 443     : SubtargetFeature<
 444         "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",
 445         "Prefer a left/right vector logical shift pair over a shift+and pair">;
 446
 447 // Merge branches using three-way conditional code.
 448 def FeatureMergeToThreeWayBranch : SubtargetFeature<"merge-to-threeway-branch",
 449                                         "ThreewayBranchProfitable", "true",
 450                                         "Merge branches to a three-way "
 451                                         "conditional branch">;
 452
 453 // Bonnell
 454 def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">;
 455 // Silvermont
 456 def ProcIntelSLM  : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">;
 457 // Goldmont
 458 def ProcIntelGLM  : SubtargetFeature<"", "X86ProcFamily", "IntelGLM", "">;
 459 // Goldmont Plus
 460 def ProcIntelGLP  : SubtargetFeature<"", "X86ProcFamily", "IntelGLP", "">;
 461 // Tremont
 462 def ProcIntelTRM  : SubtargetFeature<"", "X86ProcFamily", "IntelTRM", "">;
 463
 464 //===----------------------------------------------------------------------===//
 465 // Register File Description
 466 //===----------------------------------------------------------------------===//
 467
 468 include "X86RegisterInfo.td"
 469 include "X86RegisterBanks.td"
 470
 471 //===----------------------------------------------------------------------===//
 472 // Instruction Descriptions
 473 //===----------------------------------------------------------------------===//
 474
 475 include "X86Schedule.td"
 476 include "X86InstrInfo.td"
 477 include "X86SchedPredicates.td"
 478
 479 def X86InstrInfo : InstrInfo;
 480
 481 //===----------------------------------------------------------------------===//
 482 // X86 Scheduler Models
 483 //===----------------------------------------------------------------------===//
 484
 485 include "X86ScheduleAtom.td"
 486 include "X86SchedSandyBridge.td"
 487 include "X86SchedHaswell.td"
 488 include "X86SchedBroadwell.td"
 489 include "X86ScheduleSLM.td"
 490 include "X86ScheduleZnver1.td"
 491 include "X86ScheduleBdVer2.td"
 492 include "X86ScheduleBtVer2.td"
 493 include "X86SchedSkylakeClient.td"
 494 include "X86SchedSkylakeServer.td"
 495
 496 //===----------------------------------------------------------------------===//
 497 // X86 Processor Feature Lists
 498 //===----------------------------------------------------------------------===//
 499
 500 def ProcessorFeatures {
 501   // Nehalem
 502   list<SubtargetFeature> NHMInheritableFeatures = [FeatureX87,
 503                                                    FeatureCMPXCHG8B,
 504                                                    FeatureCMOV,
 505                                                    FeatureMMX,
 506                                                    FeatureSSE42,
 507                                                    FeatureFXSR,
 508                                                    FeatureNOPL,
 509                                                    Feature64Bit,
 510                                                    FeatureCMPXCHG16B,
 511                                                    FeaturePOPCNT,
 512                                                    FeatureLAHFSAHF,
 513                                                    FeatureMacroFusion];
 514   list<SubtargetFeature> NHMSpecificFeatures = [];
 515   list<SubtargetFeature> NHMFeatures =
 516     !listconcat(NHMInheritableFeatures, NHMSpecificFeatures);
 517
 518   // Westmere
 519   list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];
 520   list<SubtargetFeature> WSMSpecificFeatures = [];
 521   list<SubtargetFeature> WSMInheritableFeatures =
 522     !listconcat(NHMInheritableFeatures, WSMAdditionalFeatures);
 523   list<SubtargetFeature> WSMFeatures =
 524     !listconcat(WSMInheritableFeatures, WSMSpecificFeatures);
 525
 526   // Sandybridge
 527   list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
 528                                                   FeatureSlowDivide64,
 529                                                   FeatureXSAVE,
 530                                                   FeatureXSAVEOPT,
 531                                                   FeatureSlow3OpsLEA,
 532                                                   FeatureFastScalarFSQRT,
 533                                                   FeatureFastSHLDRotate,
 534                                                   FeatureMergeToThreeWayBranch];
 535   list<SubtargetFeature> SNBSpecificFeatures = [FeatureSlowUAMem32,
 536                                                 FeaturePOPCNTFalseDeps];
 537   list<SubtargetFeature> SNBInheritableFeatures =
 538     !listconcat(WSMInheritableFeatures, SNBAdditionalFeatures);
 539   list<SubtargetFeature> SNBFeatures =
 540     !listconcat(SNBInheritableFeatures, SNBSpecificFeatures);
 541
 542   // Ivybridge
 543   list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND,
 544                                                   FeatureF16C,
 545                                                   FeatureFSGSBase];
 546   list<SubtargetFeature> IVBSpecificFeatures = [FeatureSlowUAMem32,
 547                                                 FeaturePOPCNTFalseDeps];
 548   list<SubtargetFeature> IVBInheritableFeatures =
 549     !listconcat(SNBInheritableFeatures, IVBAdditionalFeatures);
 550   list<SubtargetFeature> IVBFeatures =
 551     !listconcat(IVBInheritableFeatures, IVBSpecificFeatures);
 552
 553   // Haswell
 554   list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2,
 555                                                   FeatureBMI,
 556                                                   FeatureBMI2,
 557                                                   FeatureERMSB,
 558                                                   FeatureFMA,
 559                                                   FeatureINVPCID,
 560                                                   FeatureLZCNT,
 561                                                   FeatureMOVBE,
 562                                                   FeatureFastVariableShuffle];
 563   list<SubtargetFeature> HSWSpecificFeatures = [FeaturePOPCNTFalseDeps,
 564                                                 FeatureLZCNTFalseDeps];
 565   list<SubtargetFeature> HSWInheritableFeatures =
 566     !listconcat(IVBInheritableFeatures, HSWAdditionalFeatures);
 567   list<SubtargetFeature> HSWFeatures =
 568     !listconcat(HSWInheritableFeatures, HSWSpecificFeatures);
 569
 570   // Broadwell
 571   list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX,
 572                                                   FeatureRDSEED,
 573                                                   FeaturePRFCHW];
 574   list<SubtargetFeature> BDWSpecificFeatures = [FeaturePOPCNTFalseDeps,
 575                                                 FeatureLZCNTFalseDeps];
 576   list<SubtargetFeature> BDWInheritableFeatures =
 577     !listconcat(HSWInheritableFeatures, BDWAdditionalFeatures);
 578   list<SubtargetFeature> BDWFeatures =
 579     !listconcat(BDWInheritableFeatures, BDWSpecificFeatures);
 580
 581   // Skylake
 582   list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
 583                                                   FeatureMPX,
 584                                                   FeatureXSAVEC,
 585                                                   FeatureXSAVES,
 586                                                   FeatureCLFLUSHOPT,
 587                                                   FeatureFastVectorFSQRT];
 588   list<SubtargetFeature> SKLSpecificFeatures = [FeatureHasFastGather,
 589                                                 FeaturePOPCNTFalseDeps,
 590                                                 FeatureSGX];
 591   list<SubtargetFeature> SKLInheritableFeatures =
 592     !listconcat(BDWInheritableFeatures, SKLAdditionalFeatures);
 593   list<SubtargetFeature> SKLFeatures =
 594     !listconcat(SKLInheritableFeatures, SKLSpecificFeatures);
 595
 596   // Skylake-AVX512
 597   list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAVX512,
 598                                                   FeatureCDI,
 599                                                   FeatureDQI,
 600                                                   FeatureBWI,
 601                                                   FeatureVLX,
 602                                                   FeaturePKU,
 603                                                   FeatureCLWB];
 604   list<SubtargetFeature> SKXSpecificFeatures = [FeatureHasFastGather,
 605                                                 FeaturePOPCNTFalseDeps];
 606   list<SubtargetFeature> SKXInheritableFeatures =
 607     !listconcat(SKLInheritableFeatures, SKXAdditionalFeatures);
 608   list<SubtargetFeature> SKXFeatures =
 609     !listconcat(SKXInheritableFeatures, SKXSpecificFeatures);
 610
 611   // Cascadelake
 612   list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI];
 613   list<SubtargetFeature> CLXSpecificFeatures = [FeatureHasFastGather,
 614                                                 FeaturePOPCNTFalseDeps];
 615   list<SubtargetFeature> CLXInheritableFeatures =
 616     !listconcat(SKXInheritableFeatures, CLXAdditionalFeatures);
 617   list<SubtargetFeature> CLXFeatures =
 618     !listconcat(CLXInheritableFeatures, CLXSpecificFeatures);
 619
 620   // Cooperlake
 621   list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16];
 622   list<SubtargetFeature> CPXSpecificFeatures = [FeatureHasFastGather,
 623                                                 FeaturePOPCNTFalseDeps];
 624   list<SubtargetFeature> CPXInheritableFeatures =
 625     !listconcat(CLXInheritableFeatures, CPXAdditionalFeatures);
 626   list<SubtargetFeature> CPXFeatures =
 627     !listconcat(CPXInheritableFeatures, CPXSpecificFeatures);
 628
 629   // Cannonlake
 630   list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,
 631                                                   FeatureCDI,
 632                                                   FeatureDQI,
 633                                                   FeatureBWI,
 634                                                   FeatureVLX,
 635                                                   FeaturePKU,
 636                                                   FeatureVBMI,
 637                                                   FeatureIFMA,
 638                                                   FeatureSHA,
 639                                                   FeatureSGX];
 640   list<SubtargetFeature> CNLSpecificFeatures = [FeatureHasFastGather];
 641   list<SubtargetFeature> CNLInheritableFeatures =
 642     !listconcat(SKLInheritableFeatures, CNLAdditionalFeatures);
 643   list<SubtargetFeature> CNLFeatures =
 644     !listconcat(CNLInheritableFeatures, CNLSpecificFeatures);
 645
 646   // Icelake
 647   list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG,
 648                                                   FeatureVAES,
 649                                                   FeatureVBMI2,
 650                                                   FeatureVNNI,
 651                                                   FeatureVPCLMULQDQ,
 652                                                   FeatureVPOPCNTDQ,
 653                                                   FeatureGFNI,
 654                                                   FeatureCLWB,
 655                                                   FeatureRDPID];
 656   list<SubtargetFeature> ICLSpecificFeatures = [FeatureHasFastGather];
 657   list<SubtargetFeature> ICLInheritableFeatures =
 658     !listconcat(CNLInheritableFeatures, ICLAdditionalFeatures);
 659   list<SubtargetFeature> ICLFeatures =
 660     !listconcat(ICLInheritableFeatures, ICLSpecificFeatures);
 661
 662   // Icelake Server
 663   list<SubtargetFeature> ICXSpecificFeatures = [FeaturePCONFIG,
 664                                                 FeatureWBNOINVD,
 665                                                 FeatureHasFastGather];
 666   list<SubtargetFeature> ICXFeatures =
 667     !listconcat(ICLInheritableFeatures, ICXSpecificFeatures);
 668
 669   //Tigerlake
 670   list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,
 671                                                   FeatureMOVDIRI,
 672                                                   FeatureMOVDIR64B,
 673                                                   FeatureSHSTK];
 674   list<SubtargetFeature> TGLSpecificFeatures = [FeatureHasFastGather];
 675   list<SubtargetFeature> TGLInheritableFeatures =
 676     !listconcat(TGLAdditionalFeatures ,TGLSpecificFeatures);
 677   list<SubtargetFeature> TGLFeatures =
 678     !listconcat(ICLFeatures, TGLInheritableFeatures );
 679
 680   // Atom
 681   list<SubtargetFeature> AtomInheritableFeatures = [FeatureX87,
 682                                                     FeatureCMPXCHG8B,
 683                                                     FeatureCMOV,
 684                                                     FeatureMMX,
 685                                                     FeatureSSSE3,
 686                                                     FeatureFXSR,
 687                                                     FeatureNOPL,
 688                                                     Feature64Bit,
 689                                                     FeatureCMPXCHG16B,
 690                                                     FeatureMOVBE,
 691                                                     FeatureSlowTwoMemOps,
 692                                                     FeatureLAHFSAHF];
 693   list<SubtargetFeature> AtomSpecificFeatures = [ProcIntelAtom,
 694                                                  FeatureSlowUAMem16,
 695                                                  FeatureLEAForSP,
 696                                                  FeatureSlowDivide32,
 697                                                  FeatureSlowDivide64,
 698                                                  FeatureLEAUsesAG,
 699                                                  FeaturePadShortFunctions];
 700   list<SubtargetFeature> AtomFeatures =
 701     !listconcat(AtomInheritableFeatures, AtomSpecificFeatures);
 702
 703   // Silvermont
 704   list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
 705                                                   FeaturePOPCNT,
 706                                                   FeaturePCLMUL,
 707                                                   FeaturePRFCHW,
 708                                                   FeatureSlowLEA,
 709                                                   FeatureSlowIncDec,
 710                                                   FeatureRDRAND];
 711   list<SubtargetFeature> SLMSpecificFeatures = [ProcIntelSLM,
 712                                                 FeatureSlowDivide64,
 713                                                 FeatureSlowPMULLD,
 714                                                 FeaturePOPCNTFalseDeps];
 715   list<SubtargetFeature> SLMInheritableFeatures =
 716     !listconcat(AtomInheritableFeatures, SLMAdditionalFeatures);
 717   list<SubtargetFeature> SLMFeatures =
 718     !listconcat(SLMInheritableFeatures, SLMSpecificFeatures);
 719
 720   // Goldmont
 721   list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
 722                                                   FeatureMPX,
 723                                                   FeatureSHA,
 724                                                   FeatureRDSEED,
 725                                                   FeatureXSAVE,
 726                                                   FeatureXSAVEOPT,
 727                                                   FeatureXSAVEC,
 728                                                   FeatureXSAVES,
 729                                                   FeatureCLFLUSHOPT,
 730                                                   FeatureFSGSBase];
 731   list<SubtargetFeature> GLMSpecificFeatures = [ProcIntelGLM,
 732                                                 FeaturePOPCNTFalseDeps];
 733   list<SubtargetFeature> GLMInheritableFeatures =
 734     !listconcat(SLMInheritableFeatures, GLMAdditionalFeatures);
 735   list<SubtargetFeature> GLMFeatures =
 736     !listconcat(GLMInheritableFeatures, GLMSpecificFeatures);
 737
 738   // Goldmont Plus
 739   list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,
 740                                                   FeatureRDPID,
 741                                                   FeatureSGX];
 742   list<SubtargetFeature> GLPSpecificFeatures = [ProcIntelGLP];
 743   list<SubtargetFeature> GLPInheritableFeatures =
 744     !listconcat(GLMInheritableFeatures, GLPAdditionalFeatures);
 745   list<SubtargetFeature> GLPFeatures =
 746     !listconcat(GLPInheritableFeatures, GLPSpecificFeatures);
 747
 748   // Tremont
 749   list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLDEMOTE,
 750                                                   FeatureGFNI,
 751                                                   FeatureMOVDIRI,
 752                                                   FeatureMOVDIR64B,
 753                                                   FeatureWAITPKG];
 754   list<SubtargetFeature> TRMSpecificFeatures = [ProcIntelTRM];
 755   list<SubtargetFeature> TRMFeatures =
 756     !listconcat(GLPInheritableFeatures, TRMAdditionalFeatures,
 757                 TRMSpecificFeatures);
 758
 759   // Knights Landing
 760   list<SubtargetFeature> KNLFeatures = [FeatureX87,
 761                                         FeatureCMPXCHG8B,
 762                                         FeatureCMOV,
 763                                         FeatureMMX,
 764                                         FeatureFXSR,
 765                                         FeatureNOPL,
 766                                         Feature64Bit,
 767                                         FeatureCMPXCHG16B,
 768                                         FeaturePOPCNT,
 769                                         FeatureSlowDivide64,
 770                                         FeaturePCLMUL,
 771                                         FeatureXSAVE,
 772                                         FeatureXSAVEOPT,
 773                                         FeatureLAHFSAHF,
 774                                         FeatureSlow3OpsLEA,
 775                                         FeatureSlowIncDec,
 776                                         FeatureAES,
 777                                         FeatureRDRAND,
 778                                         FeatureF16C,
 779                                         FeatureFSGSBase,
 780                                         FeatureAVX512,
 781                                         FeatureERI,
 782                                         FeatureCDI,
 783                                         FeaturePFI,
 784                                         FeaturePREFETCHWT1,
 785                                         FeatureADX,
 786                                         FeatureRDSEED,
 787                                         FeatureMOVBE,
 788                                         FeatureLZCNT,
 789                                         FeatureBMI,
 790                                         FeatureBMI2,
 791                                         FeatureFMA,
 792                                         FeaturePRFCHW,
 793                                         FeatureSlowTwoMemOps,
 794                                         FeatureFastPartialYMMorZMMWrite,
 795                                         FeatureHasFastGather,
 796                                         FeatureSlowPMADDWD];
 797   // TODO Add AVX5124FMAPS/AVX5124VNNIW features
 798   list<SubtargetFeature> KNMFeatures =
 799     !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
 800
 801   // Barcelona
 802   list<SubtargetFeature> BarcelonaInheritableFeatures = [FeatureX87,
 803                                                          FeatureCMPXCHG8B,
 804                                                          FeatureSSE4A,
 805                                                          Feature3DNowA,
 806                                                          FeatureFXSR,
 807                                                          FeatureNOPL,
 808                                                          FeatureCMPXCHG16B,
 809                                                          FeatureLZCNT,
 810                                                          FeaturePOPCNT,
 811                                                          FeatureSlowSHLD,
 812                                                          FeatureLAHFSAHF,
 813                                                          FeatureCMOV,
 814                                                          Feature64Bit,
 815                                                          FeatureFastScalarShiftMasks];
 816   list<SubtargetFeature> BarcelonaFeatures = BarcelonaInheritableFeatures;
 817
 818   // Bobcat
 819   list<SubtargetFeature> BtVer1InheritableFeatures = [FeatureX87,
 820                                                       FeatureCMPXCHG8B,
 821                                                       FeatureCMOV,
 822                                                       FeatureMMX,
 823                                                       FeatureSSSE3,
 824                                                       FeatureSSE4A,
 825                                                       FeatureFXSR,
 826                                                       FeatureNOPL,
 827                                                       Feature64Bit,
 828                                                       FeatureCMPXCHG16B,
 829                                                       FeaturePRFCHW,
 830                                                       FeatureLZCNT,
 831                                                       FeaturePOPCNT,
 832                                                       FeatureSlowSHLD,
 833                                                       FeatureLAHFSAHF,
 834                                                       FeatureFast15ByteNOP,
 835                                                       FeatureFastScalarShiftMasks,
 836                                                       FeatureFastVectorShiftMasks];
 837   list<SubtargetFeature> BtVer1Features = BtVer1InheritableFeatures;
 838
 839   // Jaguar
 840   list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
 841                                                      FeatureAES,
 842                                                      FeaturePCLMUL,
 843                                                      FeatureBMI,
 844                                                      FeatureF16C,
 845                                                      FeatureMOVBE,
 846                                                      FeatureXSAVE,
 847                                                      FeatureXSAVEOPT];
 848   list<SubtargetFeature> BtVer2SpecificFeatures = [FeatureFastLZCNT,
 849                                                    FeatureFastBEXTR,
 850                                                    FeatureFastPartialYMMorZMMWrite,
 851                                                    FeatureFastHorizontalOps];
 852   list<SubtargetFeature> BtVer2InheritableFeatures =
 853     !listconcat(BtVer1InheritableFeatures, BtVer2AdditionalFeatures);
 854   list<SubtargetFeature> BtVer2Features =
 855     !listconcat(BtVer2InheritableFeatures, BtVer2SpecificFeatures);
 856
 857   // Bulldozer
 858   list<SubtargetFeature> BdVer1InheritableFeatures = [FeatureX87,
 859                                                       FeatureCMPXCHG8B,
 860                                                       FeatureCMOV,
 861                                                       FeatureXOP,
 862                                                       Feature64Bit,
 863                                                       FeatureCMPXCHG16B,
 864                                                       FeatureAES,
 865                                                       FeaturePRFCHW,
 866                                                       FeaturePCLMUL,
 867                                                       FeatureMMX,
 868                                                       FeatureFXSR,
 869                                                       FeatureNOPL,
 870                                                       FeatureLZCNT,
 871                                                       FeaturePOPCNT,
 872                                                       FeatureXSAVE,
 873                                                       FeatureLWP,
 874                                                       FeatureSlowSHLD,
 875                                                       FeatureLAHFSAHF,
 876                                                       FeatureFast11ByteNOP,
 877                                                       FeatureFastScalarShiftMasks,
 878                                                       FeatureBranchFusion];
 879   list<SubtargetFeature> BdVer1Features = BdVer1InheritableFeatures;
 880
 881   // PileDriver
 882   list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
 883                                                      FeatureBMI,
 884                                                      FeatureTBM,
 885                                                      FeatureFMA,
 886                                                      FeatureFastBEXTR];
 887   list<SubtargetFeature> BdVer2InheritableFeatures =
 888     !listconcat(BdVer1InheritableFeatures, BdVer2AdditionalFeatures);
 889   list<SubtargetFeature> BdVer2Features = BdVer2InheritableFeatures;
 890
 891   // Steamroller
 892   list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT,
 893                                                      FeatureFSGSBase];
 894   list<SubtargetFeature> BdVer3InheritableFeatures =
 895     !listconcat(BdVer2InheritableFeatures, BdVer3AdditionalFeatures);
 896   list<SubtargetFeature> BdVer3Features = BdVer3InheritableFeatures;
 897
 898   // Excavator
 899   list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2,
 900                                                      FeatureBMI2,
 901                                                      FeatureMWAITX];
 902   list<SubtargetFeature> BdVer4InheritableFeatures =
 903     !listconcat(BdVer3InheritableFeatures, BdVer4AdditionalFeatures);
 904   list<SubtargetFeature> BdVer4Features = BdVer4InheritableFeatures;
 905
 906
 907   // AMD Zen Processors common ISAs
 908   list<SubtargetFeature> ZNFeatures = [FeatureADX,
 909                                        FeatureAES,
 910                                        FeatureAVX2,
 911                                        FeatureBMI,
 912                                        FeatureBMI2,
 913                                        FeatureCLFLUSHOPT,
 914                                        FeatureCLZERO,
 915                                        FeatureCMOV,
 916                                        Feature64Bit,
 917                                        FeatureCMPXCHG16B,
 918                                        FeatureF16C,
 919                                        FeatureFMA,
 920                                        FeatureFSGSBase,
 921                                        FeatureFXSR,
 922                                        FeatureNOPL,
 923                                        FeatureFastLZCNT,
 924                                        FeatureLAHFSAHF,
 925                                        FeatureLZCNT,
 926                                        FeatureFastBEXTR,
 927                                        FeatureFast15ByteNOP,
 928                                        FeatureBranchFusion,
 929                                        FeatureFastScalarShiftMasks,
 930                                        FeatureMMX,
 931                                        FeatureMOVBE,
 932                                        FeatureMWAITX,
 933                                        FeaturePCLMUL,
 934                                        FeaturePOPCNT,
 935                                        FeaturePRFCHW,
 936                                        FeatureRDRAND,
 937                                        FeatureRDSEED,
 938                                        FeatureSHA,
 939                                        FeatureSSE4A,
 940                                        FeatureSlowSHLD,
 941                                        FeatureX87,
 942                                        FeatureXSAVE,
 943                                        FeatureXSAVEC,
 944                                        FeatureXSAVEOPT,
 945                                        FeatureXSAVES];
 946   list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
 947                                                   FeatureRDPID,
 948                                                   FeatureWBNOINVD];
 949   list<SubtargetFeature> ZN2Features =
 950     !listconcat(ZNFeatures, ZN2AdditionalFeatures);
 951 }
 952
 953 //===----------------------------------------------------------------------===//
 954 // X86 processors supported.
 955 //===----------------------------------------------------------------------===//
 956
 957 class Proc<string Name, list<SubtargetFeature> Features>
 958  : ProcessorModel<Name, GenericModel, Features>;
 959
 960 // NOTE: CMPXCHG8B is here for legacy compatbility so that it is only disabled
 961 // if i386/i486 is specifically requested.
 962 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16,
 963                                FeatureCMPXCHG8B]>;
 964 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 965 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 966 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16,
 967                                FeatureCMPXCHG8B]>;
 968 def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16,
 969                                FeatureCMPXCHG8B]>;
 970 def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16,
 971                                FeatureCMPXCHG8B, FeatureMMX]>;
 972
 973 def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
 974                     FeatureCMOV]>;
 975 def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
 976                           FeatureCMOV, FeatureNOPL]>;
 977
 978 def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
 979                                FeatureMMX, FeatureCMOV, FeatureFXSR,
 980                                FeatureNOPL]>;
 981
 982 foreach P = ["pentium3", "pentium3m"] in {
 983   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,FeatureMMX,
 984                  FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
 985 }
 986
 987 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
 988 // The intent is to enable it for pentium4 which is the current default
 989 // processor in a vanilla 32-bit clang compilation when no specific
 990 // architecture is specified.  This generally gives a nice performance
 991 // increase on silvermont, with largely neutral behavior on other
 992 // contemporary large core processors.
 993 // pentium-m, pentium4m, prescott and nocona are included as a preventative
 994 // measure to avoid performance surprises, in case clang's default cpu
 995 // changes slightly.
 996
 997 def : ProcessorModel<"pentium-m", GenericPostRAModel,
 998                      [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
 999                       FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
1000                       FeatureCMOV]>;
1001
1002 foreach P = ["pentium4", "pentium4m"] in {
1003   def : ProcessorModel<P, GenericPostRAModel,
1004                        [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1005                         FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
1006                         FeatureCMOV]>;
1007 }
1008
1009 // Intel Quark.
1010 def : Proc<"lakemont",        []>;
1011
1012 // Intel Core Duo.
1013 def : ProcessorModel<"yonah", SandyBridgeModel,
1014                      [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1015                       FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL,
1016                       FeatureCMOV]>;
1017
1018 // NetBurst.
1019 def : ProcessorModel<"prescott", GenericPostRAModel,
1020                      [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1021                       FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL,
1022                       FeatureCMOV]>;
1023 def : ProcessorModel<"nocona", GenericPostRAModel, [
1024   FeatureX87,
1025   FeatureSlowUAMem16,
1026   FeatureCMPXCHG8B,
1027   FeatureCMOV,
1028   FeatureMMX,
1029   FeatureSSE3,
1030   FeatureFXSR,
1031   FeatureNOPL,
1032   Feature64Bit,
1033   FeatureCMPXCHG16B
1034 ]>;
1035
1036 // Intel Core 2 Solo/Duo.
1037 def : ProcessorModel<"core2", SandyBridgeModel, [
1038   FeatureX87,
1039   FeatureSlowUAMem16,
1040   FeatureCMPXCHG8B,
1041   FeatureCMOV,
1042   FeatureMMX,
1043   FeatureSSSE3,
1044   FeatureFXSR,
1045   FeatureNOPL,
1046   Feature64Bit,
1047   FeatureCMPXCHG16B,
1048   FeatureLAHFSAHF,
1049   FeatureMacroFusion
1050 ]>;
1051 def : ProcessorModel<"penryn", SandyBridgeModel, [
1052   FeatureX87,
1053   FeatureSlowUAMem16,
1054   FeatureCMPXCHG8B,
1055   FeatureCMOV,
1056   FeatureMMX,
1057   FeatureSSE41,
1058   FeatureFXSR,
1059   FeatureNOPL,
1060   Feature64Bit,
1061   FeatureCMPXCHG16B,
1062   FeatureLAHFSAHF,
1063   FeatureMacroFusion
1064 ]>;
1065
1066 // Atom CPUs.
1067 foreach P = ["bonnell", "atom"] in {
1068   def : ProcessorModel<P, AtomModel, ProcessorFeatures.AtomFeatures>;
1069 }
1070
1071 foreach P = ["silvermont", "slm"] in {
1072   def : ProcessorModel<P, SLMModel, ProcessorFeatures.SLMFeatures>;
1073 }
1074
1075 def : ProcessorModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures>;
1076 def : ProcessorModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures>;
1077 def : ProcessorModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures>;
1078
1079 // "Arrandale" along with corei3 and corei5
1080 foreach P = ["nehalem", "corei7"] in {
1081   def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures>;
1082 }
1083
1084 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
1085 def : ProcessorModel<"westmere", SandyBridgeModel,
1086                      ProcessorFeatures.WSMFeatures>;
1087
1088 foreach P = ["sandybridge", "corei7-avx"] in {
1089   def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures>;
1090 }
1091
1092 foreach P = ["ivybridge", "core-avx-i"] in {
1093   def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures>;
1094 }
1095
1096 foreach P = ["haswell", "core-avx2"] in {
1097   def : ProcessorModel<P, HaswellModel, ProcessorFeatures.HSWFeatures>;
1098 }
1099
1100 def : ProcessorModel<"broadwell", BroadwellModel,
1101                      ProcessorFeatures.BDWFeatures>;
1102
1103 def : ProcessorModel<"skylake", SkylakeClientModel,
1104                      ProcessorFeatures.SKLFeatures>;
1105
1106 // FIXME: define KNL scheduler model
1107 def : ProcessorModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures>;
1108 def : ProcessorModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures>;
1109
1110 foreach P = ["skylake-avx512", "skx"] in {
1111   def : ProcessorModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures>;
1112 }
1113
1114 def : ProcessorModel<"cascadelake", SkylakeServerModel,
1115                      ProcessorFeatures.CLXFeatures>;
1116 def : ProcessorModel<"cooperlake", SkylakeServerModel,
1117                      ProcessorFeatures.CPXFeatures>;
1118 def : ProcessorModel<"cannonlake", SkylakeServerModel,
1119                      ProcessorFeatures.CNLFeatures>;
1120 def : ProcessorModel<"icelake-client", SkylakeServerModel,
1121                      ProcessorFeatures.ICLFeatures>;
1122 def : ProcessorModel<"icelake-server", SkylakeServerModel,
1123                      ProcessorFeatures.ICXFeatures>;
1124 def : ProcessorModel<"tigerlake", SkylakeServerModel,
1125                      ProcessorFeatures.TGLFeatures>;
1126
1127 // AMD CPUs.
1128
1129 def : Proc<"k6",   [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1130                     FeatureMMX]>;
1131 def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1132                     Feature3DNow]>;
1133 def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1134                                Feature3DNow]>;
1135
1136 foreach P = ["athlon", "athlon-tbird"] in {
1137   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV,
1138                  Feature3DNowA, FeatureNOPL, FeatureSlowSHLD]>;
1139 }
1140
1141 foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
1142   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV,
1143                  FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL,
1144                  FeatureSlowSHLD]>;
1145 }
1146
1147 foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
1148   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1149                  FeatureSSE2, Feature3DNowA, FeatureFXSR, FeatureNOPL,
1150                  Feature64Bit, FeatureSlowSHLD, FeatureCMOV,
1151                  FeatureFastScalarShiftMasks]>;
1152 }
1153
1154 foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
1155   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureSSE3,
1156                  Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B,
1157                  FeatureSlowSHLD, FeatureCMOV, Feature64Bit,
1158                  FeatureFastScalarShiftMasks]>;
1159 }
1160
1161 foreach P = ["amdfam10", "barcelona"] in {
1162   def : Proc<P, ProcessorFeatures.BarcelonaFeatures>;
1163 }
1164
1165 // Bobcat
1166 def : Proc<"btver1", ProcessorFeatures.BtVer1Features>;
1167 // Jaguar
1168 def : ProcessorModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features>;
1169
1170 // Bulldozer
1171 def : ProcessorModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features>;
1172 // Piledriver
1173 def : ProcessorModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features>;
1174 // Steamroller
1175 def : Proc<"bdver3", ProcessorFeatures.BdVer3Features>;
1176 // Excavator
1177 def : Proc<"bdver4", ProcessorFeatures.BdVer4Features>;
1178
1179 def : ProcessorModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures>;
1180 def : ProcessorModel<"znver2", Znver1Model, ProcessorFeatures.ZN2Features>;
1181
1182 def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1183                                Feature3DNowA]>;
1184
1185 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
1186 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
1187 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
1188 def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1189                                FeatureMMX, FeatureSSE1, FeatureFXSR,
1190                                FeatureCMOV]>;
1191
1192 // We also provide a generic 64-bit specific x86 processor model which tries to
1193 // be good for modern chips without enabling instruction set encodings past the
1194 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
1195 // modern 64-bit x86 chip, and enables features that are generally beneficial.
1196 //
1197 // We currently use the Sandy Bridge model as the default scheduling model as
1198 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
1199 // covers a huge swath of x86 processors. If there are specific scheduling
1200 // knobs which need to be tuned differently for AMD chips, we might consider
1201 // forming a common base for them.
1202 def : ProcessorModel<"x86-64", SandyBridgeModel, [
1203   FeatureX87,
1204   FeatureCMPXCHG8B,
1205   FeatureCMOV,
1206   FeatureMMX,
1207   FeatureSSE2,
1208   FeatureFXSR,
1209   FeatureNOPL,
1210   Feature64Bit,
1211   FeatureSlow3OpsLEA,
1212   FeatureSlowIncDec,
1213   FeatureMacroFusion
1214 ]>;
1215
1216 //===----------------------------------------------------------------------===//
1217 // Calling Conventions
1218 //===----------------------------------------------------------------------===//
1219
1220 include "X86CallingConv.td"
1221
1222
1223 //===----------------------------------------------------------------------===//
1224 // Assembly Parser
1225 //===----------------------------------------------------------------------===//
1226
1227 def ATTAsmParserVariant : AsmParserVariant {
1228   int Variant = 0;
1229
1230   // Variant name.
1231   string Name = "att";
1232
1233   // Discard comments in assembly strings.
1234   string CommentDelimiter = "#";
1235
1236   // Recognize hard coded registers.
1237   string RegisterPrefix = "%";
1238 }
1239
1240 def IntelAsmParserVariant : AsmParserVariant {
1241   int Variant = 1;
1242
1243   // Variant name.
1244   string Name = "intel";
1245
1246   // Discard comments in assembly strings.
1247   string CommentDelimiter = ";";
1248
1249   // Recognize hard coded registers.
1250   string RegisterPrefix = "";
1251 }
1252
1253 //===----------------------------------------------------------------------===//
1254 // Assembly Printers
1255 //===----------------------------------------------------------------------===//
1256
1257 // The X86 target supports two different syntaxes for emitting machine code.
1258 // This is controlled by the -x86-asm-syntax={att|intel}
1259 def ATTAsmWriter : AsmWriter {
1260   string AsmWriterClassName  = "ATTInstPrinter";
1261   int Variant = 0;
1262 }
1263 def IntelAsmWriter : AsmWriter {
1264   string AsmWriterClassName  = "IntelInstPrinter";
1265   int Variant = 1;
1266 }
1267
1268 def X86 : Target {
1269   // Information about the instructions...
1270   let InstructionSet = X86InstrInfo;
1271   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
1272   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
1273   let AllowRegisterRenaming = 1;
1274 }
1275
1276 //===----------------------------------------------------------------------===//
1277 // Pfm Counters
1278 //===----------------------------------------------------------------------===//
1279
1280 include "X86PfmCounters.td"