lib/Target/X86/X86SchedBroadwell.td

   1 //=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Broadwell to support instruction
  10 // scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def BroadwellModel : SchedMachineModel {
  15   // All x86 instructions are modeled as a single micro-op, and BW can decode 4
  16   // instructions per cycle.
  17   let IssueWidth = 4;
  18   let MicroOpBufferSize = 192; // Based on the reorder buffer.
  19   let LoadLatency = 5;
  20   let MispredictPenalty = 16;
  21
  22   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  23   let LoopMicroOpBufferSize = 50;
  24
  25   // This flag is set to allow the scheduler to assign a default model to
  26   // unrecognized opcodes.
  27   let CompleteModel = 0;
  28 }
  29
  30 let SchedModel = BroadwellModel in {
  31
  32 // Broadwell can issue micro-ops to 8 different ports in one cycle.
  33
  34 // Ports 0, 1, 5, and 6 handle all computation.
  35 // Port 4 gets the data half of stores. Store data can be available later than
  36 // the store address, but since we don't model the latency of stores, we can
  37 // ignore that.
  38 // Ports 2 and 3 are identical. They handle loads and the address half of
  39 // stores. Port 7 can handle address calculations.
  40 def BWPort0 : ProcResource<1>;
  41 def BWPort1 : ProcResource<1>;
  42 def BWPort2 : ProcResource<1>;
  43 def BWPort3 : ProcResource<1>;
  44 def BWPort4 : ProcResource<1>;
  45 def BWPort5 : ProcResource<1>;
  46 def BWPort6 : ProcResource<1>;
  47 def BWPort7 : ProcResource<1>;
  48
  49 // Many micro-ops are capable of issuing on multiple ports.
  50 def BWPort01  : ProcResGroup<[BWPort0, BWPort1]>;
  51 def BWPort23  : ProcResGroup<[BWPort2, BWPort3]>;
  52 def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
  53 def BWPort04  : ProcResGroup<[BWPort0, BWPort4]>;
  54 def BWPort05  : ProcResGroup<[BWPort0, BWPort5]>;
  55 def BWPort06  : ProcResGroup<[BWPort0, BWPort6]>;
  56 def BWPort15  : ProcResGroup<[BWPort1, BWPort5]>;
  57 def BWPort16  : ProcResGroup<[BWPort1, BWPort6]>;
  58 def BWPort56  : ProcResGroup<[BWPort5, BWPort6]>;
  59 def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
  60 def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
  61 def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
  62
  63 // 60 Entry Unified Scheduler
  64 def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
  65                               BWPort5, BWPort6, BWPort7]> {
  66   let BufferSize=60;
  67 }
  68
  69 // Integer division issued on port 0.
  70 def BWDivider : ProcResource<1>;
  71 // FP division and sqrt on port 0.
  72 def BWFPDivider : ProcResource<1>;
  73
  74 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  75 // cycles after the memory operand.
  76 def : ReadAdvance<ReadAfterLd, 5>;
  77
  78 // Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available
  79 // until 5/5/6 cycles after the memory operand.
  80 def : ReadAdvance<ReadAfterVecLd, 5>;
  81 def : ReadAdvance<ReadAfterVecXLd, 5>;
  82 def : ReadAdvance<ReadAfterVecYLd, 6>;
  83
  84 def : ReadAdvance<ReadInt2Fpu, 0>;
  85
  86 // Many SchedWrites are defined in pairs with and without a folded load.
  87 // Instructions with folded loads are usually micro-fused, so they only appear
  88 // as two micro-ops when queued in the reservation station.
  89 // This multiclass defines the resource usage for variants with and without
  90 // folded loads.
  91 multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
  92                           list<ProcResourceKind> ExePorts,
  93                           int Lat, list<int> Res = [1], int UOps = 1,
  94                           int LoadLat = 5> {
  95   // Register variant is using a single cycle on ExePort.
  96   def : WriteRes<SchedRW, ExePorts> {
  97     let Latency = Lat;
  98     let ResourceCycles = Res;
  99     let NumMicroOps = UOps;
 100   }
 101
 102   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 103   // the latency (default = 5).
 104   def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
 105     let Latency = !add(Lat, LoadLat);
 106     let ResourceCycles = !listconcat([1], Res);
 107     let NumMicroOps = !add(UOps, 1);
 108   }
 109 }
 110
 111 // A folded store needs a cycle on port 4 for the store data, and an extra port
 112 // 2/3/7 cycle to recompute the address.
 113 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
 114
 115 // Arithmetic.
 116 defm : BWWriteResPair<WriteALU,    [BWPort0156], 1>; // Simple integer ALU op.
 117 defm : BWWriteResPair<WriteADC,    [BWPort06], 1>; // Integer ALU + flags op.
 118
 119 // Integer multiplication.
 120 defm : BWWriteResPair<WriteIMul8,     [BWPort1],   3>;
 121 defm : BWWriteResPair<WriteIMul16,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>;
 122 defm : X86WriteRes<WriteIMul16Imm,    [BWPort1,BWPort0156], 4, [1,1], 2>;
 123 defm : X86WriteRes<WriteIMul16ImmLd,  [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>;
 124 defm : BWWriteResPair<WriteIMul16Reg, [BWPort1],   3>;
 125 defm : BWWriteResPair<WriteIMul32,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>;
 126 defm : BWWriteResPair<WriteIMul32Imm, [BWPort1],   3>;
 127 defm : BWWriteResPair<WriteIMul32Reg, [BWPort1],   3>;
 128 defm : BWWriteResPair<WriteIMul64,    [BWPort1,BWPort5], 4, [1,1], 2>;
 129 defm : BWWriteResPair<WriteIMul64Imm, [BWPort1],   3>;
 130 defm : BWWriteResPair<WriteIMul64Reg, [BWPort1],   3>;
 131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 132
 133 // TODO: Why isn't the BWDivider used consistently?
 134 defm : X86WriteRes<WriteDiv8,      [BWPort0, BWDivider], 25, [1, 10], 1>;
 135 defm : X86WriteRes<WriteDiv16,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 136 defm : X86WriteRes<WriteDiv32,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 137 defm : X86WriteRes<WriteDiv64,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 138 defm : X86WriteRes<WriteDiv8Ld,    [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 139 defm : X86WriteRes<WriteDiv16Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 140 defm : X86WriteRes<WriteDiv32Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 141 defm : X86WriteRes<WriteDiv64Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 142
 143 defm : X86WriteRes<WriteIDiv8,     [BWPort0, BWDivider], 25, [1,10], 1>;
 144 defm : X86WriteRes<WriteIDiv16,    [BWPort0, BWDivider], 25, [1,10], 1>;
 145 defm : X86WriteRes<WriteIDiv32,    [BWPort0, BWDivider], 25, [1,10], 1>;
 146 defm : X86WriteRes<WriteIDiv64,    [BWPort0, BWDivider], 25, [1,10], 1>;
 147 defm : X86WriteRes<WriteIDiv8Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 148 defm : X86WriteRes<WriteIDiv16Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 149 defm : X86WriteRes<WriteIDiv32Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 150 defm : X86WriteRes<WriteIDiv64Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 151
 152 defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>;
 153 defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>;
 154 defm : X86WriteRes<WriteBSWAP32,   [BWPort15], 1, [1], 1>;
 155 defm : X86WriteRes<WriteBSWAP64,   [BWPort06, BWPort15], 2, [1, 1], 2>;
 156 defm : X86WriteRes<WriteXCHG,      [BWPort0156], 2, [3], 3>;
 157
 158 defm : BWWriteResPair<WriteCRC32, [BWPort1],   3>;
 159
 160 def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
 161
 162 defm : BWWriteResPair<WriteCMOV,  [BWPort06], 1>; // Conditional move.
 163 defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move.
 164
 165 def  : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
 166 def  : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
 167   let Latency = 2;
 168   let NumMicroOps = 3;
 169 }
 170
 171 defm : X86WriteRes<WriteLAHFSAHF,        [BWPort06], 1, [1], 1>;
 172 defm : X86WriteRes<WriteBitTest,         [BWPort06], 1, [1], 1>; // Bit Test instrs
 173 defm : X86WriteRes<WriteBitTestImmLd,    [BWPort06,BWPort23], 6, [1,1], 2>;
 174 defm : X86WriteRes<WriteBitTestRegLd,    [BWPort0156,BWPort23], 6, [1,1], 2>;
 175 defm : X86WriteRes<WriteBitTestSet,      [BWPort06], 1, [1], 1>; // Bit Test + Set instrs
 176 defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 5, [1,1], 3>;
 177 defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>;
 178
 179 // Bit counts.
 180 defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;
 181 defm : BWWriteResPair<WriteBSR, [BWPort1], 3>;
 182 defm : BWWriteResPair<WriteLZCNT,          [BWPort1], 3>;
 183 defm : BWWriteResPair<WriteTZCNT,          [BWPort1], 3>;
 184 defm : BWWriteResPair<WritePOPCNT,         [BWPort1], 3>;
 185
 186 // Integer shifts and rotates.
 187 defm : BWWriteResPair<WriteShift,    [BWPort06],  1>;
 188 defm : BWWriteResPair<WriteShiftCL,  [BWPort06,BWPort0156],  3, [2,1], 3>;
 189 defm : BWWriteResPair<WriteRotate,   [BWPort06],  1, [1], 1>;
 190 defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156],  3, [2,1], 3>;
 191
 192 // SHLD/SHRD.
 193 defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>;
 194 defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>;
 195 defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>;
 196 defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>;
 197
 198 // BMI1 BEXTR/BLS, BMI2 BZHI
 199 defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
 200 defm : BWWriteResPair<WriteBLS,   [BWPort15], 1>;
 201 defm : BWWriteResPair<WriteBZHI,  [BWPort15], 1>;
 202
 203 // Loads, stores, and moves, not folded with other operations.
 204 defm : X86WriteRes<WriteLoad,    [BWPort23], 5, [1], 1>;
 205 defm : X86WriteRes<WriteStore,   [BWPort237, BWPort4], 1, [1,1], 1>;
 206 defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>;
 207 defm : X86WriteRes<WriteMove,    [BWPort0156], 1, [1], 1>;
 208
 209 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 210 // These can often bypass execution ports completely.
 211 def : WriteRes<WriteZero,  []>;
 212
 213 // Treat misc copies as a move.
 214 def : InstRW<[WriteMove], (instrs COPY)>;
 215
 216 // Branches don't produce values, so they have no latency, but they still
 217 // consume resources. Indirect branches can fold loads.
 218 defm : BWWriteResPair<WriteJump,  [BWPort06],   1>;
 219
 220 // Floating point. This covers both scalar and vector operations.
 221 defm : X86WriteRes<WriteFLD0,          [BWPort01], 1, [1], 1>;
 222 defm : X86WriteRes<WriteFLD1,          [BWPort01], 1, [2], 2>;
 223 defm : X86WriteRes<WriteFLDC,          [BWPort01], 1, [2], 2>;
 224 defm : X86WriteRes<WriteFLoad,         [BWPort23], 5, [1], 1>;
 225 defm : X86WriteRes<WriteFLoadX,        [BWPort23], 5, [1], 1>;
 226 defm : X86WriteRes<WriteFLoadY,        [BWPort23], 6, [1], 1>;
 227 defm : X86WriteRes<WriteFMaskedLoad,   [BWPort23,BWPort5], 7, [1,2], 3>;
 228 defm : X86WriteRes<WriteFMaskedLoadY,  [BWPort23,BWPort5], 8, [1,2], 3>;
 229 defm : X86WriteRes<WriteFStore,        [BWPort237,BWPort4], 1, [1,1], 2>;
 230 defm : X86WriteRes<WriteFStoreX,       [BWPort237,BWPort4], 1, [1,1], 2>;
 231 defm : X86WriteRes<WriteFStoreY,       [BWPort237,BWPort4], 1, [1,1], 2>;
 232 defm : X86WriteRes<WriteFStoreNT,      [BWPort237,BWPort4], 1, [1,1], 2>;
 233 defm : X86WriteRes<WriteFStoreNTX,     [BWPort237,BWPort4], 1, [1,1], 2>;
 234 defm : X86WriteRes<WriteFStoreNTY,     [BWPort237,BWPort4], 1, [1,1], 2>;
 235 defm : X86WriteRes<WriteFMaskedStore,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 236 defm : X86WriteRes<WriteFMaskedStoreY, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 237 defm : X86WriteRes<WriteFMove,         [BWPort5], 1, [1], 1>;
 238 defm : X86WriteRes<WriteFMoveX,        [BWPort5], 1, [1], 1>;
 239 defm : X86WriteRes<WriteFMoveY,        [BWPort5], 1, [1], 1>;
 240
 241 defm : BWWriteResPair<WriteFAdd,    [BWPort1],  3, [1], 1, 5>; // Floating point add/sub.
 242 defm : BWWriteResPair<WriteFAddX,   [BWPort1],  3, [1], 1, 5>; // Floating point add/sub (XMM).
 243 defm : BWWriteResPair<WriteFAddY,   [BWPort1],  3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).
 244 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 245 defm : BWWriteResPair<WriteFAdd64,  [BWPort1],  3, [1], 1, 5>; // Floating point double add/sub.
 246 defm : BWWriteResPair<WriteFAdd64X, [BWPort1],  3, [1], 1, 5>; // Floating point double add/sub (XMM).
 247 defm : BWWriteResPair<WriteFAdd64Y, [BWPort1],  3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM).
 248 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 249
 250 defm : BWWriteResPair<WriteFCmp,    [BWPort1],  3, [1], 1, 5>; // Floating point compare.
 251 defm : BWWriteResPair<WriteFCmpX,   [BWPort1],  3, [1], 1, 5>; // Floating point compare (XMM).
 252 defm : BWWriteResPair<WriteFCmpY,   [BWPort1],  3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
 253 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 254 defm : BWWriteResPair<WriteFCmp64,  [BWPort1],  3, [1], 1, 5>; // Floating point double compare.
 255 defm : BWWriteResPair<WriteFCmp64X, [BWPort1],  3, [1], 1, 5>; // Floating point double compare (XMM).
 256 defm : BWWriteResPair<WriteFCmp64Y, [BWPort1],  3, [1], 1, 6>; // Floating point double compare (YMM/ZMM).
 257 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 258
 259 defm : BWWriteResPair<WriteFCom,    [BWPort1],  3>; // Floating point compare to flags.
 260
 261 defm : BWWriteResPair<WriteFMul,    [BWPort01], 3, [1], 1, 5>; // Floating point multiplication.
 262 defm : BWWriteResPair<WriteFMulX,   [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM).
 263 defm : BWWriteResPair<WriteFMulY,   [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
 264 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 265 defm : BWWriteResPair<WriteFMul64,  [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication.
 266 defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM).
 267 defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM).
 268 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 269
 270 //defm : BWWriteResPair<WriteFDiv,     [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 271 defm : BWWriteResPair<WriteFDivX,    [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM).
 272 defm : BWWriteResPair<WriteFDivY,    [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM).
 273 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 274 //defm : BWWriteResPair<WriteFDiv64,   [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division.
 275 defm : BWWriteResPair<WriteFDiv64X,  [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM).
 276 defm : BWWriteResPair<WriteFDiv64Y,  [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM).
 277 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 278
 279 defm : X86WriteRes<WriteFSqrt,       [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root.
 280 defm : X86WriteRes<WriteFSqrtLd,     [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>;
 281 defm : BWWriteResPair<WriteFSqrtX,   [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM).
 282 defm : BWWriteResPair<WriteFSqrtY,   [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM).
 283 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 284 defm : X86WriteRes<WriteFSqrt64,     [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root.
 285 defm : X86WriteRes<WriteFSqrt64Ld,   [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>;
 286 defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM).
 287 defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM).
 288 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 289 defm : BWWriteResPair<WriteFSqrt80,  [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root.
 290
 291 defm : BWWriteResPair<WriteFRcp,   [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal estimate.
 292 defm : BWWriteResPair<WriteFRcpX,  [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal estimate (XMM).
 293 defm : BWWriteResPair<WriteFRcpY,  [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM).
 294 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 295
 296 defm : BWWriteResPair<WriteFRsqrt, [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal square root estimate.
 297 defm : BWWriteResPair<WriteFRsqrtX,[BWPort0],  5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM).
 298 defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM).
 299 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 300
 301 defm : BWWriteResPair<WriteFMA,    [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add.
 302 defm : BWWriteResPair<WriteFMAX,   [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM).
 303 defm : BWWriteResPair<WriteFMAY,   [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM).
 304 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 305 defm : BWWriteResPair<WriteDPPD,   [BWPort0,BWPort1,BWPort5],  9, [1,1,1], 3, 5>; // Floating point double dot product.
 306 defm : BWWriteResPair<WriteDPPS,   [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 5>; // Floating point single dot product.
 307 defm : BWWriteResPair<WriteDPPSY,  [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 6>; // Floating point single dot product (YMM).
 308 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
 309 defm : BWWriteResPair<WriteFSign,     [BWPort5], 1>; // Floating point fabs/fchs.
 310 defm : X86WriteRes<WriteFRnd,            [BWPort23],  6, [1],   1>; // Floating point rounding.
 311 defm : X86WriteRes<WriteFRndY,           [BWPort23],  6, [1],   1>; // Floating point rounding (YMM/ZMM).
 312 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 313 defm : X86WriteRes<WriteFRndLd,  [BWPort1,BWPort23], 11, [2,1], 3>;
 314 defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>;
 315 defm : BWWriteResPair<WriteFLogic,    [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals.
 316 defm : BWWriteResPair<WriteFLogicY,   [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM).
 317 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 318 defm : BWWriteResPair<WriteFTest,     [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions.
 319 defm : BWWriteResPair<WriteFTestY,    [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM).
 320 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 321 defm : BWWriteResPair<WriteFShuffle,  [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles.
 322 defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM).
 323 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 324 defm : BWWriteResPair<WriteFVarShuffle,  [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles.
 325 defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
 326 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 327 defm : BWWriteResPair<WriteFBlend,  [BWPort015], 1, [1], 1, 5>; // Floating point vector blends.
 328 defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends.
 329 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 330 defm : BWWriteResPair<WriteFVarBlend,  [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends.
 331 defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends.
 332 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 333
 334 // FMA Scheduling helper class.
 335 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 336
 337 // Vector integer operations.
 338 defm : X86WriteRes<WriteVecLoad,         [BWPort23], 5, [1], 1>;
 339 defm : X86WriteRes<WriteVecLoadX,        [BWPort23], 5, [1], 1>;
 340 defm : X86WriteRes<WriteVecLoadY,        [BWPort23], 6, [1], 1>;
 341 defm : X86WriteRes<WriteVecLoadNT,       [BWPort23], 5, [1], 1>;
 342 defm : X86WriteRes<WriteVecLoadNTY,      [BWPort23], 6, [1], 1>;
 343 defm : X86WriteRes<WriteVecMaskedLoad,   [BWPort23,BWPort5], 7, [1,2], 3>;
 344 defm : X86WriteRes<WriteVecMaskedLoadY,  [BWPort23,BWPort5], 8, [1,2], 3>;
 345 defm : X86WriteRes<WriteVecStore,        [BWPort237,BWPort4], 1, [1,1], 2>;
 346 defm : X86WriteRes<WriteVecStoreX,       [BWPort237,BWPort4], 1, [1,1], 2>;
 347 defm : X86WriteRes<WriteVecStoreY,       [BWPort237,BWPort4], 1, [1,1], 2>;
 348 defm : X86WriteRes<WriteVecStoreNT,      [BWPort237,BWPort4], 1, [1,1], 2>;
 349 defm : X86WriteRes<WriteVecStoreNTY,     [BWPort237,BWPort4], 1, [1,1], 2>;
 350 defm : X86WriteRes<WriteVecMaskedStore,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 351 defm : X86WriteRes<WriteVecMaskedStoreY, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 352 defm : X86WriteRes<WriteVecMove,         [BWPort015], 1, [1], 1>;
 353 defm : X86WriteRes<WriteVecMoveX,        [BWPort015], 1, [1], 1>;
 354 defm : X86WriteRes<WriteVecMoveY,        [BWPort015], 1, [1], 1>;
 355 defm : X86WriteRes<WriteVecMoveToGpr,    [BWPort0], 1, [1], 1>;
 356 defm : X86WriteRes<WriteVecMoveFromGpr,  [BWPort5], 1, [1], 1>;
 357
 358 defm : X86WriteRes<WriteEMMS,            [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>;
 359
 360 defm : BWWriteResPair<WriteVecALU,   [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 361 defm : BWWriteResPair<WriteVecALUX,  [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 362 defm : BWWriteResPair<WriteVecALUY,  [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM).
 363 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 364 defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
 365 defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
 366 defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM).
 367 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 368 defm : BWWriteResPair<WriteVecTest,  [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions.
 369 defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM).
 370 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 371 defm : BWWriteResPair<WriteVecIMul,  [BWPort0],  5, [1], 1, 5>; // Vector integer multiply.
 372 defm : BWWriteResPair<WriteVecIMulX, [BWPort0],  5, [1], 1, 5>; // Vector integer multiply.
 373 defm : BWWriteResPair<WriteVecIMulY, [BWPort0],  5, [1], 1, 6>; // Vector integer multiply.
 374 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 375 defm : BWWriteResPair<WritePMULLD,   [BWPort0], 10, [2], 2, 5>; // Vector PMULLD.
 376 defm : BWWriteResPair<WritePMULLDY,  [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM).
 377 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 378 defm : BWWriteResPair<WriteShuffle,  [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
 379 defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
 380 defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM).
 381 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 382 defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 383 defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 384 defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM).
 385 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 386 defm : BWWriteResPair<WriteBlend,  [BWPort5], 1, [1], 1, 5>; // Vector blends.
 387 defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM).
 388 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 389 defm : BWWriteResPair<WriteVarBlend,  [BWPort5], 2, [2], 2, 5>; // Vector variable blends.
 390 defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM).
 391 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 392 defm : BWWriteResPair<WriteMPSAD,  [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD.
 393 defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD.
 394 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 395 defm : BWWriteResPair<WritePSADBW,   [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
 396 defm : BWWriteResPair<WritePSADBWX,  [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
 397 defm : BWWriteResPair<WritePSADBWY,  [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM).
 398 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 399 defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS.
 400
 401 // Vector integer shifts.
 402 defm : BWWriteResPair<WriteVecShift,     [BWPort0], 1, [1], 1, 5>;
 403 defm : BWWriteResPair<WriteVecShiftX,    [BWPort0,BWPort5],  2, [1,1], 2, 5>;
 404 defm : X86WriteRes<WriteVecShiftY,       [BWPort0,BWPort5],  4, [1,1], 2>;
 405 defm : X86WriteRes<WriteVecShiftYLd,     [BWPort0,BWPort23], 7, [1,1], 2>;
 406 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 407
 408 defm : BWWriteResPair<WriteVecShiftImm,  [BWPort0],  1, [1], 1, 5>;
 409 defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0],  1, [1], 1, 5>; // Vector integer immediate shifts (XMM).
 410 defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0],  1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM).
 411 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 412 defm : BWWriteResPair<WriteVarVecShift,  [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts.
 413 defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM).
 414 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 415
 416 // Vector insert/extract operations.
 417 def : WriteRes<WriteVecInsert, [BWPort5]> {
 418   let Latency = 2;
 419   let NumMicroOps = 2;
 420   let ResourceCycles = [2];
 421 }
 422 def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> {
 423   let Latency = 6;
 424   let NumMicroOps = 2;
 425 }
 426
 427 def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> {
 428   let Latency = 2;
 429   let NumMicroOps = 2;
 430 }
 431 def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> {
 432   let Latency = 2;
 433   let NumMicroOps = 3;
 434 }
 435
 436 // Conversion between integer and float.
 437 defm : BWWriteResPair<WriteCvtSS2I,   [BWPort1], 3>;
 438 defm : BWWriteResPair<WriteCvtPS2I,   [BWPort1], 3>;
 439 defm : BWWriteResPair<WriteCvtPS2IY,  [BWPort1], 3>;
 440 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 441 defm : BWWriteResPair<WriteCvtSD2I,   [BWPort1], 3>;
 442 defm : BWWriteResPair<WriteCvtPD2I,   [BWPort1], 3>;
 443 defm : BWWriteResPair<WriteCvtPD2IY,  [BWPort1], 3>;
 444 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 445
 446 defm : BWWriteResPair<WriteCvtI2SS,   [BWPort1], 4>;
 447 defm : BWWriteResPair<WriteCvtI2PS,   [BWPort1], 4>;
 448 defm : BWWriteResPair<WriteCvtI2PSY,  [BWPort1], 4>;
 449 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 450 defm : BWWriteResPair<WriteCvtI2SD,   [BWPort1], 4>;
 451 defm : BWWriteResPair<WriteCvtI2PD,   [BWPort1], 4>;
 452 defm : BWWriteResPair<WriteCvtI2PDY,  [BWPort1], 4>;
 453 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 454
 455 defm : BWWriteResPair<WriteCvtSS2SD,  [BWPort1], 3>;
 456 defm : BWWriteResPair<WriteCvtPS2PD,  [BWPort1], 3>;
 457 defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort1], 3>;
 458 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 459 defm : BWWriteResPair<WriteCvtSD2SS,  [BWPort1], 3>;
 460 defm : BWWriteResPair<WriteCvtPD2PS,  [BWPort1], 3>;
 461 defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1], 3>;
 462 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 463
 464 defm : X86WriteRes<WriteCvtPH2PS,     [BWPort0,BWPort5], 2, [1,1], 2>;
 465 defm : X86WriteRes<WriteCvtPH2PSY,    [BWPort0,BWPort5], 2, [1,1], 2>;
 466 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 467 defm : X86WriteRes<WriteCvtPH2PSLd,  [BWPort0,BWPort23], 6, [1,1], 2>;
 468 defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>;
 469 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 470
 471 defm : X86WriteRes<WriteCvtPS2PH,    [BWPort1,BWPort5], 4, [1,1], 2>;
 472 defm : X86WriteRes<WriteCvtPS2PHY,   [BWPort1,BWPort5], 6, [1,1], 2>;
 473 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 474 defm : X86WriteRes<WriteCvtPS2PHSt,  [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>;
 475 defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>;
 476 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 477
 478 // Strings instructions.
 479
 480 // Packed Compare Implicit Length Strings, Return Mask
 481 def : WriteRes<WritePCmpIStrM, [BWPort0]> {
 482   let Latency = 11;
 483   let NumMicroOps = 3;
 484   let ResourceCycles = [3];
 485 }
 486 def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
 487   let Latency = 16;
 488   let NumMicroOps = 4;
 489   let ResourceCycles = [3,1];
 490 }
 491
 492 // Packed Compare Explicit Length Strings, Return Mask
 493 def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
 494   let Latency = 19;
 495   let NumMicroOps = 9;
 496   let ResourceCycles = [4,3,1,1];
 497 }
 498 def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
 499   let Latency = 24;
 500   let NumMicroOps = 10;
 501   let ResourceCycles = [4,3,1,1,1];
 502 }
 503
 504 // Packed Compare Implicit Length Strings, Return Index
 505 def : WriteRes<WritePCmpIStrI, [BWPort0]> {
 506   let Latency = 11;
 507   let NumMicroOps = 3;
 508   let ResourceCycles = [3];
 509 }
 510 def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
 511   let Latency = 16;
 512   let NumMicroOps = 4;
 513   let ResourceCycles = [3,1];
 514 }
 515
 516 // Packed Compare Explicit Length Strings, Return Index
 517 def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
 518   let Latency = 18;
 519   let NumMicroOps = 8;
 520   let ResourceCycles = [4,3,1];
 521 }
 522 def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
 523   let Latency = 23;
 524   let NumMicroOps = 9;
 525   let ResourceCycles = [4,3,1,1];
 526 }
 527
 528 // MOVMSK Instructions.
 529 def : WriteRes<WriteFMOVMSK,    [BWPort0]> { let Latency = 3; }
 530 def : WriteRes<WriteVecMOVMSK,  [BWPort0]> { let Latency = 3; }
 531 def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; }
 532 def : WriteRes<WriteMMXMOVMSK,  [BWPort0]> { let Latency = 1; }
 533
 534 // AES instructions.
 535 def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
 536   let Latency = 7;
 537   let NumMicroOps = 1;
 538   let ResourceCycles = [1];
 539 }
 540 def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
 541   let Latency = 12;
 542   let NumMicroOps = 2;
 543   let ResourceCycles = [1,1];
 544 }
 545
 546 def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
 547   let Latency = 14;
 548   let NumMicroOps = 2;
 549   let ResourceCycles = [2];
 550 }
 551 def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
 552   let Latency = 19;
 553   let NumMicroOps = 3;
 554   let ResourceCycles = [2,1];
 555 }
 556
 557 def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
 558   let Latency = 29;
 559   let NumMicroOps = 11;
 560   let ResourceCycles = [2,7,2];
 561 }
 562 def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
 563   let Latency = 33;
 564   let NumMicroOps = 11;
 565   let ResourceCycles = [2,7,1,1];
 566 }
 567
 568 // Carry-less multiplication instructions.
 569 defm : BWWriteResPair<WriteCLMul,  [BWPort0], 5>;
 570
 571 // Catch-all for expensive system instructions.
 572 def : WriteRes<WriteSystem,     [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 573
 574 // AVX2.
 575 defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles.
 576 defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles.
 577 defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width vector shuffles.
 578 defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width vector variable shuffles.
 579
 580 // Old microcoded instructions that nobody use.
 581 def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 582
 583 // Fence instructions.
 584 def : WriteRes<WriteFence,  [BWPort23, BWPort4]>;
 585
 586 // Load/store MXCSR.
 587 def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 588 def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 589
 590 // Nop, not very useful expect it provides a model for nops!
 591 def : WriteRes<WriteNop, []>;
 592
 593 ////////////////////////////////////////////////////////////////////////////////
 594 // Horizontal add/sub  instructions.
 595 ////////////////////////////////////////////////////////////////////////////////
 596
 597 defm : BWWriteResPair<WriteFHAdd,   [BWPort1,BWPort5], 5, [1,2], 3, 5>;
 598 defm : BWWriteResPair<WriteFHAddY,  [BWPort1,BWPort5], 5, [1,2], 3, 6>;
 599 defm : BWWriteResPair<WritePHAdd,  [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 600 defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 601 defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>;
 602
 603 // Remaining instrs.
 604
 605 def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
 606   let Latency = 1;
 607   let NumMicroOps = 1;
 608   let ResourceCycles = [1];
 609 }
 610 def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr",
 611                                            "VPSRLVQ(Y?)rr")>;
 612
 613 def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
 614   let Latency = 1;
 615   let NumMicroOps = 1;
 616   let ResourceCycles = [1];
 617 }
 618 def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r",
 619                                            "UCOM_F(P?)r")>;
 620
 621 def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
 622   let Latency = 1;
 623   let NumMicroOps = 1;
 624   let ResourceCycles = [1];
 625 }
 626 def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>;
 627
 628 def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
 629   let Latency = 1;
 630   let NumMicroOps = 1;
 631   let ResourceCycles = [1];
 632 }
 633 def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 634
 635 def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
 636   let Latency = 1;
 637   let NumMicroOps = 1;
 638   let ResourceCycles = [1];
 639 }
 640 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
 641
 642 def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
 643   let Latency = 1;
 644   let NumMicroOps = 1;
 645   let ResourceCycles = [1];
 646 }
 647 def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
 648
 649 def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
 650   let Latency = 1;
 651   let NumMicroOps = 1;
 652   let ResourceCycles = [1];
 653 }
 654 def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>;
 655
 656 def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
 657   let Latency = 1;
 658   let NumMicroOps = 1;
 659   let ResourceCycles = [1];
 660 }
 661 def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>;
 662
 663 def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
 664   let Latency = 1;
 665   let NumMicroOps = 1;
 666   let ResourceCycles = [1];
 667 }
 668 def: InstRW<[BWWriteResGroup9], (instrs SGDT64m,
 669                                         SIDT64m,
 670                                         SMSW16m,
 671                                         STRm,
 672                                         SYSCALL)>;
 673
 674 def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
 675   let Latency = 1;
 676   let NumMicroOps = 2;
 677   let ResourceCycles = [1,1];
 678 }
 679 def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>;
 680 def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>;
 681
 682 def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
 683   let Latency = 2;
 684   let NumMicroOps = 2;
 685   let ResourceCycles = [2];
 686 }
 687 def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
 688
 689 def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
 690   let Latency = 2;
 691   let NumMicroOps = 2;
 692   let ResourceCycles = [2];
 693 }
 694 def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
 695                                          MFENCE,
 696                                          WAIT,
 697                                          XGETBV)>;
 698
 699 def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
 700   let Latency = 2;
 701   let NumMicroOps = 2;
 702   let ResourceCycles = [1,1];
 703 }
 704 def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr",
 705                                             "(V?)CVTSS2SDrr")>;
 706
 707 def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
 708   let Latency = 2;
 709   let NumMicroOps = 2;
 710   let ResourceCycles = [1,1];
 711 }
 712 def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
 713
 714 def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
 715   let Latency = 2;
 716   let NumMicroOps = 2;
 717   let ResourceCycles = [1,1];
 718 }
 719 def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>;
 720
 721 def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
 722   let Latency = 2;
 723   let NumMicroOps = 2;
 724   let ResourceCycles = [1,1];
 725 }
 726 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
 727
 728 def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
 729   let Latency = 2;
 730   let NumMicroOps = 2;
 731   let ResourceCycles = [1,1];
 732 }
 733 def: InstRW<[BWWriteResGroup20], (instrs CWD,
 734                                          JCXZ, JECXZ, JRCXZ,
 735                                          ADC8i8, SBB8i8,
 736                                          ADC16i16, SBB16i16,
 737                                          ADC32i32, SBB32i32,
 738                                          ADC64i32, SBB64i32)>;
 739
 740 def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
 741   let Latency = 2;
 742   let NumMicroOps = 3;
 743   let ResourceCycles = [1,1,1];
 744 }
 745 def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>;
 746
 747 def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
 748   let Latency = 2;
 749   let NumMicroOps = 3;
 750   let ResourceCycles = [1,1,1];
 751 }
 752 def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
 753
 754 def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
 755   let Latency = 2;
 756   let NumMicroOps = 3;
 757   let ResourceCycles = [1,1,1];
 758 }
 759 def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
 760                                          STOSB, STOSL, STOSQ, STOSW)>;
 761 def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>;
 762
 763 def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
 764   let Latency = 3;
 765   let NumMicroOps = 1;
 766   let ResourceCycles = [1];
 767 }
 768 def: InstRW<[BWWriteResGroup27], (instrs MMX_CVTPI2PSirr)>;
 769 def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr",
 770                                             "(V?)CVTDQ2PS(Y?)rr")>;
 771
 772 def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
 773   let Latency = 3;
 774   let NumMicroOps = 1;
 775   let ResourceCycles = [1];
 776 }
 777 def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr,
 778                                          VPBROADCASTWrr)>;
 779
 780 def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
 781   let Latency = 3;
 782   let NumMicroOps = 3;
 783   let ResourceCycles = [2,1];
 784 }
 785 def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWirr,
 786                                          MMX_PACKSSWBirr,
 787                                          MMX_PACKUSWBirr)>;
 788
 789 def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
 790   let Latency = 3;
 791   let NumMicroOps = 3;
 792   let ResourceCycles = [1,2];
 793 }
 794 def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
 795
 796 def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
 797   let Latency = 3;
 798   let NumMicroOps = 3;
 799   let ResourceCycles = [1,2];
 800 }
 801 def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r(1|i)",
 802                                             "RCR(8|16|32|64)r(1|i)")>;
 803
 804 def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
 805   let Latency = 3;
 806   let NumMicroOps = 4;
 807   let ResourceCycles = [1,1,1,1];
 808 }
 809 def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
 810
 811 def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
 812   let Latency = 3;
 813   let NumMicroOps = 4;
 814   let ResourceCycles = [1,1,1,1];
 815 }
 816 def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>;
 817
 818 def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
 819   let Latency = 4;
 820   let NumMicroOps = 2;
 821   let ResourceCycles = [1,1];
 822 }
 823 def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr",
 824                                             "(V?)CVT(T?)SD2SIrr",
 825                                             "(V?)CVT(T?)SS2SI64rr",
 826                                             "(V?)CVT(T?)SS2SIrr")>;
 827
 828 def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
 829   let Latency = 4;
 830   let NumMicroOps = 2;
 831   let ResourceCycles = [1,1];
 832 }
 833 def: InstRW<[BWWriteResGroup40], (instrs VCVTPS2PDYrr)>;
 834
 835 def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
 836   let Latency = 4;
 837   let NumMicroOps = 2;
 838   let ResourceCycles = [1,1];
 839 }
 840 def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>;
 841
 842 def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
 843   let Latency = 4;
 844   let NumMicroOps = 2;
 845   let ResourceCycles = [1,1];
 846 }
 847 def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDirr)>;
 848 def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIirr",
 849                                             "MMX_CVT(T?)PS2PIirr",
 850                                             "(V?)CVTDQ2PDrr",
 851                                             "(V?)CVTPD2PSrr",
 852                                             "(V?)CVTSD2SSrr",
 853                                             "(V?)CVTSI642SDrr",
 854                                             "(V?)CVTSI2SDrr",
 855                                             "(V?)CVTSI2SSrr",
 856                                             "(V?)CVT(T?)PD2DQrr")>;
 857
 858 def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
 859   let Latency = 4;
 860   let NumMicroOps = 3;
 861   let ResourceCycles = [1,1,1];
 862 }
 863 def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>;
 864
 865 def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
 866   let Latency = 4;
 867   let NumMicroOps = 3;
 868   let ResourceCycles = [1,1,1];
 869 }
 870 def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m",
 871                                             "IST_F(16|32)m")>;
 872
 873 def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
 874   let Latency = 4;
 875   let NumMicroOps = 4;
 876   let ResourceCycles = [4];
 877 }
 878 def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>;
 879
 880 def BWWriteResGroup46 : SchedWriteRes<[]> {
 881   let Latency = 0;
 882   let NumMicroOps = 4;
 883   let ResourceCycles = [];
 884 }
 885 def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>;
 886
 887 def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
 888   let Latency = 5;
 889   let NumMicroOps = 1;
 890   let ResourceCycles = [1];
 891 }
 892 def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 893
 894 def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
 895   let Latency = 5;
 896   let NumMicroOps = 1;
 897   let ResourceCycles = [1];
 898 }
 899 def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm(8|16|32)",
 900                                             "MOVZX(16|32|64)rm(8|16)")>;
 901 def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm,
 902                                          VMOVDDUPrm, MOVDDUPrm,
 903                                          VMOVSHDUPrm, MOVSHDUPrm,
 904                                          VMOVSLDUPrm, MOVSLDUPrm,
 905                                          VPBROADCASTDrm,
 906                                          VPBROADCASTQrm)>;
 907
 908 def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
 909   let Latency = 5;
 910   let NumMicroOps = 3;
 911   let ResourceCycles = [1,2];
 912 }
 913 def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>;
 914
 915 def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
 916   let Latency = 5;
 917   let NumMicroOps = 3;
 918   let ResourceCycles = [1,1,1];
 919 }
 920 def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
 921
 922 def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
 923   let Latency = 5;
 924   let NumMicroOps = 5;
 925   let ResourceCycles = [1,4];
 926 }
 927 def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>;
 928
 929 def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
 930   let Latency = 5;
 931   let NumMicroOps = 5;
 932   let ResourceCycles = [1,4];
 933 }
 934 def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>;
 935
 936 def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
 937   let Latency = 5;
 938   let NumMicroOps = 6;
 939   let ResourceCycles = [1,1,4];
 940 }
 941 def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>;
 942
 943 def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
 944   let Latency = 6;
 945   let NumMicroOps = 1;
 946   let ResourceCycles = [1];
 947 }
 948 def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
 949 def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
 950                                          VBROADCASTI128,
 951                                          VBROADCASTSDYrm,
 952                                          VBROADCASTSSYrm,
 953                                          VMOVDDUPYrm,
 954                                          VMOVSHDUPYrm,
 955                                          VMOVSLDUPYrm,
 956                                          VPBROADCASTDYrm,
 957                                          VPBROADCASTQYrm)>;
 958
 959 def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
 960   let Latency = 6;
 961   let NumMicroOps = 2;
 962   let ResourceCycles = [1,1];
 963 }
 964 def: InstRW<[BWWriteResGroup59], (instrs CVTPS2PDrm, VCVTPS2PDrm,
 965                                          CVTSS2SDrm, VCVTSS2SDrm,
 966                                          CVTSS2SDrm_Int, VCVTSS2SDrm_Int,
 967                                          VPSLLVQrm,
 968                                          VPSRLVQrm)>;
 969
 970 def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
 971   let Latency = 6;
 972   let NumMicroOps = 2;
 973   let ResourceCycles = [1,1];
 974 }
 975 def: InstRW<[BWWriteResGroup60], (instrs VCVTDQ2PDYrr,
 976                                          VCVTPD2PSYrr,
 977                                          VCVTPD2DQYrr,
 978                                          VCVTTPD2DQYrr)>;
 979
 980 def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
 981   let Latency = 6;
 982   let NumMicroOps = 2;
 983   let ResourceCycles = [1,1];
 984 }
 985 def: InstRW<[BWWriteResGroup62], (instrs FARJMP64)>;
 986 def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;
 987
 988 def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
 989   let Latency = 6;
 990   let NumMicroOps = 2;
 991   let ResourceCycles = [1,1];
 992 }
 993 def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
 994                                             "MOVBE(16|32|64)rm")>;
 995
 996 def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
 997   let Latency = 6;
 998   let NumMicroOps = 2;
 999   let ResourceCycles = [1,1];
1000 }
1001 def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm,
1002                                          VINSERTI128rm,
1003                                          VPBLENDDrmi)>;
1004
1005 def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1006   let Latency = 6;
1007   let NumMicroOps = 2;
1008   let ResourceCycles = [1,1];
1009 }
1010 def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
1011 def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
1012
1013 def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1014   let Latency = 6;
1015   let NumMicroOps = 4;
1016   let ResourceCycles = [1,1,1,1];
1017 }
1018 def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1019
1020 def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1021   let Latency = 6;
1022   let NumMicroOps = 4;
1023   let ResourceCycles = [1,1,1,1];
1024 }
1025 def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
1026                                             "SHL(8|16|32|64)m(1|i)",
1027                                             "SHR(8|16|32|64)m(1|i)")>;
1028
1029 def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1030   let Latency = 6;
1031   let NumMicroOps = 4;
1032   let ResourceCycles = [1,1,1,1];
1033 }
1034 def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
1035                                             "PUSH(16|32|64)rmm")>;
1036
1037 def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1038   let Latency = 6;
1039   let NumMicroOps = 6;
1040   let ResourceCycles = [1,5];
1041 }
1042 def: InstRW<[BWWriteResGroup71], (instrs STD)>;
1043
1044 def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1045   let Latency = 7;
1046   let NumMicroOps = 2;
1047   let ResourceCycles = [1,1];
1048 }
1049 def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm,
1050                                          VPSRLVQYrm)>;
1051
1052 def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1053   let Latency = 7;
1054   let NumMicroOps = 2;
1055   let ResourceCycles = [1,1];
1056 }
1057 def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>;
1058
1059 def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1060   let Latency = 7;
1061   let NumMicroOps = 2;
1062   let ResourceCycles = [1,1];
1063 }
1064 def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>;
1065
1066 def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1067   let Latency = 7;
1068   let NumMicroOps = 3;
1069   let ResourceCycles = [2,1];
1070 }
1071 def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWirm,
1072                                          MMX_PACKSSWBirm,
1073                                          MMX_PACKUSWBirm)>;
1074
1075 def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1076   let Latency = 7;
1077   let NumMicroOps = 3;
1078   let ResourceCycles = [1,2];
1079 }
1080 def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
1081                                          SCASB, SCASL, SCASQ, SCASW)>;
1082
1083 def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1084   let Latency = 7;
1085   let NumMicroOps = 3;
1086   let ResourceCycles = [1,1,1];
1087 }
1088 def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>;
1089
1090 def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1091   let Latency = 7;
1092   let NumMicroOps = 3;
1093   let ResourceCycles = [1,1,1];
1094 }
1095 def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>;
1096
1097 def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1098   let Latency = 7;
1099   let NumMicroOps = 5;
1100   let ResourceCycles = [1,1,1,2];
1101 }
1102 def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
1103                                             "ROR(8|16|32|64)m(1|i)")>;
1104
1105 def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> {
1106   let Latency = 2;
1107   let NumMicroOps = 2;
1108   let ResourceCycles = [2];
1109 }
1110 def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1111                                            ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1112
1113 def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1114   let Latency = 7;
1115   let NumMicroOps = 5;
1116   let ResourceCycles = [1,1,1,2];
1117 }
1118 def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
1119
1120 def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1121   let Latency = 7;
1122   let NumMicroOps = 5;
1123   let ResourceCycles = [1,1,1,1,1];
1124 }
1125 def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>;
1126 def: InstRW<[BWWriteResGroup89], (instrs FARCALL64)>;
1127
1128 def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1129   let Latency = 7;
1130   let NumMicroOps = 7;
1131   let ResourceCycles = [2,2,1,2];
1132 }
1133 def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
1134
1135 def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1136   let Latency = 8;
1137   let NumMicroOps = 2;
1138   let ResourceCycles = [1,1];
1139 }
1140 def: InstRW<[BWWriteResGroup91], (instrs MMX_CVTPI2PSirm,
1141                                          CVTDQ2PSrm,
1142                                          VCVTDQ2PSrm)>;
1143 def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>;
1144
1145 def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1146   let Latency = 8;
1147   let NumMicroOps = 2;
1148   let ResourceCycles = [1,1];
1149 }
1150 def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm,
1151                                          VPMOVSXBQYrm,
1152                                          VPMOVSXBWYrm,
1153                                          VPMOVSXDQYrm,
1154                                          VPMOVSXWDYrm,
1155                                          VPMOVSXWQYrm,
1156                                          VPMOVZXWDYrm)>;
1157
1158 def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1159   let Latency = 8;
1160   let NumMicroOps = 5;
1161   let ResourceCycles = [1,1,1,2];
1162 }
1163 def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)",
1164                                             "RCR(8|16|32|64)m(1|i)")>;
1165
1166 def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1167   let Latency = 8;
1168   let NumMicroOps = 6;
1169   let ResourceCycles = [1,1,1,3];
1170 }
1171 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
1172
1173 def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1174   let Latency = 8;
1175   let NumMicroOps = 6;
1176   let ResourceCycles = [1,1,1,2,1];
1177 }
1178 def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
1179 def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
1180                                              "ROR(8|16|32|64)mCL",
1181                                              "SAR(8|16|32|64)mCL",
1182                                              "SHL(8|16|32|64)mCL",
1183                                              "SHR(8|16|32|64)mCL")>;
1184
1185 def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
1186   let Latency = 9;
1187   let NumMicroOps = 2;
1188   let ResourceCycles = [1,1];
1189 }
1190 def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1191                                              "ILD_F(16|32|64)m")>;
1192 def: InstRW<[BWWriteResGroup101], (instrs VCVTPS2DQYrm,
1193                                           VCVTTPS2DQYrm)>;
1194
1195 def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1196   let Latency = 9;
1197   let NumMicroOps = 3;
1198   let ResourceCycles = [1,1,1];
1199 }
1200 def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm",
1201                                              "(V?)CVT(T?)SD2SI64rm",
1202                                              "(V?)CVT(T?)SD2SIrm",
1203                                              "VCVTTSS2SI64rm",
1204                                              "(V?)CVTTSS2SIrm")>;
1205
1206 def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1207   let Latency = 9;
1208   let NumMicroOps = 3;
1209   let ResourceCycles = [1,1,1];
1210 }
1211 def: InstRW<[BWWriteResGroup106], (instrs VCVTPS2PDYrm)>;
1212
1213 def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1214   let Latency = 9;
1215   let NumMicroOps = 3;
1216   let ResourceCycles = [1,1,1];
1217 }
1218 def: InstRW<[BWWriteResGroup107], (instrs CVTPD2PSrm,
1219                                           CVTPD2DQrm,
1220                                           CVTTPD2DQrm,
1221                                           MMX_CVTPI2PDirm)>;
1222 def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIirm",
1223                                              "(V?)CVTDQ2PDrm",
1224                                              "(V?)CVTSD2SSrm")>;
1225
1226 def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
1227   let Latency = 9;
1228   let NumMicroOps = 3;
1229   let ResourceCycles = [1,1,1];
1230 }
1231 def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
1232                                              "VPBROADCASTW(Y?)rm")>;
1233
1234 def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1235   let Latency = 9;
1236   let NumMicroOps = 5;
1237   let ResourceCycles = [1,1,3];
1238 }
1239 def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
1240
1241 def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1242   let Latency = 9;
1243   let NumMicroOps = 5;
1244   let ResourceCycles = [1,2,1,1];
1245 }
1246 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1247                                              "LSL(16|32|64)rm")>;
1248
1249 def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
1250   let Latency = 10;
1251   let NumMicroOps = 2;
1252   let ResourceCycles = [1,1];
1253 }
1254 def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>;
1255
1256 def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
1257   let Latency = 10;
1258   let NumMicroOps = 3;
1259   let ResourceCycles = [2,1];
1260 }
1261 def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>;
1262
1263 def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
1264   let Latency = 10;
1265   let NumMicroOps = 4;
1266   let ResourceCycles = [1,1,1,1];
1267 }
1268 def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
1269
1270 def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1271   let Latency = 11;
1272   let NumMicroOps = 1;
1273   let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
1274 }
1275 def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair
1276
1277 def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
1278   let Latency = 11;
1279   let NumMicroOps = 2;
1280   let ResourceCycles = [1,1];
1281 }
1282 def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>;
1283 def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>;
1284
1285 def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1286   let Latency = 11;
1287   let NumMicroOps = 3;
1288   let ResourceCycles = [1,1,1];
1289 }
1290 def: InstRW<[BWWriteResGroup128], (instrs VCVTDQ2PDYrm)>;
1291
1292 def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1293   let Latency = 11;
1294   let NumMicroOps = 7;
1295   let ResourceCycles = [2,2,3];
1296 }
1297 def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
1298                                              "RCR(16|32|64)rCL")>;
1299
1300 def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1301   let Latency = 11;
1302   let NumMicroOps = 9;
1303   let ResourceCycles = [1,4,1,3];
1304 }
1305 def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>;
1306
1307 def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
1308   let Latency = 11;
1309   let NumMicroOps = 11;
1310   let ResourceCycles = [2,9];
1311 }
1312 def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
1313 def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
1314
1315 def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
1316   let Latency = 12;
1317   let NumMicroOps = 3;
1318   let ResourceCycles = [2,1];
1319 }
1320 def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1321
1322 def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1323   let Latency = 14;
1324   let NumMicroOps = 1;
1325   let ResourceCycles = [1,4];
1326 }
1327 def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair
1328
1329 def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1330   let Latency = 14;
1331   let NumMicroOps = 3;
1332   let ResourceCycles = [1,1,1];
1333 }
1334 def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>;
1335
1336 def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1337   let Latency = 14;
1338   let NumMicroOps = 8;
1339   let ResourceCycles = [2,2,1,3];
1340 }
1341 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
1342
1343 def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1344   let Latency = 14;
1345   let NumMicroOps = 10;
1346   let ResourceCycles = [2,3,1,4];
1347 }
1348 def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>;
1349
1350 def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
1351   let Latency = 14;
1352   let NumMicroOps = 12;
1353   let ResourceCycles = [2,1,4,5];
1354 }
1355 def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>;
1356
1357 def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
1358   let Latency = 15;
1359   let NumMicroOps = 1;
1360   let ResourceCycles = [1];
1361 }
1362 def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1363
1364 def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1365   let Latency = 15;
1366   let NumMicroOps = 10;
1367   let ResourceCycles = [1,1,1,4,1,2];
1368 }
1369 def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
1370
1371 def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1372   let Latency = 16;
1373   let NumMicroOps = 2;
1374   let ResourceCycles = [1,1,5];
1375 }
1376 def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair
1377
1378 def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1379   let Latency = 16;
1380   let NumMicroOps = 14;
1381   let ResourceCycles = [1,1,1,4,2,5];
1382 }
1383 def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>;
1384
1385 def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> {
1386   let Latency = 8;
1387   let NumMicroOps = 20;
1388   let ResourceCycles = [1,1];
1389 }
1390 def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
1391
1392 def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
1393   let Latency = 18;
1394   let NumMicroOps = 8;
1395   let ResourceCycles = [1,1,1,5];
1396 }
1397 def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
1398 def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
1399
1400 def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1401   let Latency = 18;
1402   let NumMicroOps = 11;
1403   let ResourceCycles = [2,1,1,3,1,3];
1404 }
1405 def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
1406
1407 def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1408   let Latency = 19;
1409   let NumMicroOps = 2;
1410   let ResourceCycles = [1,1,8];
1411 }
1412 def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair
1413
1414 def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
1415   let Latency = 20;
1416   let NumMicroOps = 1;
1417   let ResourceCycles = [1];
1418 }
1419 def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1420
1421 def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1422   let Latency = 20;
1423   let NumMicroOps = 8;
1424   let ResourceCycles = [1,1,1,1,1,1,2];
1425 }
1426 def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>;
1427
1428 def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
1429   let Latency = 21;
1430   let NumMicroOps = 2;
1431   let ResourceCycles = [1,1];
1432 }
1433 def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>;
1434
1435 def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1436   let Latency = 21;
1437   let NumMicroOps = 19;
1438   let ResourceCycles = [2,1,4,1,1,4,6];
1439 }
1440 def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>;
1441
1442 def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1443   let Latency = 22;
1444   let NumMicroOps = 18;
1445   let ResourceCycles = [1,1,16];
1446 }
1447 def: InstRW<[BWWriteResGroup172], (instrs POPF64)>;
1448
1449 def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1450   let Latency = 23;
1451   let NumMicroOps = 19;
1452   let ResourceCycles = [3,1,15];
1453 }
1454 def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
1455
1456 def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1457   let Latency = 24;
1458   let NumMicroOps = 3;
1459   let ResourceCycles = [1,1,1];
1460 }
1461 def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>;
1462
1463 def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
1464   let Latency = 26;
1465   let NumMicroOps = 2;
1466   let ResourceCycles = [1,1];
1467 }
1468 def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>;
1469
1470 def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1471   let Latency = 29;
1472   let NumMicroOps = 3;
1473   let ResourceCycles = [1,1,1];
1474 }
1475 def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>;
1476
1477 def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1478   let Latency = 22;
1479   let NumMicroOps = 7;
1480   let ResourceCycles = [1,3,2,1];
1481 }
1482 def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
1483
1484 def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1485   let Latency = 23;
1486   let NumMicroOps = 9;
1487   let ResourceCycles = [1,3,4,1];
1488 }
1489 def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
1490
1491 def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1492   let Latency = 24;
1493   let NumMicroOps = 9;
1494   let ResourceCycles = [1,5,2,1];
1495 }
1496 def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
1497
1498 def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1499   let Latency = 25;
1500   let NumMicroOps = 7;
1501   let ResourceCycles = [1,3,2,1];
1502 }
1503 def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
1504                                             VGATHERDPSrm)>;
1505
1506 def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1507   let Latency = 26;
1508   let NumMicroOps = 9;
1509   let ResourceCycles = [1,5,2,1];
1510 }
1511 def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
1512
1513 def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1514   let Latency = 26;
1515   let NumMicroOps = 14;
1516   let ResourceCycles = [1,4,8,1];
1517 }
1518 def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
1519
1520 def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1521   let Latency = 27;
1522   let NumMicroOps = 9;
1523   let ResourceCycles = [1,5,2,1];
1524 }
1525 def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
1526
1527 def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1528   let Latency = 29;
1529   let NumMicroOps = 27;
1530   let ResourceCycles = [1,5,1,1,19];
1531 }
1532 def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>;
1533
1534 def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1535   let Latency = 30;
1536   let NumMicroOps = 28;
1537   let ResourceCycles = [1,6,1,1,19];
1538 }
1539 def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>;
1540 def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
1541
1542 def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
1543   let Latency = 34;
1544   let NumMicroOps = 23;
1545   let ResourceCycles = [1,5,3,4,10];
1546 }
1547 def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
1548                                              "IN(8|16|32)rr")>;
1549
1550 def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1551   let Latency = 35;
1552   let NumMicroOps = 23;
1553   let ResourceCycles = [1,5,2,1,4,10];
1554 }
1555 def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
1556                                              "OUT(8|16|32)rr")>;
1557
1558 def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
1559   let Latency = 42;
1560   let NumMicroOps = 22;
1561   let ResourceCycles = [2,20];
1562 }
1563 def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
1564
1565 def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
1566   let Latency = 60;
1567   let NumMicroOps = 64;
1568   let ResourceCycles = [2,2,8,1,10,2,39];
1569 }
1570 def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>;
1571
1572 def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1573   let Latency = 63;
1574   let NumMicroOps = 88;
1575   let ResourceCycles = [4,4,31,1,2,1,45];
1576 }
1577 def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
1578
1579 def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1580   let Latency = 63;
1581   let NumMicroOps = 90;
1582   let ResourceCycles = [4,2,33,1,2,1,47];
1583 }
1584 def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
1585
1586 def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
1587   let Latency = 75;
1588   let NumMicroOps = 15;
1589   let ResourceCycles = [6,3,6];
1590 }
1591 def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>;
1592
1593 def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
1594   let Latency = 115;
1595   let NumMicroOps = 100;
1596   let ResourceCycles = [9,9,11,8,1,11,21,30];
1597 }
1598 def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>;
1599
1600 def: InstRW<[WriteZero], (instrs CLC)>;
1601
1602
1603 // Intruction variants handled by the renamer. These might not need execution
1604 // ports in certain conditions.
1605 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1606 // section "Haswell and Broadwell Pipeline" > "Register allocation and
1607 // renaming".
1608 // These can be investigated with llvm-exegesis, e.g.
1609 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1610 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1611
1612 def BWWriteZeroLatency : SchedWriteRes<[]> {
1613   let Latency = 0;
1614 }
1615
1616 def BWWriteZeroIdiom : SchedWriteVariant<[
1617     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1618     SchedVar<NoSchedPred,                          [WriteALU]>
1619 ]>;
1620 def : InstRW<[BWWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1621                                          XOR32rr, XOR64rr)>;
1622
1623 def BWWriteFZeroIdiom : SchedWriteVariant<[
1624     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1625     SchedVar<NoSchedPred,                          [WriteFLogic]>
1626 ]>;
1627 def : InstRW<[BWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1628                                           VXORPDrr)>;
1629
1630 def BWWriteFZeroIdiomY : SchedWriteVariant<[
1631     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1632     SchedVar<NoSchedPred,                          [WriteFLogicY]>
1633 ]>;
1634 def : InstRW<[BWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1635
1636 def BWWriteVZeroIdiomLogicX : SchedWriteVariant<[
1637     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1638     SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1639 ]>;
1640 def : InstRW<[BWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1641
1642 def BWWriteVZeroIdiomLogicY : SchedWriteVariant<[
1643     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1644     SchedVar<NoSchedPred,                          [WriteVecLogicY]>
1645 ]>;
1646 def : InstRW<[BWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1647
1648 def BWWriteVZeroIdiomALUX : SchedWriteVariant<[
1649     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1650     SchedVar<NoSchedPred,                          [WriteVecALUX]>
1651 ]>;
1652 def : InstRW<[BWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
1653                                               PSUBDrr, VPSUBDrr,
1654                                               PSUBQrr, VPSUBQrr,
1655                                               PSUBWrr, VPSUBWrr,
1656                                               PCMPGTBrr, VPCMPGTBrr,
1657                                               PCMPGTDrr, VPCMPGTDrr,
1658                                               PCMPGTWrr, VPCMPGTWrr)>;
1659
1660 def BWWriteVZeroIdiomALUY : SchedWriteVariant<[
1661     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1662     SchedVar<NoSchedPred,                          [WriteVecALUY]>
1663 ]>;
1664 def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
1665                                               VPSUBDYrr,
1666                                               VPSUBQYrr,
1667                                               VPSUBWYrr,
1668                                               VPCMPGTBYrr,
1669                                               VPCMPGTDYrr,
1670                                               VPCMPGTWYrr)>;
1671
1672 def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> {
1673   let Latency = 5;
1674   let NumMicroOps = 1;
1675   let ResourceCycles = [1];
1676 }
1677
1678 def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1679     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1680     SchedVar<NoSchedPred,                          [BWWritePCMPGTQ]>
1681 ]>;
1682 def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1683                                                  VPCMPGTQYrr)>;
1684
1685
1686 // CMOVs that use both Z and C flag require an extra uop.
1687 def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> {
1688   let Latency = 2;
1689   let ResourceCycles = [1,1];
1690   let NumMicroOps = 2;
1691 }
1692
1693 def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1694   let Latency = 7;
1695   let ResourceCycles = [1,1,1];
1696   let NumMicroOps = 3;
1697 }
1698
1699 def BWCMOVA_CMOVBErr :  SchedWriteVariant<[
1700   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [BWWriteCMOVA_CMOVBErr]>,
1701   SchedVar<NoSchedPred,                             [WriteCMOV]>
1702 ]>;
1703
1704 def BWCMOVA_CMOVBErm :  SchedWriteVariant<[
1705   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>,
1706   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1707 ]>;
1708
1709 def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1710 def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1711
1712 // SETCCs that use both Z and C flag require an extra uop.
1713 def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> {
1714   let Latency = 2;
1715   let ResourceCycles = [1,1];
1716   let NumMicroOps = 2;
1717 }
1718
1719 def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1720   let Latency = 3;
1721   let ResourceCycles = [1,1,1,1];
1722   let NumMicroOps = 4;
1723 }
1724
1725 def BWSETA_SETBErr :  SchedWriteVariant<[
1726   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>,
1727   SchedVar<NoSchedPred,                         [WriteSETCC]>
1728 ]>;
1729
1730 def BWSETA_SETBErm :  SchedWriteVariant<[
1731   SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [BWWriteSETA_SETBEm]>,
1732   SchedVar<NoSchedPred,                         [WriteSETCCStore]>
1733 ]>;
1734
1735 def : InstRW<[BWSETA_SETBErr], (instrs SETCCr)>;
1736 def : InstRW<[BWSETA_SETBErm], (instrs SETCCm)>;
1737
1738 } // SchedModel