[AMDGPU] Check for immediate SrcC in mfma in AsmParser
[llvm-core.git] / lib / Target / X86 / X86SchedSkylakeClient.td
blob8f3e4ae62d53a8d3c07782f36c3eaac1d230447a
1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the machine model for Skylake Client to support
10 // instruction scheduling and other instruction cost heuristics.
12 //===----------------------------------------------------------------------===//
14 def SkylakeClientModel : SchedMachineModel {
15   // All x86 instructions are modeled as a single micro-op, and SKylake can
16   // decode 6 instructions per cycle.
17   let IssueWidth = 6;
18   let MicroOpBufferSize = 224; // Based on the reorder buffer.
19   let LoadLatency = 5;
20   let MispredictPenalty = 14;
22   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23   let LoopMicroOpBufferSize = 50;
25   // This flag is set to allow the scheduler to assign a default model to
26   // unrecognized opcodes.
27   let CompleteModel = 0;
30 let SchedModel = SkylakeClientModel in {
32 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
34 // Ports 0, 1, 5, and 6 handle all computation.
35 // Port 4 gets the data half of stores. Store data can be available later than
36 // the store address, but since we don't model the latency of stores, we can
37 // ignore that.
38 // Ports 2 and 3 are identical. They handle loads and the address half of
39 // stores. Port 7 can handle address calculations.
40 def SKLPort0 : ProcResource<1>;
41 def SKLPort1 : ProcResource<1>;
42 def SKLPort2 : ProcResource<1>;
43 def SKLPort3 : ProcResource<1>;
44 def SKLPort4 : ProcResource<1>;
45 def SKLPort5 : ProcResource<1>;
46 def SKLPort6 : ProcResource<1>;
47 def SKLPort7 : ProcResource<1>;
49 // Many micro-ops are capable of issuing on multiple ports.
50 def SKLPort01  : ProcResGroup<[SKLPort0, SKLPort1]>;
51 def SKLPort23  : ProcResGroup<[SKLPort2, SKLPort3]>;
52 def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
53 def SKLPort04  : ProcResGroup<[SKLPort0, SKLPort4]>;
54 def SKLPort05  : ProcResGroup<[SKLPort0, SKLPort5]>;
55 def SKLPort06  : ProcResGroup<[SKLPort0, SKLPort6]>;
56 def SKLPort15  : ProcResGroup<[SKLPort1, SKLPort5]>;
57 def SKLPort16  : ProcResGroup<[SKLPort1, SKLPort6]>;
58 def SKLPort56  : ProcResGroup<[SKLPort5, SKLPort6]>;
59 def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
60 def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
61 def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
63 def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
64 // FP division and sqrt on port 0.
65 def SKLFPDivider : ProcResource<1>;
67 // 60 Entry Unified Scheduler
68 def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
69                               SKLPort5, SKLPort6, SKLPort7]> {
70   let BufferSize=60;
73 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
74 // cycles after the memory operand.
75 def : ReadAdvance<ReadAfterLd, 5>;
77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
78 // until 5/6/7 cycles after the memory operand.
79 def : ReadAdvance<ReadAfterVecLd, 5>;
80 def : ReadAdvance<ReadAfterVecXLd, 6>;
81 def : ReadAdvance<ReadAfterVecYLd, 7>;
83 def : ReadAdvance<ReadInt2Fpu, 0>;
85 // Many SchedWrites are defined in pairs with and without a folded load.
86 // Instructions with folded loads are usually micro-fused, so they only appear
87 // as two micro-ops when queued in the reservation station.
88 // This multiclass defines the resource usage for variants with and without
89 // folded loads.
90 multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
91                           list<ProcResourceKind> ExePorts,
92                           int Lat, list<int> Res = [1], int UOps = 1,
93                           int LoadLat = 5> {
94   // Register variant is using a single cycle on ExePort.
95   def : WriteRes<SchedRW, ExePorts> {
96     let Latency = Lat;
97     let ResourceCycles = Res;
98     let NumMicroOps = UOps;
99   }
101   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
102   // the latency (default = 5).
103   def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
104     let Latency = !add(Lat, LoadLat);
105     let ResourceCycles = !listconcat([1], Res);
106     let NumMicroOps = !add(UOps, 1);
107   }
110 // A folded store needs a cycle on port 4 for the store data, and an extra port
111 // 2/3/7 cycle to recompute the address.
112 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
114 // Arithmetic.
115 defm : SKLWriteResPair<WriteALU,    [SKLPort0156], 1>; // Simple integer ALU op.
116 defm : SKLWriteResPair<WriteADC,    [SKLPort06],   1>; // Integer ALU + flags op.
118 // Integer multiplication.
119 defm : SKLWriteResPair<WriteIMul8,     [SKLPort1],   3>;
120 defm : SKLWriteResPair<WriteIMul16,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>;
121 defm : X86WriteRes<WriteIMul16Imm,     [SKLPort1,SKLPort0156], 4, [1,1], 2>;
122 defm : X86WriteRes<WriteIMul16ImmLd,   [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>;
123 defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1],   3>;
124 defm : SKLWriteResPair<WriteIMul32,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
125 defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1],   3>;
126 defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1],   3>;
127 defm : SKLWriteResPair<WriteIMul64,    [SKLPort1,SKLPort5], 4, [1,1], 2>;
128 defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1],   3>;
129 defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1],   3>;
130 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
132 defm : X86WriteRes<WriteBSWAP32,    [SKLPort15], 1, [1], 1>;
133 defm : X86WriteRes<WriteBSWAP64,    [SKLPort06, SKLPort15], 2, [1,1], 2>;
134 defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>;
135 defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>;
136 defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>;
138 // TODO: Why isn't the SKLDivider used?
139 defm : SKLWriteResPair<WriteDiv8,   [SKLPort0,SKLDivider], 25, [1,10], 1, 4>;
140 defm : X86WriteRes<WriteDiv16,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
141 defm : X86WriteRes<WriteDiv32,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
142 defm : X86WriteRes<WriteDiv64,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
143 defm : X86WriteRes<WriteDiv16Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
144 defm : X86WriteRes<WriteDiv32Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
145 defm : X86WriteRes<WriteDiv64Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
147 defm : X86WriteRes<WriteIDiv8,    [SKLPort0,SKLDivider], 25, [1,10], 1>;
148 defm : X86WriteRes<WriteIDiv16,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
149 defm : X86WriteRes<WriteIDiv32,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
150 defm : X86WriteRes<WriteIDiv64,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
151 defm : X86WriteRes<WriteIDiv8Ld,  [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
152 defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
153 defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
154 defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
156 defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
158 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
160 defm : SKLWriteResPair<WriteCMOV,  [SKLPort06], 1, [1], 1>; // Conditional move.
161 defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move.
162 def  : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
163 def  : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
164   let Latency = 2;
165   let NumMicroOps = 3;
168 defm : X86WriteRes<WriteLAHFSAHF,        [SKLPort06], 1, [1], 1>;
169 defm : X86WriteRes<WriteBitTest,         [SKLPort06], 1, [1], 1>;
170 defm : X86WriteRes<WriteBitTestImmLd,    [SKLPort06,SKLPort23], 6, [1,1], 2>;
171 defm : X86WriteRes<WriteBitTestRegLd,    [SKLPort0156,SKLPort23], 6, [1,1], 2>;
172 defm : X86WriteRes<WriteBitTestSet,      [SKLPort06], 1, [1], 1>;
173 defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>;
174 defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>;
176 // Bit counts.
177 defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
178 defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;
179 defm : SKLWriteResPair<WriteLZCNT,          [SKLPort1], 3>;
180 defm : SKLWriteResPair<WriteTZCNT,          [SKLPort1], 3>;
181 defm : SKLWriteResPair<WritePOPCNT,         [SKLPort1], 3>;
183 // Integer shifts and rotates.
184 defm : SKLWriteResPair<WriteShift,    [SKLPort06],  1>;
185 defm : SKLWriteResPair<WriteShiftCL,  [SKLPort06],  3, [3], 3>;
186 defm : SKLWriteResPair<WriteRotate,   [SKLPort06],  1, [1], 1>;
187 defm : SKLWriteResPair<WriteRotateCL, [SKLPort06],  3, [3], 3>;
189 // SHLD/SHRD.
190 defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;
191 defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>;
192 defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>;
193 defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>;
195 // BMI1 BEXTR/BLS, BMI2 BZHI
196 defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;
197 defm : SKLWriteResPair<WriteBLS,   [SKLPort15], 1>;
198 defm : SKLWriteResPair<WriteBZHI,  [SKLPort15], 1>;
200 // Loads, stores, and moves, not folded with other operations.
201 defm : X86WriteRes<WriteLoad,    [SKLPort23], 5, [1], 1>;
202 defm : X86WriteRes<WriteStore,   [SKLPort237, SKLPort4], 1, [1,1], 1>;
203 defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;
204 defm : X86WriteRes<WriteMove,    [SKLPort0156], 1, [1], 1>;
206 // Idioms that clear a register, like xorps %xmm0, %xmm0.
207 // These can often bypass execution ports completely.
208 def : WriteRes<WriteZero,  []>;
210 // Branches don't produce values, so they have no latency, but they still
211 // consume resources. Indirect branches can fold loads.
212 defm : SKLWriteResPair<WriteJump,  [SKLPort06],   1>;
214 // Floating point. This covers both scalar and vector operations.
215 defm : X86WriteRes<WriteFLD0,          [SKLPort05], 1, [1], 1>;
216 defm : X86WriteRes<WriteFLD1,          [SKLPort05], 1, [2], 2>;
217 defm : X86WriteRes<WriteFLDC,          [SKLPort05], 1, [2], 2>;
218 defm : X86WriteRes<WriteFLoad,         [SKLPort23], 5, [1], 1>;
219 defm : X86WriteRes<WriteFLoadX,        [SKLPort23], 6, [1], 1>;
220 defm : X86WriteRes<WriteFLoadY,        [SKLPort23], 7, [1], 1>;
221 defm : X86WriteRes<WriteFMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
222 defm : X86WriteRes<WriteFMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
223 defm : X86WriteRes<WriteFStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
224 defm : X86WriteRes<WriteFStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
225 defm : X86WriteRes<WriteFStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
226 defm : X86WriteRes<WriteFStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
227 defm : X86WriteRes<WriteFStoreNTX,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
228 defm : X86WriteRes<WriteFStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
229 defm : X86WriteRes<WriteFMaskedStore,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
230 defm : X86WriteRes<WriteFMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>;
231 defm : X86WriteRes<WriteFMove,         [SKLPort015], 1, [1], 1>;
232 defm : X86WriteRes<WriteFMoveX,        [SKLPort015], 1, [1], 1>;
233 defm : X86WriteRes<WriteFMoveY,        [SKLPort015], 1, [1], 1>;
234 defm : X86WriteRes<WriteEMMS,          [SKLPort05,SKLPort0156], 10, [9,1], 10>;
236 defm : SKLWriteResPair<WriteFAdd,     [SKLPort01],  4, [1], 1, 5>; // Floating point add/sub.
237 defm : SKLWriteResPair<WriteFAddX,    [SKLPort01],  4, [1], 1, 6>;
238 defm : SKLWriteResPair<WriteFAddY,    [SKLPort01],  4, [1], 1, 7>;
239 defm : X86WriteResPairUnsupported<WriteFAddZ>;
240 defm : SKLWriteResPair<WriteFAdd64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double add/sub.
241 defm : SKLWriteResPair<WriteFAdd64X,  [SKLPort01],  4, [1], 1, 6>;
242 defm : SKLWriteResPair<WriteFAdd64Y,  [SKLPort01],  4, [1], 1, 7>;
243 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
245 defm : SKLWriteResPair<WriteFCmp,     [SKLPort01],  4, [1], 1, 5>; // Floating point compare.
246 defm : SKLWriteResPair<WriteFCmpX,    [SKLPort01],  4, [1], 1, 6>;
247 defm : SKLWriteResPair<WriteFCmpY,    [SKLPort01],  4, [1], 1, 7>;
248 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
249 defm : SKLWriteResPair<WriteFCmp64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double compare.
250 defm : SKLWriteResPair<WriteFCmp64X,  [SKLPort01],  4, [1], 1, 6>;
251 defm : SKLWriteResPair<WriteFCmp64Y,  [SKLPort01],  4, [1], 1, 7>;
252 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
254 defm : SKLWriteResPair<WriteFCom,      [SKLPort0],  2>; // Floating point compare to flags.
256 defm : SKLWriteResPair<WriteFMul,     [SKLPort01],  4, [1], 1, 5>; // Floating point multiplication.
257 defm : SKLWriteResPair<WriteFMulX,    [SKLPort01],  4, [1], 1, 6>;
258 defm : SKLWriteResPair<WriteFMulY,    [SKLPort01],  4, [1], 1, 7>;
259 defm : X86WriteResPairUnsupported<WriteFMulZ>;
260 defm : SKLWriteResPair<WriteFMul64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double multiplication.
261 defm : SKLWriteResPair<WriteFMul64X,  [SKLPort01],  4, [1], 1, 6>;
262 defm : SKLWriteResPair<WriteFMul64Y,  [SKLPort01],  4, [1], 1, 7>;
263 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
265 defm : SKLWriteResPair<WriteFDiv,     [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.
266 //defm : SKLWriteResPair<WriteFDivX,    [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>;
267 defm : SKLWriteResPair<WriteFDivY,    [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>;
268 defm : X86WriteResPairUnsupported<WriteFDivZ>;
269 //defm : SKLWriteResPair<WriteFDiv64,   [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division.
270 //defm : SKLWriteResPair<WriteFDiv64X,  [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>;
271 //defm : SKLWriteResPair<WriteFDiv64Y,  [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>;
272 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
274 defm : SKLWriteResPair<WriteFSqrt,    [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
275 defm : SKLWriteResPair<WriteFSqrtX,   [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>;
276 defm : SKLWriteResPair<WriteFSqrtY,   [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>;
277 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
278 defm : SKLWriteResPair<WriteFSqrt64,  [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
279 defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>;
280 defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>;
281 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
282 defm : SKLWriteResPair<WriteFSqrt80,  [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root.
284 defm : SKLWriteResPair<WriteFRcp,   [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
285 defm : SKLWriteResPair<WriteFRcpX,  [SKLPort0], 4, [1], 1, 6>;
286 defm : SKLWriteResPair<WriteFRcpY,  [SKLPort0], 4, [1], 1, 7>;
287 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
289 defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
290 defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>;
291 defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>;
292 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
294 defm : SKLWriteResPair<WriteFMA,    [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add.
295 defm : SKLWriteResPair<WriteFMAX,   [SKLPort01], 4, [1], 1, 6>;
296 defm : SKLWriteResPair<WriteFMAY,   [SKLPort01], 4, [1], 1, 7>;
297 defm : X86WriteResPairUnsupported<WriteFMAZ>;
298 defm : SKLWriteResPair<WriteDPPD,   [SKLPort5,SKLPort01],  9, [1,2], 3, 6>; // Floating point double dot product.
299 defm : SKLWriteResPair<WriteDPPS,   [SKLPort5,SKLPort01], 13, [1,3], 4, 6>;
300 defm : SKLWriteResPair<WriteDPPSY,  [SKLPort5,SKLPort01], 13, [1,3], 4, 7>;
301 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
302 defm : SKLWriteResPair<WriteFSign,   [SKLPort0], 1>; // Floating point fabs/fchs.
303 defm : SKLWriteResPair<WriteFRnd,     [SKLPort01], 8, [2], 2, 6>; // Floating point rounding.
304 defm : SKLWriteResPair<WriteFRndY,    [SKLPort01], 8, [2], 2, 7>;
305 defm : X86WriteResPairUnsupported<WriteFRndZ>;
306 defm : SKLWriteResPair<WriteFLogic,  [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
307 defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>;
308 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
309 defm : SKLWriteResPair<WriteFTest,   [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
310 defm : SKLWriteResPair<WriteFTestY,  [SKLPort0], 2, [1], 1, 7>;
311 defm : X86WriteResPairUnsupported<WriteFTestZ>;
312 defm : SKLWriteResPair<WriteFShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
313 defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>;
314 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
315 defm : SKLWriteResPair<WriteFVarShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
316 defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
317 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
318 defm : SKLWriteResPair<WriteFBlend,  [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends.
319 defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>;
320 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
321 defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends.
322 defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>;
323 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
325 // FMA Scheduling helper class.
326 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
328 // Vector integer operations.
329 defm : X86WriteRes<WriteVecLoad,         [SKLPort23], 5, [1], 1>;
330 defm : X86WriteRes<WriteVecLoadX,        [SKLPort23], 6, [1], 1>;
331 defm : X86WriteRes<WriteVecLoadY,        [SKLPort23], 7, [1], 1>;
332 defm : X86WriteRes<WriteVecLoadNT,       [SKLPort23], 6, [1], 1>;
333 defm : X86WriteRes<WriteVecLoadNTY,      [SKLPort23], 7, [1], 1>;
334 defm : X86WriteRes<WriteVecMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
335 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
336 defm : X86WriteRes<WriteVecStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
337 defm : X86WriteRes<WriteVecStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
338 defm : X86WriteRes<WriteVecStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
339 defm : X86WriteRes<WriteVecStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
340 defm : X86WriteRes<WriteVecStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
341 defm : X86WriteRes<WriteVecMaskedStore,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
342 defm : X86WriteRes<WriteVecMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>;
343 defm : X86WriteRes<WriteVecMove,         [SKLPort05],  1, [1], 1>;
344 defm : X86WriteRes<WriteVecMoveX,        [SKLPort015], 1, [1], 1>;
345 defm : X86WriteRes<WriteVecMoveY,        [SKLPort015], 1, [1], 1>;
346 defm : X86WriteRes<WriteVecMoveToGpr,    [SKLPort0], 2, [1], 1>;
347 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKLPort5], 1, [1], 1>;
349 defm : SKLWriteResPair<WriteVecALU,   [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
350 defm : SKLWriteResPair<WriteVecALUX,  [SKLPort01], 1, [1], 1, 6>;
351 defm : SKLWriteResPair<WriteVecALUY,  [SKLPort01], 1, [1], 1, 7>;
352 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
353 defm : SKLWriteResPair<WriteVecLogic, [SKLPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
354 defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>;
355 defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>;
356 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
357 defm : SKLWriteResPair<WriteVecTest,  [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
358 defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>;
359 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
360 defm : SKLWriteResPair<WriteVecIMul,  [SKLPort0] ,  4, [1], 1, 5>; // Vector integer multiply.
361 defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01],  4, [1], 1, 6>;
362 defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01],  4, [1], 1, 7>;
363 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
364 defm : SKLWriteResPair<WritePMULLD,   [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD.
365 defm : SKLWriteResPair<WritePMULLDY,  [SKLPort01], 10, [2], 2, 7>;
366 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
367 defm : SKLWriteResPair<WriteShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
368 defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;
369 defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;
370 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
371 defm : SKLWriteResPair<WriteVarShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
372 defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;
373 defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
374 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
375 defm : SKLWriteResPair<WriteBlend,  [SKLPort5], 1, [1], 1, 6>; // Vector blends.
376 defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>;
377 defm : X86WriteResPairUnsupported<WriteBlendZ>;
378 defm : SKLWriteResPair<WriteVarBlend,  [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
379 defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>;
380 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
381 defm : SKLWriteResPair<WriteMPSAD,  [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
382 defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>;
383 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
384 defm : SKLWriteResPair<WritePSADBW,  [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW.
385 defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;
386 defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;
387 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
388 defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
390 // Vector integer shifts.
391 defm : SKLWriteResPair<WriteVecShift,     [SKLPort0], 1, [1], 1, 5>;
392 defm : X86WriteRes<WriteVecShiftX,        [SKLPort5,SKLPort01],  2, [1,1], 2>;
393 defm : X86WriteRes<WriteVecShiftY,        [SKLPort5,SKLPort01],  4, [1,1], 2>;
394 defm : X86WriteRes<WriteVecShiftXLd,      [SKLPort01,SKLPort23], 7, [1,1], 2>;
395 defm : X86WriteRes<WriteVecShiftYLd,      [SKLPort01,SKLPort23], 8, [1,1], 2>;
396 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
398 defm : SKLWriteResPair<WriteVecShiftImm,  [SKLPort0],  1, [1], 1, 5>; // Vector integer immediate shifts.
399 defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>;
400 defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>;
401 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
402 defm : SKLWriteResPair<WriteVarVecShift,  [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.
403 defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;
404 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
406 // Vector insert/extract operations.
407 def : WriteRes<WriteVecInsert, [SKLPort5]> {
408   let Latency = 2;
409   let NumMicroOps = 2;
410   let ResourceCycles = [2];
412 def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
413   let Latency = 6;
414   let NumMicroOps = 2;
416 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
418 def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {
419   let Latency = 3;
420   let NumMicroOps = 2;
422 def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> {
423   let Latency = 2;
424   let NumMicroOps = 3;
427 // Conversion between integer and float.
428 defm : SKLWriteResPair<WriteCvtSS2I,   [SKLPort1], 3>;
429 defm : SKLWriteResPair<WriteCvtPS2I,   [SKLPort1], 3>;
430 defm : SKLWriteResPair<WriteCvtPS2IY,  [SKLPort1], 3>;
431 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
432 defm : SKLWriteResPair<WriteCvtSD2I,   [SKLPort1], 3>;
433 defm : SKLWriteResPair<WriteCvtPD2I,   [SKLPort1], 3>;
434 defm : SKLWriteResPair<WriteCvtPD2IY,  [SKLPort1], 3>;
435 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
437 defm : SKLWriteResPair<WriteCvtI2SS,   [SKLPort1], 4>;
438 defm : SKLWriteResPair<WriteCvtI2PS,   [SKLPort1], 4>;
439 defm : SKLWriteResPair<WriteCvtI2PSY,  [SKLPort1], 4>;
440 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
441 defm : SKLWriteResPair<WriteCvtI2SD,   [SKLPort1], 4>;
442 defm : SKLWriteResPair<WriteCvtI2PD,   [SKLPort1], 4>;
443 defm : SKLWriteResPair<WriteCvtI2PDY,  [SKLPort1], 4>;
444 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
446 defm : SKLWriteResPair<WriteCvtSS2SD,  [SKLPort1], 3>;
447 defm : SKLWriteResPair<WriteCvtPS2PD,  [SKLPort1], 3>;
448 defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>;
449 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
450 defm : SKLWriteResPair<WriteCvtSD2SS,  [SKLPort1], 3>;
451 defm : SKLWriteResPair<WriteCvtPD2PS,  [SKLPort1], 3>;
452 defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>;
453 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
455 defm : X86WriteRes<WriteCvtPH2PS,    [SKLPort5,SKLPort015],  5, [1,1], 2>;
456 defm : X86WriteRes<WriteCvtPH2PSY,    [SKLPort5,SKLPort01],  7, [1,1], 2>;
457 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
458 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKLPort23,SKLPort01],  9, [1,1], 2>;
459 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
460 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
462 defm : X86WriteRes<WriteCvtPS2PH,                       [SKLPort5,SKLPort015], 5, [1,1], 2>;
463 defm : X86WriteRes<WriteCvtPS2PHY,                       [SKLPort5,SKLPort01], 7, [1,1], 2>;
464 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
465 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>;
466 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>;
467 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
469 // Strings instructions.
471 // Packed Compare Implicit Length Strings, Return Mask
472 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
473   let Latency = 10;
474   let NumMicroOps = 3;
475   let ResourceCycles = [3];
477 def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
478   let Latency = 16;
479   let NumMicroOps = 4;
480   let ResourceCycles = [3,1];
483 // Packed Compare Explicit Length Strings, Return Mask
484 def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
485   let Latency = 19;
486   let NumMicroOps = 9;
487   let ResourceCycles = [4,3,1,1];
489 def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
490   let Latency = 25;
491   let NumMicroOps = 10;
492   let ResourceCycles = [4,3,1,1,1];
495 // Packed Compare Implicit Length Strings, Return Index
496 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
497   let Latency = 10;
498   let NumMicroOps = 3;
499   let ResourceCycles = [3];
501 def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
502   let Latency = 16;
503   let NumMicroOps = 4;
504   let ResourceCycles = [3,1];
507 // Packed Compare Explicit Length Strings, Return Index
508 def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
509   let Latency = 18;
510   let NumMicroOps = 8;
511   let ResourceCycles = [4,3,1];
513 def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
514   let Latency = 24;
515   let NumMicroOps = 9;
516   let ResourceCycles = [4,3,1,1];
519 // MOVMSK Instructions.
520 def : WriteRes<WriteFMOVMSK,    [SKLPort0]> { let Latency = 2; }
521 def : WriteRes<WriteVecMOVMSK,  [SKLPort0]> { let Latency = 2; }
522 def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }
523 def : WriteRes<WriteMMXMOVMSK,  [SKLPort0]> { let Latency = 2; }
525 // AES instructions.
526 def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
527   let Latency = 4;
528   let NumMicroOps = 1;
529   let ResourceCycles = [1];
531 def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
532   let Latency = 10;
533   let NumMicroOps = 2;
534   let ResourceCycles = [1,1];
537 def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
538   let Latency = 8;
539   let NumMicroOps = 2;
540   let ResourceCycles = [2];
542 def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
543   let Latency = 14;
544   let NumMicroOps = 3;
545   let ResourceCycles = [2,1];
548 def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
549   let Latency = 20;
550   let NumMicroOps = 11;
551   let ResourceCycles = [3,6,2];
553 def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
554   let Latency = 25;
555   let NumMicroOps = 11;
556   let ResourceCycles = [3,6,1,1];
559 // Carry-less multiplication instructions.
560 def : WriteRes<WriteCLMul, [SKLPort5]> {
561   let Latency = 6;
562   let NumMicroOps = 1;
563   let ResourceCycles = [1];
565 def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
566   let Latency = 12;
567   let NumMicroOps = 2;
568   let ResourceCycles = [1,1];
571 // Catch-all for expensive system instructions.
572 def : WriteRes<WriteSystem,     [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
574 // AVX2.
575 defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
576 defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
577 defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
578 defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
580 // Old microcoded instructions that nobody use.
581 def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
583 // Fence instructions.
584 def : WriteRes<WriteFence,  [SKLPort23, SKLPort4]>;
586 // Load/store MXCSR.
587 def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
588 def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
590 // Nop, not very useful expect it provides a model for nops!
591 def : WriteRes<WriteNop, []>;
593 ////////////////////////////////////////////////////////////////////////////////
594 // Horizontal add/sub  instructions.
595 ////////////////////////////////////////////////////////////////////////////////
597 defm : SKLWriteResPair<WriteFHAdd,  [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
598 defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;
599 defm : SKLWriteResPair<WritePHAdd,  [SKLPort5,SKLPort05],  3, [2,1], 3, 5>;
600 defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;
601 defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
603 // Remaining instrs.
605 def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
606   let Latency = 1;
607   let NumMicroOps = 1;
608   let ResourceCycles = [1];
610 def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr",
611                                             "MMX_PADDUS(B|W)irr",
612                                             "MMX_PAVG(B|W)irr",
613                                             "MMX_PCMPEQ(B|D|W)irr",
614                                             "MMX_PCMPGT(B|D|W)irr",
615                                             "MMX_P(MAX|MIN)SWirr",
616                                             "MMX_P(MAX|MIN)UBirr",
617                                             "MMX_PSUBS(B|W)irr",
618                                             "MMX_PSUBUS(B|W)irr")>;
620 def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
621   let Latency = 1;
622   let NumMicroOps = 1;
623   let ResourceCycles = [1];
625 def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
626                                             "UCOM_F(P?)r")>;
628 def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
629   let Latency = 1;
630   let NumMicroOps = 1;
631   let ResourceCycles = [1];
633 def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
635 def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
636   let Latency = 1;
637   let NumMicroOps = 1;
638   let ResourceCycles = [1];
640 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
642 def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
643   let Latency = 1;
644   let NumMicroOps = 1;
645   let ResourceCycles = [1];
647 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
649 def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
650   let Latency = 1;
651   let NumMicroOps = 1;
652   let ResourceCycles = [1];
654 def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;
656 def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
657   let Latency = 1;
658   let NumMicroOps = 1;
659   let ResourceCycles = [1];
661 def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
662                                             "VPBLENDD(Y?)rri")>;
664 def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
665   let Latency = 1;
666   let NumMicroOps = 1;
667   let ResourceCycles = [1];
669 def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
670                                           CMC, STC,
671                                           SGDT64m,
672                                           SIDT64m,
673                                           SMSW16m,
674                                           STRm,
675                                           SYSCALL)>;
677 def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
678   let Latency = 1;
679   let NumMicroOps = 2;
680   let ResourceCycles = [1,1];
682 def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
683 def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>;
685 def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
686   let Latency = 2;
687   let NumMicroOps = 2;
688   let ResourceCycles = [2];
690 def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
692 def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
693   let Latency = 2;
694   let NumMicroOps = 2;
695   let ResourceCycles = [2];
697 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
698                                           MMX_MOVDQ2Qrr)>;
700 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
701   let Latency = 2;
702   let NumMicroOps = 2;
703   let ResourceCycles = [2];
705 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
706                                           WAIT,
707                                           XGETBV)>;
709 def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
710   let Latency = 2;
711   let NumMicroOps = 2;
712   let ResourceCycles = [1,1];
714 def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
716 def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
717   let Latency = 2;
718   let NumMicroOps = 2;
719   let ResourceCycles = [1,1];
721 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
723 def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
724   let Latency = 2;
725   let NumMicroOps = 2;
726   let ResourceCycles = [1,1];
728 def: InstRW<[SKLWriteResGroup23], (instrs CWD,
729                                           JCXZ, JECXZ, JRCXZ,
730                                           ADC8i8, SBB8i8,
731                                           ADC16i16, SBB16i16,
732                                           ADC32i32, SBB32i32,
733                                           ADC64i32, SBB64i32)>;
735 def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
736   let Latency = 2;
737   let NumMicroOps = 3;
738   let ResourceCycles = [1,1,1];
740 def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
742 def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
743   let Latency = 2;
744   let NumMicroOps = 3;
745   let ResourceCycles = [1,1,1];
747 def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
749 def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
750   let Latency = 2;
751   let NumMicroOps = 3;
752   let ResourceCycles = [1,1,1];
754 def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
755                                           STOSB, STOSL, STOSQ, STOSW)>;
756 def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
758 def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
759   let Latency = 3;
760   let NumMicroOps = 1;
761   let ResourceCycles = [1];
763 def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
764                                              "PEXT(32|64)rr")>;
766 def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
767   let Latency = 3;
768   let NumMicroOps = 1;
769   let ResourceCycles = [1];
771 def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
772                                              "VPBROADCAST(B|W)rr")>;
774 def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
775   let Latency = 3;
776   let NumMicroOps = 2;
777   let ResourceCycles = [1,1];
779 def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
781 def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
782   let Latency = 3;
783   let NumMicroOps = 3;
784   let ResourceCycles = [1,2];
786 def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
788 def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
789   let Latency = 3;
790   let NumMicroOps = 3;
791   let ResourceCycles = [2,1];
793 def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
794                                              "(V?)PHSUBSW(Y?)rr")>;
796 def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
797   let Latency = 3;
798   let NumMicroOps = 3;
799   let ResourceCycles = [2,1];
801 def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWirr,
802                                           MMX_PACKSSWBirr,
803                                           MMX_PACKUSWBirr)>;
805 def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
806   let Latency = 3;
807   let NumMicroOps = 3;
808   let ResourceCycles = [1,2];
810 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
812 def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
813   let Latency = 3;
814   let NumMicroOps = 3;
815   let ResourceCycles = [1,2];
817 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
819 def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
820   let Latency = 3;
821   let NumMicroOps = 3;
822   let ResourceCycles = [1,2];
824 def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r(1|i)",
825                                              "RCR(8|16|32|64)r(1|i)")>;
827 def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
828   let Latency = 3;
829   let NumMicroOps = 3;
830   let ResourceCycles = [1,1,1];
832 def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
834 def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
835   let Latency = 3;
836   let NumMicroOps = 4;
837   let ResourceCycles = [1,1,1,1];
839 def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
841 def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
842   let Latency = 3;
843   let NumMicroOps = 4;
844   let ResourceCycles = [1,1,1,1];
846 def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
848 def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
849   let Latency = 4;
850   let NumMicroOps = 1;
851   let ResourceCycles = [1];
853 def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
855 def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
856   let Latency = 4;
857   let NumMicroOps = 1;
858   let ResourceCycles = [1];
860 def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr",
861                                              "(V?)CVT(T?)PS2DQ(Y?)rr")>;
863 def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
864   let Latency = 4;
865   let NumMicroOps = 3;
866   let ResourceCycles = [1,1,1];
868 def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
869                                              "IST_F(16|32)m")>;
871 def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
872   let Latency = 4;
873   let NumMicroOps = 4;
874   let ResourceCycles = [4];
876 def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
878 def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
879   let Latency = 4;
880   let NumMicroOps = 4;
881   let ResourceCycles = [1,3];
883 def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
885 def SKLWriteResGroup56 : SchedWriteRes<[]> {
886   let Latency = 0;
887   let NumMicroOps = 4;
888   let ResourceCycles = [];
890 def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
892 def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
893   let Latency = 4;
894   let NumMicroOps = 4;
895   let ResourceCycles = [1,1,2];
897 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
899 def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
900   let Latency = 5;
901   let NumMicroOps = 1;
902   let ResourceCycles = [1];
904 def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
905                                              "MOVZX(16|32|64)rm(8|16)",
906                                              "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67?
908 def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
909   let Latency = 5;
910   let NumMicroOps = 2;
911   let ResourceCycles = [1,1];
913 def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDirr,
914                                           CVTDQ2PDrr,
915                                           VCVTDQ2PDrr)>;
917 def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
918   let Latency = 5;
919   let NumMicroOps = 2;
920   let ResourceCycles = [1,1];
922 def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr",
923                                              "MMX_CVT(T?)PS2PIirr",
924                                              "(V?)CVT(T?)PD2DQrr",
925                                              "(V?)CVTPD2PSrr",
926                                              "(V?)CVTPS2PDrr",
927                                              "(V?)CVTSD2SSrr",
928                                              "(V?)CVTSI642SDrr",
929                                              "(V?)CVTSI2SDrr",
930                                              "(V?)CVTSI2SSrr",
931                                              "(V?)CVTSS2SDrr")>;
933 def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
934   let Latency = 5;
935   let NumMicroOps = 3;
936   let ResourceCycles = [1,1,1];
938 def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
940 def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
941   let Latency = 5;
942   let NumMicroOps = 5;
943   let ResourceCycles = [1,4];
945 def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
947 def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
948   let Latency = 5;
949   let NumMicroOps = 6;
950   let ResourceCycles = [1,1,4];
952 def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
954 def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
955   let Latency = 6;
956   let NumMicroOps = 1;
957   let ResourceCycles = [1];
959 def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm,
960                                           VPBROADCASTDrm,
961                                           VPBROADCASTQrm)>;
962 def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm",
963                                              "(V?)MOVSLDUPrm")>;
965 def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
966   let Latency = 6;
967   let NumMicroOps = 2;
968   let ResourceCycles = [2];
970 def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSirr)>;
972 def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
973   let Latency = 6;
974   let NumMicroOps = 2;
975   let ResourceCycles = [1,1];
977 def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBirm,
978                                           MMX_PADDSWirm,
979                                           MMX_PADDUSBirm,
980                                           MMX_PADDUSWirm,
981                                           MMX_PAVGBirm,
982                                           MMX_PAVGWirm,
983                                           MMX_PCMPEQBirm,
984                                           MMX_PCMPEQDirm,
985                                           MMX_PCMPEQWirm,
986                                           MMX_PCMPGTBirm,
987                                           MMX_PCMPGTDirm,
988                                           MMX_PCMPGTWirm,
989                                           MMX_PMAXSWirm,
990                                           MMX_PMAXUBirm,
991                                           MMX_PMINSWirm,
992                                           MMX_PMINUBirm,
993                                           MMX_PSUBSBirm,
994                                           MMX_PSUBSWirm,
995                                           MMX_PSUBUSBirm,
996                                           MMX_PSUBUSWirm)>;
998 def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> {
999   let Latency = 6;
1000   let NumMicroOps = 2;
1001   let ResourceCycles = [1,1];
1003 def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr",
1004                                              "(V?)CVT(T?)SD2SI(64)?rr")>;
1006 def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
1007   let Latency = 6;
1008   let NumMicroOps = 2;
1009   let ResourceCycles = [1,1];
1011 def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64)>;
1012 def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
1014 def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
1015   let Latency = 6;
1016   let NumMicroOps = 2;
1017   let ResourceCycles = [1,1];
1019 def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1020                                              "MOVBE(16|32|64)rm")>;
1022 def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1023   let Latency = 6;
1024   let NumMicroOps = 2;
1025   let ResourceCycles = [1,1];
1027 def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
1028 def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
1030 def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1031   let Latency = 6;
1032   let NumMicroOps = 3;
1033   let ResourceCycles = [2,1];
1035 def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
1037 def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
1038   let Latency = 6;
1039   let NumMicroOps = 4;
1040   let ResourceCycles = [1,1,1,1];
1042 def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
1044 def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1045   let Latency = 6;
1046   let NumMicroOps = 4;
1047   let ResourceCycles = [1,1,1,1];
1049 def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",
1050                                              "SHL(8|16|32|64)m(1|i)",
1051                                              "SHR(8|16|32|64)m(1|i)")>;
1053 def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1054   let Latency = 6;
1055   let NumMicroOps = 4;
1056   let ResourceCycles = [1,1,1,1];
1058 def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
1059                                              "PUSH(16|32|64)rmm")>;
1061 def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1062   let Latency = 6;
1063   let NumMicroOps = 6;
1064   let ResourceCycles = [1,5];
1066 def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
1068 def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
1069   let Latency = 7;
1070   let NumMicroOps = 1;
1071   let ResourceCycles = [1];
1073 def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
1074 def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
1075                                           VBROADCASTI128,
1076                                           VBROADCASTSDYrm,
1077                                           VBROADCASTSSYrm,
1078                                           VMOVDDUPYrm,
1079                                           VMOVSHDUPYrm,
1080                                           VMOVSLDUPYrm,
1081                                           VPBROADCASTDYrm,
1082                                           VPBROADCASTQYrm)>;
1084 def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1085   let Latency = 7;
1086   let NumMicroOps = 2;
1087   let ResourceCycles = [1,1];
1089 def: InstRW<[SKLWriteResGroup86], (instrs VCVTDQ2PDYrr)>;
1091 def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1092   let Latency = 6;
1093   let NumMicroOps = 2;
1094   let ResourceCycles = [1,1];
1096 def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
1097                                              "(V?)PMOV(SX|ZX)BQrm",
1098                                              "(V?)PMOV(SX|ZX)BWrm",
1099                                              "(V?)PMOV(SX|ZX)DQrm",
1100                                              "(V?)PMOV(SX|ZX)WDrm",
1101                                              "(V?)PMOV(SX|ZX)WQrm")>;
1103 def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1104   let Latency = 7;
1105   let NumMicroOps = 2;
1106   let ResourceCycles = [1,1];
1108 def: InstRW<[SKLWriteResGroup89], (instrs VCVTPD2PSYrr,
1109                                           VCVTPS2PDYrr,
1110                                           VCVTPD2DQYrr,
1111                                           VCVTTPD2DQYrr)>;
1113 def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1114   let Latency = 7;
1115   let NumMicroOps = 2;
1116   let ResourceCycles = [1,1];
1118 def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm,
1119                                           VINSERTI128rm,
1120                                           VPBLENDDrmi)>;
1121 def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd],
1122                                   (instregex "(V?)PADD(B|D|Q|W)rm",
1123                                              "(V?)PSUB(B|D|Q|W)rm")>;
1125 def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1126   let Latency = 7;
1127   let NumMicroOps = 3;
1128   let ResourceCycles = [2,1];
1130 def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWirm,
1131                                           MMX_PACKSSWBirm,
1132                                           MMX_PACKUSWBirm)>;
1134 def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1135   let Latency = 7;
1136   let NumMicroOps = 3;
1137   let ResourceCycles = [1,2];
1139 def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
1140                                           SCASB, SCASL, SCASQ, SCASW)>;
1142 def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
1143   let Latency = 7;
1144   let NumMicroOps = 3;
1145   let ResourceCycles = [1,1,1];
1147 def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>;
1149 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
1150   let Latency = 7;
1151   let NumMicroOps = 3;
1152   let ResourceCycles = [1,1,1];
1154 def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
1156 def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
1157   let Latency = 7;
1158   let NumMicroOps = 3;
1159   let ResourceCycles = [1,1,1];
1161 def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>;
1163 def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1164   let Latency = 7;
1165   let NumMicroOps = 5;
1166   let ResourceCycles = [1,1,1,2];
1168 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
1169                                               "ROR(8|16|32|64)m(1|i)")>;
1171 def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> {
1172   let Latency = 2;
1173   let NumMicroOps = 2;
1174   let ResourceCycles = [2];
1176 def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1177                                              ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1179 def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1180   let Latency = 7;
1181   let NumMicroOps = 5;
1182   let ResourceCycles = [1,1,1,2];
1184 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
1186 def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1187   let Latency = 7;
1188   let NumMicroOps = 5;
1189   let ResourceCycles = [1,1,1,1,1];
1191 def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;
1192 def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64)>;
1194 def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
1195   let Latency = 7;
1196   let NumMicroOps = 7;
1197   let ResourceCycles = [1,3,1,2];
1199 def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
1201 def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
1202   let Latency = 8;
1203   let NumMicroOps = 2;
1204   let ResourceCycles = [1,1];
1206 def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
1207                                               "PEXT(32|64)rm")>;
1209 def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1210   let Latency = 8;
1211   let NumMicroOps = 2;
1212   let ResourceCycles = [1,1];
1214 def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>;
1215 def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm,
1216                                            VPBROADCASTWYrm,
1217                                            VPMOVSXBDYrm,
1218                                            VPMOVSXBQYrm,
1219                                            VPMOVSXWQYrm)>;
1221 def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1222   let Latency = 8;
1223   let NumMicroOps = 2;
1224   let ResourceCycles = [1,1];
1226 def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>;
1227 def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd],
1228                                    (instregex "VPADD(B|D|Q|W)Yrm",
1229                                               "VPSUB(B|D|Q|W)Yrm")>;
1231 def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1232   let Latency = 8;
1233   let NumMicroOps = 4;
1234   let ResourceCycles = [1,2,1];
1236 def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1238 def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1239   let Latency = 8;
1240   let NumMicroOps = 5;
1241   let ResourceCycles = [1,1,1,2];
1243 def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",
1244                                               "RCR(8|16|32|64)m(1|i)")>;
1246 def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1247   let Latency = 8;
1248   let NumMicroOps = 6;
1249   let ResourceCycles = [1,1,1,3];
1251 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
1252                                               "ROR(8|16|32|64)mCL",
1253                                               "SAR(8|16|32|64)mCL",
1254                                               "SHL(8|16|32|64)mCL",
1255                                               "SHR(8|16|32|64)mCL")>;
1257 def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1258   let Latency = 8;
1259   let NumMicroOps = 6;
1260   let ResourceCycles = [1,1,1,2,1];
1262 def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
1264 def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1265   let Latency = 9;
1266   let NumMicroOps = 2;
1267   let ResourceCycles = [1,1];
1269 def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSirm)>;
1271 def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1272   let Latency = 9;
1273   let NumMicroOps = 2;
1274   let ResourceCycles = [1,1];
1276 def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,
1277                                            VPCMPGTQrm,
1278                                            VPMOVSXBWYrm,
1279                                            VPMOVSXDQYrm,
1280                                            VPMOVSXWDYrm,
1281                                            VPMOVZXWDYrm)>;
1283 def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
1284   let Latency = 9;
1285   let NumMicroOps = 2;
1286   let ResourceCycles = [1,1];
1288 def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm",
1289                                               "(V?)CVTPS2PDrm")>;
1291 def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1292   let Latency = 9;
1293   let NumMicroOps = 4;
1294   let ResourceCycles = [2,1,1];
1296 def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
1297                                               "(V?)PHSUBSWrm")>;
1299 def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1300   let Latency = 9;
1301   let NumMicroOps = 5;
1302   let ResourceCycles = [1,2,1,1];
1304 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
1305                                               "LSL(16|32|64)rm")>;
1307 def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1308   let Latency = 10;
1309   let NumMicroOps = 2;
1310   let ResourceCycles = [1,1];
1312 def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1313                                               "ILD_F(16|32|64)m")>;
1314 def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>;
1316 def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1317   let Latency = 10;
1318   let NumMicroOps = 2;
1319   let ResourceCycles = [1,1];
1321 def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm",
1322                                               "(V?)CVTPS2DQrm",
1323                                               "(V?)CVTSS2SDrm",
1324                                               "(V?)CVTTPS2DQrm")>;
1326 def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1327   let Latency = 10;
1328   let NumMicroOps = 3;
1329   let ResourceCycles = [1,1,1];
1331 def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDirm)>;
1333 def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1334   let Latency = 10;
1335   let NumMicroOps = 3;
1336   let ResourceCycles = [1,1,1];
1338 def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>;
1340 def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1341   let Latency = 10;
1342   let NumMicroOps = 4;
1343   let ResourceCycles = [2,1,1];
1345 def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm,
1346                                            VPHSUBSWYrm)>;
1348 def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1349   let Latency = 10;
1350   let NumMicroOps = 8;
1351   let ResourceCycles = [1,1,1,1,1,3];
1353 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
1355 def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1356   let Latency = 11;
1357   let NumMicroOps = 1;
1358   let ResourceCycles = [1,3];
1360 def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair
1362 def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1363   let Latency = 11;
1364   let NumMicroOps = 2;
1365   let ResourceCycles = [1,1];
1367 def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
1369 def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1370   let Latency = 11;
1371   let NumMicroOps = 2;
1372   let ResourceCycles = [1,1];
1374 def: InstRW<[SKLWriteResGroup147], (instrs VCVTDQ2PSYrm,
1375                                            VCVTPS2PDYrm,
1376                                            VCVTPS2DQYrm,
1377                                            VCVTTPS2DQYrm)>;
1379 def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1380   let Latency = 11;
1381   let NumMicroOps = 3;
1382   let ResourceCycles = [2,1];
1384 def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
1386 def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1387   let Latency = 11;
1388   let NumMicroOps = 3;
1389   let ResourceCycles = [1,1,1];
1391 def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
1393 def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
1394   let Latency = 11;
1395   let NumMicroOps = 3;
1396   let ResourceCycles = [1,1,1];
1398 def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm",
1399                                               "(V?)CVT(T?)SD2SI(64)?rm",
1400                                               "VCVTTSS2SI64rm",
1401                                               "(V?)CVT(T?)SS2SIrm")>;
1403 def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1404   let Latency = 11;
1405   let NumMicroOps = 3;
1406   let ResourceCycles = [1,1,1];
1408 def: InstRW<[SKLWriteResGroup152], (instrs CVTPD2PSrm,
1409                                            CVTPD2DQrm,
1410                                            CVTTPD2DQrm,
1411                                            MMX_CVTPD2PIirm,
1412                                            MMX_CVTTPD2PIirm)>;
1414 def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1415   let Latency = 11;
1416   let NumMicroOps = 7;
1417   let ResourceCycles = [2,3,2];
1419 def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
1420                                               "RCR(16|32|64)rCL")>;
1422 def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1423   let Latency = 11;
1424   let NumMicroOps = 9;
1425   let ResourceCycles = [1,5,1,2];
1427 def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>;
1429 def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1430   let Latency = 11;
1431   let NumMicroOps = 11;
1432   let ResourceCycles = [2,9];
1434 def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
1436 def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
1437   let Latency = 12;
1438   let NumMicroOps = 4;
1439   let ResourceCycles = [1,1,1,1];
1441 def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
1443 def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1444   let Latency = 13;
1445   let NumMicroOps = 3;
1446   let ResourceCycles = [2,1];
1448 def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1450 def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1451   let Latency = 13;
1452   let NumMicroOps = 3;
1453   let ResourceCycles = [1,1,1];
1455 def: InstRW<[SKLWriteResGroup163], (instrs VCVTDQ2PDYrm)>;
1457 def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1458   let Latency = 14;
1459   let NumMicroOps = 1;
1460   let ResourceCycles = [1,3];
1462 def : SchedAlias<WriteFDiv64,  SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1463 def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1465 def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1466   let Latency = 14;
1467   let NumMicroOps = 1;
1468   let ResourceCycles = [1,5];
1470 def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair
1472 def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1473   let Latency = 14;
1474   let NumMicroOps = 3;
1475   let ResourceCycles = [1,1,1];
1477 def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
1479 def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1480   let Latency = 14;
1481   let NumMicroOps = 10;
1482   let ResourceCycles = [2,4,1,3];
1484 def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>;
1486 def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
1487   let Latency = 15;
1488   let NumMicroOps = 1;
1489   let ResourceCycles = [1];
1491 def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1493 def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1494   let Latency = 15;
1495   let NumMicroOps = 10;
1496   let ResourceCycles = [1,1,1,5,1,1];
1498 def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
1500 def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1501   let Latency = 16;
1502   let NumMicroOps = 14;
1503   let ResourceCycles = [1,1,1,4,2,5];
1505 def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
1507 def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
1508   let Latency = 16;
1509   let NumMicroOps = 16;
1510   let ResourceCycles = [16];
1512 def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
1514 def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1515   let Latency = 17;
1516   let NumMicroOps = 2;
1517   let ResourceCycles = [1,1,5];
1519 def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair
1521 def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1522   let Latency = 17;
1523   let NumMicroOps = 15;
1524   let ResourceCycles = [2,1,2,4,2,4];
1526 def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
1528 def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1529   let Latency = 18;
1530   let NumMicroOps = 8;
1531   let ResourceCycles = [1,1,1,5];
1533 def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
1535 def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1536   let Latency = 18;
1537   let NumMicroOps = 11;
1538   let ResourceCycles = [2,1,1,4,1,2];
1540 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
1542 def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1543   let Latency = 19;
1544   let NumMicroOps = 2;
1545   let ResourceCycles = [1,1,4];
1547 def : SchedAlias<WriteFDiv64Ld,  SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair
1549 def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
1550   let Latency = 20;
1551   let NumMicroOps = 1;
1552   let ResourceCycles = [1];
1554 def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1556 def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1557   let Latency = 20;
1558   let NumMicroOps = 2;
1559   let ResourceCycles = [1,1,4];
1561 def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair
1563 def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1564   let Latency = 20;
1565   let NumMicroOps = 8;
1566   let ResourceCycles = [1,1,1,1,1,1,2];
1568 def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
1570 def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
1571   let Latency = 20;
1572   let NumMicroOps = 10;
1573   let ResourceCycles = [1,2,7];
1575 def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
1577 def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1578   let Latency = 21;
1579   let NumMicroOps = 2;
1580   let ResourceCycles = [1,1,8];
1582 def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair
1584 def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1585   let Latency = 22;
1586   let NumMicroOps = 2;
1587   let ResourceCycles = [1,1];
1589 def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
1591 def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1592   let Latency = 22;
1593   let NumMicroOps = 5;
1594   let ResourceCycles = [1,2,1,1];
1596 def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm,
1597                                              VGATHERDPDrm,
1598                                              VGATHERQPDrm,
1599                                              VGATHERQPSrm,
1600                                              VPGATHERDDrm,
1601                                              VPGATHERDQrm,
1602                                              VPGATHERQDrm,
1603                                              VPGATHERQQrm)>;
1605 def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1606   let Latency = 25;
1607   let NumMicroOps = 5;
1608   let ResourceCycles = [1,2,1,1];
1610 def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm,
1611                                              VGATHERQPDYrm,
1612                                              VGATHERQPSYrm,
1613                                              VPGATHERDDYrm,
1614                                              VPGATHERDQYrm,
1615                                              VPGATHERQDYrm,
1616                                              VPGATHERQQYrm,
1617                                              VGATHERDPDYrm)>;
1619 def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1620   let Latency = 23;
1621   let NumMicroOps = 19;
1622   let ResourceCycles = [2,1,4,1,1,4,6];
1624 def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
1626 def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1627   let Latency = 25;
1628   let NumMicroOps = 3;
1629   let ResourceCycles = [1,1,1];
1631 def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
1633 def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1634   let Latency = 27;
1635   let NumMicroOps = 2;
1636   let ResourceCycles = [1,1];
1638 def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
1640 def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1641   let Latency = 30;
1642   let NumMicroOps = 3;
1643   let ResourceCycles = [1,1,1];
1645 def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
1647 def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
1648   let Latency = 35;
1649   let NumMicroOps = 23;
1650   let ResourceCycles = [1,5,3,4,10];
1652 def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
1653                                               "IN(8|16|32)rr")>;
1655 def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1656   let Latency = 35;
1657   let NumMicroOps = 23;
1658   let ResourceCycles = [1,5,2,1,4,10];
1660 def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
1661                                               "OUT(8|16|32)rr")>;
1663 def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1664   let Latency = 37;
1665   let NumMicroOps = 31;
1666   let ResourceCycles = [1,8,1,21];
1668 def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
1670 def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
1671   let Latency = 40;
1672   let NumMicroOps = 18;
1673   let ResourceCycles = [1,1,2,3,1,1,1,8];
1675 def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
1677 def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1678   let Latency = 41;
1679   let NumMicroOps = 39;
1680   let ResourceCycles = [1,10,1,1,26];
1682 def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
1684 def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1685   let Latency = 42;
1686   let NumMicroOps = 22;
1687   let ResourceCycles = [2,20];
1689 def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
1691 def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1692   let Latency = 42;
1693   let NumMicroOps = 40;
1694   let ResourceCycles = [1,11,1,1,26];
1696 def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
1697 def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
1699 def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1700   let Latency = 46;
1701   let NumMicroOps = 44;
1702   let ResourceCycles = [1,11,1,1,30];
1704 def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
1706 def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
1707   let Latency = 62;
1708   let NumMicroOps = 64;
1709   let ResourceCycles = [2,8,5,10,39];
1711 def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
1713 def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1714   let Latency = 63;
1715   let NumMicroOps = 88;
1716   let ResourceCycles = [4,4,31,1,2,1,45];
1718 def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
1720 def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1721   let Latency = 63;
1722   let NumMicroOps = 90;
1723   let ResourceCycles = [4,2,33,1,2,1,47];
1725 def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
1727 def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
1728   let Latency = 75;
1729   let NumMicroOps = 15;
1730   let ResourceCycles = [6,3,6];
1732 def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
1734 def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
1735   let Latency = 106;
1736   let NumMicroOps = 100;
1737   let ResourceCycles = [9,1,11,16,1,11,21,30];
1739 def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
1741 def: InstRW<[WriteZero], (instrs CLC)>;
1744 // Intruction variants handled by the renamer. These might not need execution
1745 // ports in certain conditions.
1746 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1747 // section "Skylake Pipeline" > "Register allocation and renaming".
1748 // These can be investigated with llvm-exegesis, e.g.
1749 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1750 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1752 def SKLWriteZeroLatency : SchedWriteRes<[]> {
1753   let Latency = 0;
1756 def SKLWriteZeroIdiom : SchedWriteVariant<[
1757     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1758     SchedVar<NoSchedPred,                          [WriteALU]>
1760 def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1761                                           XOR32rr, XOR64rr)>;
1763 def SKLWriteFZeroIdiom : SchedWriteVariant<[
1764     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1765     SchedVar<NoSchedPred,                          [WriteFLogic]>
1767 def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1768                                            VXORPDrr)>;
1770 def SKLWriteFZeroIdiomY : SchedWriteVariant<[
1771     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1772     SchedVar<NoSchedPred,                          [WriteFLogicY]>
1774 def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1776 def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[
1777     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1778     SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1780 def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1782 def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[
1783     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1784     SchedVar<NoSchedPred,                          [WriteVecLogicY]>
1786 def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1788 def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[
1789     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1790     SchedVar<NoSchedPred,                          [WriteVecALUX]>
1792 def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,
1793                                                PCMPGTDrr, VPCMPGTDrr,
1794                                                PCMPGTWrr, VPCMPGTWrr)>;
1796 def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[
1797     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1798     SchedVar<NoSchedPred,                          [WriteVecALUY]>
1800 def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
1801                                                VPCMPGTDYrr,
1802                                                VPCMPGTWYrr)>;
1804 def SKLWritePSUB : SchedWriteRes<[SKLPort015]> {
1805   let Latency = 1;
1806   let NumMicroOps = 1;
1807   let ResourceCycles = [1];
1810 def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[
1811     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1812     SchedVar<NoSchedPred,                          [SKLWritePSUB]>
1814 def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr,
1815                                                PSUBDrr, VPSUBDrr,
1816                                                PSUBQrr, VPSUBQrr,
1817                                                PSUBWrr, VPSUBWrr,
1818                                                VPSUBBYrr,
1819                                                VPSUBDYrr,
1820                                                VPSUBQYrr,
1821                                                VPSUBWYrr)>;
1823 def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> {
1824   let Latency = 3;
1825   let NumMicroOps = 1;
1826   let ResourceCycles = [1];
1829 def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1830     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1831     SchedVar<NoSchedPred,                          [SKLWritePCMPGTQ]>
1833 def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1834                                                   VPCMPGTQYrr)>;
1837 // CMOVs that use both Z and C flag require an extra uop.
1838 def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> {
1839   let Latency = 2;
1840   let ResourceCycles = [2];
1841   let NumMicroOps = 2;
1844 def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> {
1845   let Latency = 7;
1846   let ResourceCycles = [1,2];
1847   let NumMicroOps = 3;
1850 def SKLCMOVA_CMOVBErr :  SchedWriteVariant<[
1851   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>,
1852   SchedVar<NoSchedPred,                             [WriteCMOV]>
1855 def SKLCMOVA_CMOVBErm :  SchedWriteVariant<[
1856   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>,
1857   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1860 def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1861 def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1863 // SETCCs that use both Z and C flag require an extra uop.
1864 def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> {
1865   let Latency = 2;
1866   let ResourceCycles = [2];
1867   let NumMicroOps = 2;
1870 def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
1871   let Latency = 3;
1872   let ResourceCycles = [1,1,2];
1873   let NumMicroOps = 4;
1876 def SKLSETA_SETBErr :  SchedWriteVariant<[
1877   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>,
1878   SchedVar<NoSchedPred,                         [WriteSETCC]>
1881 def SKLSETA_SETBErm :  SchedWriteVariant<[
1882   SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>,
1883   SchedVar<NoSchedPred,                         [WriteSETCCStore]>
1886 def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>;
1887 def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>;
1889 } // SchedModel