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1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the machine model for Skylake Server to support
10 // instruction scheduling and other instruction cost heuristics.
11 //
12 //===----------------------------------------------------------------------===//
14 def SkylakeServerModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and SKylake can
16 // decode 6 instructions per cycle.
17 let IssueWidth = 6;
18 let MicroOpBufferSize = 224; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 14;
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
25 // This flag is set to allow the scheduler to assign a default model to
26 // unrecognized opcodes.
27 let CompleteModel = 0;
28 }
30 let SchedModel = SkylakeServerModel in {
32 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
34 // Ports 0, 1, 5, and 6 handle all computation.
35 // Port 4 gets the data half of stores. Store data can be available later than
36 // the store address, but since we don't model the latency of stores, we can
37 // ignore that.
38 // Ports 2 and 3 are identical. They handle loads and the address half of
39 // stores. Port 7 can handle address calculations.
40 def SKXPort0 : ProcResource<1>;
41 def SKXPort1 : ProcResource<1>;
42 def SKXPort2 : ProcResource<1>;
43 def SKXPort3 : ProcResource<1>;
44 def SKXPort4 : ProcResource<1>;
45 def SKXPort5 : ProcResource<1>;
46 def SKXPort6 : ProcResource<1>;
47 def SKXPort7 : ProcResource<1>;
49 // Many micro-ops are capable of issuing on multiple ports.
50 def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>;
51 def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>;
52 def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>;
53 def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>;
54 def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>;
55 def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>;
56 def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>;
57 def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>;
58 def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>;
59 def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
60 def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
61 def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
63 def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
64 // FP division and sqrt on port 0.
65 def SKXFPDivider : ProcResource<1>;
67 // 60 Entry Unified Scheduler
68 def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
69 SKXPort5, SKXPort6, SKXPort7]> {
70 let BufferSize=60;
71 }
73 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
74 // cycles after the memory operand.
75 def : ReadAdvance<ReadAfterLd, 5>;
77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
78 // until 5/6/7 cycles after the memory operand.
79 def : ReadAdvance<ReadAfterVecLd, 5>;
80 def : ReadAdvance<ReadAfterVecXLd, 6>;
81 def : ReadAdvance<ReadAfterVecYLd, 7>;
83 def : ReadAdvance<ReadInt2Fpu, 0>;
85 // Many SchedWrites are defined in pairs with and without a folded load.
86 // Instructions with folded loads are usually micro-fused, so they only appear
87 // as two micro-ops when queued in the reservation station.
88 // This multiclass defines the resource usage for variants with and without
89 // folded loads.
90 multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
91 list<ProcResourceKind> ExePorts,
92 int Lat, list<int> Res = [1], int UOps = 1,
93 int LoadLat = 5> {
94 // Register variant is using a single cycle on ExePort.
95 def : WriteRes<SchedRW, ExePorts> {
96 let Latency = Lat;
97 let ResourceCycles = Res;
98 let NumMicroOps = UOps;
99 }
101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
102 // the latency (default = 5).
103 def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
104 let Latency = !add(Lat, LoadLat);
105 let ResourceCycles = !listconcat([1], Res);
106 let NumMicroOps = !add(UOps, 1);
107 }
108 }
110 // A folded store needs a cycle on port 4 for the store data, and an extra port
111 // 2/3/7 cycle to recompute the address.
112 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
114 // Arithmetic.
115 defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op.
116 defm : SKXWriteResPair<WriteADC, [SKXPort06], 1>; // Integer ALU + flags op.
118 // Integer multiplication.
119 defm : SKXWriteResPair<WriteIMul8, [SKXPort1], 3>;
120 defm : SKXWriteResPair<WriteIMul16, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>;
121 defm : X86WriteRes<WriteIMul16Imm, [SKXPort1,SKXPort0156], 4, [1,1], 2>;
122 defm : X86WriteRes<WriteIMul16ImmLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
123 defm : X86WriteRes<WriteIMul16Reg, [SKXPort1], 3, [1], 1>;
124 defm : X86WriteRes<WriteIMul16RegLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
125 defm : SKXWriteResPair<WriteIMul32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
126 defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1], 3>;
127 defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1], 3>;
128 defm : SKXWriteResPair<WriteIMul64, [SKXPort1,SKXPort5], 4, [1,1], 2>;
129 defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1], 3>;
130 defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1], 3>;
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
133 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
134 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
135 defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;
136 defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>;
137 defm : X86WriteRes<WriteXCHG, [SKXPort0156], 2, [3], 3>;
139 // TODO: Why isn't the SKXDivider used?
140 defm : SKXWriteResPair<WriteDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
141 defm : X86WriteRes<WriteDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
142 defm : X86WriteRes<WriteDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
143 defm : X86WriteRes<WriteDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
144 defm : X86WriteRes<WriteDiv16Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
145 defm : X86WriteRes<WriteDiv32Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
146 defm : X86WriteRes<WriteDiv64Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
148 defm : X86WriteRes<WriteIDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1>;
149 defm : X86WriteRes<WriteIDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
150 defm : X86WriteRes<WriteIDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
151 defm : X86WriteRes<WriteIDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
152 defm : X86WriteRes<WriteIDiv8Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
153 defm : X86WriteRes<WriteIDiv16Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
154 defm : X86WriteRes<WriteIDiv32Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
155 defm : X86WriteRes<WriteIDiv64Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
157 defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
159 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
161 defm : SKXWriteResPair<WriteCMOV, [SKXPort06], 1, [1], 1>; // Conditional move.
162 defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move.
163 def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
164 def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
165 let Latency = 2;
166 let NumMicroOps = 3;
167 }
168 defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>;
169 defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>;
170 defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>;
171 defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>;
172 defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>;
173 defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 5, [1,1], 3>;
174 defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>;
176 // Integer shifts and rotates.
177 defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;
178 defm : SKXWriteResPair<WriteShiftCL, [SKXPort06], 3, [3], 3>;
179 defm : SKXWriteResPair<WriteRotate, [SKXPort06], 1, [1], 1>;
180 defm : SKXWriteResPair<WriteRotateCL, [SKXPort06], 3, [3], 3>;
182 // SHLD/SHRD.
183 defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;
184 defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>;
185 defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>;
186 defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>;
188 // Bit counts.
189 defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
190 defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
191 defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>;
192 defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>;
193 defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>;
195 // BMI1 BEXTR/BLS, BMI2 BZHI
196 defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;
197 defm : SKXWriteResPair<WriteBLS, [SKXPort15], 1>;
198 defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>;
200 // Loads, stores, and moves, not folded with other operations.
201 defm : X86WriteRes<WriteLoad, [SKXPort23], 5, [1], 1>;
202 defm : X86WriteRes<WriteStore, [SKXPort237, SKXPort4], 1, [1,1], 1>;
203 defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;
204 defm : X86WriteRes<WriteMove, [SKXPort0156], 1, [1], 1>;
206 // Idioms that clear a register, like xorps %xmm0, %xmm0.
207 // These can often bypass execution ports completely.
208 def : WriteRes<WriteZero, []>;
210 // Branches don't produce values, so they have no latency, but they still
211 // consume resources. Indirect branches can fold loads.
212 defm : SKXWriteResPair<WriteJump, [SKXPort06], 1>;
214 // Floating point. This covers both scalar and vector operations.
215 defm : X86WriteRes<WriteFLD0, [SKXPort05], 1, [1], 1>;
216 defm : X86WriteRes<WriteFLD1, [SKXPort05], 1, [2], 2>;
217 defm : X86WriteRes<WriteFLDC, [SKXPort05], 1, [2], 2>;
218 defm : X86WriteRes<WriteFLoad, [SKXPort23], 5, [1], 1>;
219 defm : X86WriteRes<WriteFLoadX, [SKXPort23], 6, [1], 1>;
220 defm : X86WriteRes<WriteFLoadY, [SKXPort23], 7, [1], 1>;
221 defm : X86WriteRes<WriteFMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
222 defm : X86WriteRes<WriteFMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
223 defm : X86WriteRes<WriteFStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;
224 defm : X86WriteRes<WriteFStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
225 defm : X86WriteRes<WriteFStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
226 defm : X86WriteRes<WriteFStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;
227 defm : X86WriteRes<WriteFStoreNTX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
228 defm : X86WriteRes<WriteFStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
229 defm : X86WriteRes<WriteFMaskedStore, [SKXPort237,SKXPort0], 2, [1,1], 2>;
230 defm : X86WriteRes<WriteFMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
231 defm : X86WriteRes<WriteFMove, [SKXPort015], 1, [1], 1>;
232 defm : X86WriteRes<WriteFMoveX, [SKXPort015], 1, [1], 1>;
233 defm : X86WriteRes<WriteFMoveY, [SKXPort015], 1, [1], 1>;
234 defm : X86WriteRes<WriteEMMS, [SKXPort05,SKXPort0156], 10, [9,1], 10>;
236 defm : SKXWriteResPair<WriteFAdd, [SKXPort01], 4, [1], 1, 5>; // Floating point add/sub.
237 defm : SKXWriteResPair<WriteFAddX, [SKXPort01], 4, [1], 1, 6>;
238 defm : SKXWriteResPair<WriteFAddY, [SKXPort01], 4, [1], 1, 7>;
239 defm : SKXWriteResPair<WriteFAddZ, [SKXPort05], 4, [1], 1, 7>;
240 defm : SKXWriteResPair<WriteFAdd64, [SKXPort01], 4, [1], 1, 5>; // Floating point double add/sub.
241 defm : SKXWriteResPair<WriteFAdd64X, [SKXPort01], 4, [1], 1, 6>;
242 defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort01], 4, [1], 1, 7>;
243 defm : SKXWriteResPair<WriteFAdd64Z, [SKXPort05], 4, [1], 1, 7>;
245 defm : SKXWriteResPair<WriteFCmp, [SKXPort01], 4, [1], 1, 5>; // Floating point compare.
246 defm : SKXWriteResPair<WriteFCmpX, [SKXPort01], 4, [1], 1, 6>;
247 defm : SKXWriteResPair<WriteFCmpY, [SKXPort01], 4, [1], 1, 7>;
248 defm : SKXWriteResPair<WriteFCmpZ, [SKXPort05], 4, [1], 1, 7>;
249 defm : SKXWriteResPair<WriteFCmp64, [SKXPort01], 4, [1], 1, 5>; // Floating point double compare.
250 defm : SKXWriteResPair<WriteFCmp64X, [SKXPort01], 4, [1], 1, 6>;
251 defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort01], 4, [1], 1, 7>;
252 defm : SKXWriteResPair<WriteFCmp64Z, [SKXPort05], 4, [1], 1, 7>;
254 defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags.
256 defm : SKXWriteResPair<WriteFMul, [SKXPort01], 4, [1], 1, 5>; // Floating point multiplication.
257 defm : SKXWriteResPair<WriteFMulX, [SKXPort01], 4, [1], 1, 6>;
258 defm : SKXWriteResPair<WriteFMulY, [SKXPort01], 4, [1], 1, 7>;
259 defm : SKXWriteResPair<WriteFMulZ, [SKXPort05], 4, [1], 1, 7>;
260 defm : SKXWriteResPair<WriteFMul64, [SKXPort01], 4, [1], 1, 5>; // Floating point double multiplication.
261 defm : SKXWriteResPair<WriteFMul64X, [SKXPort01], 4, [1], 1, 6>;
262 defm : SKXWriteResPair<WriteFMul64Y, [SKXPort01], 4, [1], 1, 7>;
263 defm : SKXWriteResPair<WriteFMul64Z, [SKXPort05], 4, [1], 1, 7>;
265 defm : SKXWriteResPair<WriteFDiv, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
266 //defm : SKXWriteResPair<WriteFDivX, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles.
267 defm : SKXWriteResPair<WriteFDivY, [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.
268 defm : SKXWriteResPair<WriteFDivZ, [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles.
269 //defm : SKXWriteResPair<WriteFDiv64, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
270 //defm : SKXWriteResPair<WriteFDiv64X, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles.
271 //defm : SKXWriteResPair<WriteFDiv64Y, [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles.
272 defm : SKXWriteResPair<WriteFDiv64Z, [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles.
274 defm : SKXWriteResPair<WriteFSqrt, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
275 defm : SKXWriteResPair<WriteFSqrtX, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>;
276 defm : SKXWriteResPair<WriteFSqrtY, [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;
277 defm : SKXWriteResPair<WriteFSqrtZ, [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;
278 defm : SKXWriteResPair<WriteFSqrt64, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
279 defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>;
280 defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;
281 defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;
282 defm : SKXWriteResPair<WriteFSqrt80, [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root.
284 defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
285 defm : SKXWriteResPair<WriteFRcpX, [SKXPort0], 4, [1], 1, 6>;
286 defm : SKXWriteResPair<WriteFRcpY, [SKXPort0], 4, [1], 1, 7>;
287 defm : SKXWriteResPair<WriteFRcpZ, [SKXPort0,SKXPort5], 4, [2,1], 3, 7>;
289 defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
290 defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0], 4, [1], 1, 6>;
291 defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0], 4, [1], 1, 7>;
292 defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5], 9, [2,1], 3, 7>;
294 defm : SKXWriteResPair<WriteFMA, [SKXPort01], 4, [1], 1, 5>; // Fused Multiply Add.
295 defm : SKXWriteResPair<WriteFMAX, [SKXPort01], 4, [1], 1, 6>;
296 defm : SKXWriteResPair<WriteFMAY, [SKXPort01], 4, [1], 1, 7>;
297 defm : SKXWriteResPair<WriteFMAZ, [SKXPort05], 4, [1], 1, 7>;
298 defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015], 9, [1,2], 3, 6>; // Floating point double dot product.
299 defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>;
300 defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
301 defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
302 defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs.
303 defm : SKXWriteResPair<WriteFRnd, [SKXPort01], 8, [2], 2, 6>; // Floating point rounding.
304 defm : SKXWriteResPair<WriteFRndY, [SKXPort01], 8, [2], 2, 7>;
305 defm : SKXWriteResPair<WriteFRndZ, [SKXPort05], 8, [2], 2, 7>;
306 defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
307 defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;
308 defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;
309 defm : SKXWriteResPair<WriteFTest, [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
310 defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;
311 defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;
312 defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
313 defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;
314 defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;
315 defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
316 defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
317 defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
318 defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends.
319 defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;
320 defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;
321 defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends.
322 defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;
323 defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;
325 // FMA Scheduling helper class.
326 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
328 // Vector integer operations.
329 defm : X86WriteRes<WriteVecLoad, [SKXPort23], 5, [1], 1>;
330 defm : X86WriteRes<WriteVecLoadX, [SKXPort23], 6, [1], 1>;
331 defm : X86WriteRes<WriteVecLoadY, [SKXPort23], 7, [1], 1>;
332 defm : X86WriteRes<WriteVecLoadNT, [SKXPort23], 6, [1], 1>;
333 defm : X86WriteRes<WriteVecLoadNTY, [SKXPort23], 7, [1], 1>;
334 defm : X86WriteRes<WriteVecMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
335 defm : X86WriteRes<WriteVecMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
336 defm : X86WriteRes<WriteVecStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;
337 defm : X86WriteRes<WriteVecStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
338 defm : X86WriteRes<WriteVecStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
339 defm : X86WriteRes<WriteVecStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;
340 defm : X86WriteRes<WriteVecStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
341 defm : X86WriteRes<WriteVecMaskedStore, [SKXPort237,SKXPort0], 2, [1,1], 2>;
342 defm : X86WriteRes<WriteVecMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
343 defm : X86WriteRes<WriteVecMove, [SKXPort05], 1, [1], 1>;
344 defm : X86WriteRes<WriteVecMoveX, [SKXPort015], 1, [1], 1>;
345 defm : X86WriteRes<WriteVecMoveY, [SKXPort015], 1, [1], 1>;
346 defm : X86WriteRes<WriteVecMoveToGpr, [SKXPort0], 2, [1], 1>;
347 defm : X86WriteRes<WriteVecMoveFromGpr, [SKXPort5], 1, [1], 1>;
349 defm : SKXWriteResPair<WriteVecALU, [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
350 defm : SKXWriteResPair<WriteVecALUX, [SKXPort01], 1, [1], 1, 6>;
351 defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>;
352 defm : SKXWriteResPair<WriteVecALUZ, [SKXPort0], 1, [1], 1, 7>;
353 defm : SKXWriteResPair<WriteVecLogic, [SKXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor.
354 defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>;
355 defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;
356 defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;
357 defm : SKXWriteResPair<WriteVecTest, [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
358 defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
359 defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
360 defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 4, [1], 1, 5>; // Vector integer multiply.
361 defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01], 4, [1], 1, 6>;
362 defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01], 4, [1], 1, 7>;
363 defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05], 4, [1], 1, 7>;
364 defm : SKXWriteResPair<WritePMULLD, [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD.
365 defm : SKXWriteResPair<WritePMULLDY, [SKXPort01], 10, [2], 2, 7>;
366 defm : SKXWriteResPair<WritePMULLDZ, [SKXPort05], 10, [2], 2, 7>;
367 defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.
368 defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>;
369 defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;
370 defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;
371 defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles.
372 defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>;
373 defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
374 defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
375 defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
376 defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;
377 defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;
378 defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
379 defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>;
380 defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05], 2, [1], 1, 6>;
381 defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
382 defm : SKXWriteResPair<WriteMPSADY, [SKXPort5], 4, [2], 2, 7>;
383 defm : SKXWriteResPair<WriteMPSADZ, [SKXPort5], 4, [2], 2, 7>;
384 defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW.
385 defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>;
386 defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;
387 defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>;
388 defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
390 // Vector integer shifts.
391 defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>;
392 defm : X86WriteRes<WriteVecShiftX, [SKXPort5,SKXPort01], 2, [1,1], 2>;
393 defm : X86WriteRes<WriteVecShiftY, [SKXPort5,SKXPort01], 4, [1,1], 2>;
394 defm : X86WriteRes<WriteVecShiftZ, [SKXPort5,SKXPort0], 4, [1,1], 2>;
395 defm : X86WriteRes<WriteVecShiftXLd, [SKXPort01,SKXPort23], 7, [1,1], 2>;
396 defm : X86WriteRes<WriteVecShiftYLd, [SKXPort01,SKXPort23], 8, [1,1], 2>;
397 defm : X86WriteRes<WriteVecShiftZLd, [SKXPort0,SKXPort23], 8, [1,1], 2>;
399 defm : SKXWriteResPair<WriteVecShiftImm, [SKXPort0], 1, [1], 1, 5>;
400 defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts.
401 defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;
402 defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;
403 defm : SKXWriteResPair<WriteVarVecShift, [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.
404 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
405 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
407 // Vector insert/extract operations.
408 def : WriteRes<WriteVecInsert, [SKXPort5]> {
409 let Latency = 2;
410 let NumMicroOps = 2;
411 let ResourceCycles = [2];
412 }
413 def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
414 let Latency = 6;
415 let NumMicroOps = 2;
416 }
417 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
419 def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {
420 let Latency = 3;
421 let NumMicroOps = 2;
422 }
423 def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> {
424 let Latency = 2;
425 let NumMicroOps = 3;
426 }
428 // Conversion between integer and float.
429 defm : SKXWriteResPair<WriteCvtSS2I, [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
430 defm : SKXWriteResPair<WriteCvtPS2I, [SKXPort01], 3>;
431 defm : SKXWriteResPair<WriteCvtPS2IY, [SKXPort01], 3>;
432 defm : SKXWriteResPair<WriteCvtPS2IZ, [SKXPort05], 3>;
433 defm : SKXWriteResPair<WriteCvtSD2I, [SKXPort01], 6, [2], 2>;
434 defm : SKXWriteResPair<WriteCvtPD2I, [SKXPort01], 3>;
435 defm : SKXWriteResPair<WriteCvtPD2IY, [SKXPort01], 3>;
436 defm : SKXWriteResPair<WriteCvtPD2IZ, [SKXPort05], 3>;
438 defm : SKXWriteResPair<WriteCvtI2SS, [SKXPort1], 4>;
439 defm : SKXWriteResPair<WriteCvtI2PS, [SKXPort01], 4>;
440 defm : SKXWriteResPair<WriteCvtI2PSY, [SKXPort01], 4>;
441 defm : SKXWriteResPair<WriteCvtI2PSZ, [SKXPort05], 4>; // Needs more work: DD vs DQ.
442 defm : SKXWriteResPair<WriteCvtI2SD, [SKXPort1], 4>;
443 defm : SKXWriteResPair<WriteCvtI2PD, [SKXPort01], 4>;
444 defm : SKXWriteResPair<WriteCvtI2PDY, [SKXPort01], 4>;
445 defm : SKXWriteResPair<WriteCvtI2PDZ, [SKXPort05], 4>;
447 defm : SKXWriteResPair<WriteCvtSS2SD, [SKXPort1], 3>;
448 defm : SKXWriteResPair<WriteCvtPS2PD, [SKXPort1], 3>;
449 defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
450 defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>;
451 defm : SKXWriteResPair<WriteCvtSD2SS, [SKXPort1], 3>;
452 defm : SKXWriteResPair<WriteCvtPD2PS, [SKXPort1], 3>;
453 defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
454 defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>;
456 defm : X86WriteRes<WriteCvtPH2PS, [SKXPort5,SKXPort01], 5, [1,1], 2>;
457 defm : X86WriteRes<WriteCvtPH2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
458 defm : X86WriteRes<WriteCvtPH2PSZ, [SKXPort5,SKXPort0], 7, [1,1], 2>;
459 defm : X86WriteRes<WriteCvtPH2PSLd, [SKXPort23,SKXPort01], 9, [1,1], 2>;
460 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>;
461 defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>;
463 defm : X86WriteRes<WriteCvtPS2PH, [SKXPort5,SKXPort01], 5, [1,1], 2>;
464 defm : X86WriteRes<WriteCvtPS2PHY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
465 defm : X86WriteRes<WriteCvtPS2PHZ, [SKXPort5,SKXPort05], 7, [1,1], 2>;
466 defm : X86WriteRes<WriteCvtPS2PHSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>;
467 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>;
468 defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;
470 // Strings instructions.
472 // Packed Compare Implicit Length Strings, Return Mask
473 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
474 let Latency = 10;
475 let NumMicroOps = 3;
476 let ResourceCycles = [3];
477 }
478 def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
479 let Latency = 16;
480 let NumMicroOps = 4;
481 let ResourceCycles = [3,1];
482 }
484 // Packed Compare Explicit Length Strings, Return Mask
485 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
486 let Latency = 19;
487 let NumMicroOps = 9;
488 let ResourceCycles = [4,3,1,1];
489 }
490 def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
491 let Latency = 25;
492 let NumMicroOps = 10;
493 let ResourceCycles = [4,3,1,1,1];
494 }
496 // Packed Compare Implicit Length Strings, Return Index
497 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
498 let Latency = 10;
499 let NumMicroOps = 3;
500 let ResourceCycles = [3];
501 }
502 def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
503 let Latency = 16;
504 let NumMicroOps = 4;
505 let ResourceCycles = [3,1];
506 }
508 // Packed Compare Explicit Length Strings, Return Index
509 def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
510 let Latency = 18;
511 let NumMicroOps = 8;
512 let ResourceCycles = [4,3,1];
513 }
514 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
515 let Latency = 24;
516 let NumMicroOps = 9;
517 let ResourceCycles = [4,3,1,1];
518 }
520 // MOVMSK Instructions.
521 def : WriteRes<WriteFMOVMSK, [SKXPort0]> { let Latency = 2; }
522 def : WriteRes<WriteVecMOVMSK, [SKXPort0]> { let Latency = 2; }
523 def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }
524 def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; }
526 // AES instructions.
527 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
528 let Latency = 4;
529 let NumMicroOps = 1;
530 let ResourceCycles = [1];
531 }
532 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
533 let Latency = 10;
534 let NumMicroOps = 2;
535 let ResourceCycles = [1,1];
536 }
538 def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
539 let Latency = 8;
540 let NumMicroOps = 2;
541 let ResourceCycles = [2];
542 }
543 def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
544 let Latency = 14;
545 let NumMicroOps = 3;
546 let ResourceCycles = [2,1];
547 }
549 def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
550 let Latency = 20;
551 let NumMicroOps = 11;
552 let ResourceCycles = [3,6,2];
553 }
554 def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
555 let Latency = 25;
556 let NumMicroOps = 11;
557 let ResourceCycles = [3,6,1,1];
558 }
560 // Carry-less multiplication instructions.
561 def : WriteRes<WriteCLMul, [SKXPort5]> {
562 let Latency = 6;
563 let NumMicroOps = 1;
564 let ResourceCycles = [1];
565 }
566 def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
567 let Latency = 12;
568 let NumMicroOps = 2;
569 let ResourceCycles = [1,1];
570 }
572 // Catch-all for expensive system instructions.
573 def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
575 // AVX2.
576 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
577 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
578 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles.
579 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles.
581 // Old microcoded instructions that nobody use.
582 def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
584 // Fence instructions.
585 def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>;
587 // Load/store MXCSR.
588 def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
589 def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
591 // Nop, not very useful expect it provides a model for nops!
592 def : WriteRes<WriteNop, []>;
594 ////////////////////////////////////////////////////////////////////////////////
595 // Horizontal add/sub instructions.
596 ////////////////////////////////////////////////////////////////////////////////
598 defm : SKXWriteResPair<WriteFHAdd, [SKXPort5,SKXPort015], 6, [2,1], 3, 6>;
599 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>;
600 defm : SKXWriteResPair<WritePHAdd, [SKXPort5,SKXPort05], 3, [2,1], 3, 5>;
601 defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;
602 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
604 // Remaining instrs.
606 def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
607 let Latency = 1;
608 let NumMicroOps = 1;
609 let ResourceCycles = [1];
610 }
611 def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
612 "KANDN(B|D|Q|W)rr",
613 "KMOV(B|D|Q|W)kk",
614 "KNOT(B|D|Q|W)rr",
615 "KOR(B|D|Q|W)rr",
616 "KXNOR(B|D|Q|W)rr",
617 "KXOR(B|D|Q|W)rr",
618 "MMX_PADDS(B|W)irr",
619 "MMX_PADDUS(B|W)irr",
620 "MMX_PAVG(B|W)irr",
621 "MMX_PCMPEQ(B|D|W)irr",
622 "MMX_PCMPGT(B|D|W)irr",
623 "MMX_P(MAX|MIN)SWirr",
624 "MMX_P(MAX|MIN)UBirr",
625 "MMX_PSUBS(B|W)irr",
626 "MMX_PSUBUS(B|W)irr",
627 "VPMOVB2M(Z|Z128|Z256)rr",
628 "VPMOVD2M(Z|Z128|Z256)rr",
629 "VPMOVQ2M(Z|Z128|Z256)rr",
630 "VPMOVW2M(Z|Z128|Z256)rr")>;
632 def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
633 let Latency = 1;
634 let NumMicroOps = 1;
635 let ResourceCycles = [1];
636 }
637 def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
638 "KMOV(B|D|Q|W)kr",
639 "UCOM_F(P?)r")>;
641 def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
642 let Latency = 1;
643 let NumMicroOps = 1;
644 let ResourceCycles = [1];
645 }
646 def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
648 def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
649 let Latency = 1;
650 let NumMicroOps = 1;
651 let ResourceCycles = [1];
652 }
653 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
655 def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
656 let Latency = 1;
657 let NumMicroOps = 1;
658 let ResourceCycles = [1];
659 }
660 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
662 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
663 let Latency = 1;
664 let NumMicroOps = 1;
665 let ResourceCycles = [1];
666 }
667 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
669 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
670 let Latency = 1;
671 let NumMicroOps = 1;
672 let ResourceCycles = [1];
673 }
674 def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
675 "VBLENDMPS(Z128|Z256)rr",
676 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
677 "(V?)PADD(B|D|Q|W)rr",
678 "VPBLENDD(Y?)rri",
679 "VPBLENDMB(Z128|Z256)rr",
680 "VPBLENDMD(Z128|Z256)rr",
681 "VPBLENDMQ(Z128|Z256)rr",
682 "VPBLENDMW(Z128|Z256)rr",
683 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk",
684 "VPTERNLOGD(Z|Z128|Z256)rri",
685 "VPTERNLOGQ(Z|Z128|Z256)rri")>;
687 def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
688 let Latency = 1;
689 let NumMicroOps = 1;
690 let ResourceCycles = [1];
691 }
692 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
693 CMC, STC,
694 SGDT64m,
695 SIDT64m,
696 SMSW16m,
697 STRm,
698 SYSCALL)>;
700 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
701 let Latency = 1;
702 let NumMicroOps = 2;
703 let ResourceCycles = [1,1];
704 }
705 def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
706 def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
707 "ST_FP(32|64|80)m")>;
709 def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
710 let Latency = 2;
711 let NumMicroOps = 2;
712 let ResourceCycles = [2];
713 }
714 def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
716 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
717 let Latency = 2;
718 let NumMicroOps = 2;
719 let ResourceCycles = [2];
720 }
721 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
722 MMX_MOVDQ2Qrr)>;
724 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
725 let Latency = 2;
726 let NumMicroOps = 2;
727 let ResourceCycles = [2];
728 }
729 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
730 WAIT,
731 XGETBV)>;
733 def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
734 let Latency = 2;
735 let NumMicroOps = 2;
736 let ResourceCycles = [1,1];
737 }
738 def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
740 def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
741 let Latency = 2;
742 let NumMicroOps = 2;
743 let ResourceCycles = [1,1];
744 }
745 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
747 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
748 let Latency = 2;
749 let NumMicroOps = 2;
750 let ResourceCycles = [1,1];
751 }
752 def: InstRW<[SKXWriteResGroup23], (instrs CWD,
753 JCXZ, JECXZ, JRCXZ,
754 ADC8i8, SBB8i8,
755 ADC16i16, SBB16i16,
756 ADC32i32, SBB32i32,
757 ADC64i32, SBB64i32)>;
759 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
760 let Latency = 2;
761 let NumMicroOps = 3;
762 let ResourceCycles = [1,1,1];
763 }
764 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
766 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
767 let Latency = 2;
768 let NumMicroOps = 3;
769 let ResourceCycles = [1,1,1];
770 }
771 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
773 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
774 let Latency = 2;
775 let NumMicroOps = 3;
776 let ResourceCycles = [1,1,1];
777 }
778 def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
779 STOSB, STOSL, STOSQ, STOSW)>;
780 def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
782 def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
783 let Latency = 2;
784 let NumMicroOps = 5;
785 let ResourceCycles = [2,2,1];
786 }
787 def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
789 def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
790 let Latency = 3;
791 let NumMicroOps = 1;
792 let ResourceCycles = [1];
793 }
794 def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
795 "KORTEST(B|D|Q|W)rr",
796 "KTEST(B|D|Q|W)rr")>;
798 def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
799 let Latency = 3;
800 let NumMicroOps = 1;
801 let ResourceCycles = [1];
802 }
803 def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
804 "PEXT(32|64)rr")>;
806 def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
807 let Latency = 3;
808 let NumMicroOps = 1;
809 let ResourceCycles = [1];
810 }
811 def: InstRW<[SKXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined.
812 def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
813 "KADD(B|D|Q|W)rr",
814 "KSHIFTL(B|D|Q|W)ri",
815 "KSHIFTR(B|D|Q|W)ri",
816 "KUNPCK(BW|DQ|WD)rr",
817 "VALIGND(Z|Z128|Z256)rri",
818 "VALIGNQ(Z|Z128|Z256)rri",
819 "VCMPPD(Z|Z128|Z256)rri",
820 "VCMPPS(Z|Z128|Z256)rri",
821 "VCMP(SD|SS)Zrr",
822 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined.
823 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
824 "VFPCLASS(SD|SS)Zrr",
825 "VPBROADCAST(B|W)rr",
826 "VPCMPB(Z|Z128|Z256)rri",
827 "VPCMPD(Z|Z128|Z256)rri",
828 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
829 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
830 "VPCMPQ(Z|Z128|Z256)rri",
831 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
832 "VPCMPW(Z|Z128|Z256)rri",
833 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr",
834 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
836 def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
837 let Latency = 3;
838 let NumMicroOps = 2;
839 let ResourceCycles = [1,1];
840 }
841 def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
843 def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
844 let Latency = 3;
845 let NumMicroOps = 3;
846 let ResourceCycles = [1,2];
847 }
848 def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
850 def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
851 let Latency = 3;
852 let NumMicroOps = 3;
853 let ResourceCycles = [2,1];
854 }
855 def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
857 def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
858 let Latency = 3;
859 let NumMicroOps = 3;
860 let ResourceCycles = [2,1];
861 }
862 def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWirr,
863 MMX_PACKSSWBirr,
864 MMX_PACKUSWBirr)>;
866 def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
867 let Latency = 3;
868 let NumMicroOps = 3;
869 let ResourceCycles = [1,2];
870 }
871 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
873 def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
874 let Latency = 3;
875 let NumMicroOps = 3;
876 let ResourceCycles = [1,2];
877 }
878 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
880 def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
881 let Latency = 3;
882 let NumMicroOps = 3;
883 let ResourceCycles = [1,2];
884 }
885 def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)",
886 "RCR(8|16|32|64)r(1|i)")>;
888 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
889 let Latency = 3;
890 let NumMicroOps = 3;
891 let ResourceCycles = [1,1,1];
892 }
893 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
895 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
896 let Latency = 3;
897 let NumMicroOps = 4;
898 let ResourceCycles = [1,1,1,1];
899 }
900 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
902 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
903 let Latency = 3;
904 let NumMicroOps = 4;
905 let ResourceCycles = [1,1,1,1];
906 }
907 def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
909 def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
910 let Latency = 4;
911 let NumMicroOps = 1;
912 let ResourceCycles = [1];
913 }
914 def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
916 def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
917 let Latency = 4;
918 let NumMicroOps = 1;
919 let ResourceCycles = [1];
920 }
921 def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr",
922 "(V?)CVTDQ2PSrr",
923 "VCVTPD2QQ(Z128|Z256)rr",
924 "VCVTPD2UQQ(Z128|Z256)rr",
925 "VCVTPS2DQ(Y|Z128|Z256)rr",
926 "(V?)CVTPS2DQrr",
927 "VCVTPS2UDQ(Z128|Z256)rr",
928 "VCVTQQ2PD(Z128|Z256)rr",
929 "VCVTTPD2QQ(Z128|Z256)rr",
930 "VCVTTPD2UQQ(Z128|Z256)rr",
931 "VCVTTPS2DQ(Z128|Z256)rr",
932 "(V?)CVTTPS2DQrr",
933 "VCVTTPS2UDQ(Z128|Z256)rr",
934 "VCVTUDQ2PS(Z128|Z256)rr",
935 "VCVTUQQ2PD(Z128|Z256)rr")>;
937 def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
938 let Latency = 4;
939 let NumMicroOps = 1;
940 let ResourceCycles = [1];
941 }
942 def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
943 VCVTPD2QQZrr,
944 VCVTPD2UQQZrr,
945 VCVTPS2DQZrr,
946 VCVTPS2UDQZrr,
947 VCVTQQ2PDZrr,
948 VCVTTPD2QQZrr,
949 VCVTTPD2UQQZrr,
950 VCVTTPS2DQZrr,
951 VCVTTPS2UDQZrr,
952 VCVTUDQ2PSZrr,
953 VCVTUQQ2PDZrr)>;
955 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
956 let Latency = 4;
957 let NumMicroOps = 2;
958 let ResourceCycles = [2];
959 }
960 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
961 "VEXPANDPS(Z|Z128|Z256)rr",
962 "VPEXPANDD(Z|Z128|Z256)rr",
963 "VPEXPANDQ(Z|Z128|Z256)rr",
964 "VPMOVDB(Z|Z128|Z256)rr",
965 "VPMOVDW(Z|Z128|Z256)rr",
966 "VPMOVQB(Z|Z128|Z256)rr",
967 "VPMOVQW(Z|Z128|Z256)rr",
968 "VPMOVSDB(Z|Z128|Z256)rr",
969 "VPMOVSDW(Z|Z128|Z256)rr",
970 "VPMOVSQB(Z|Z128|Z256)rr",
971 "VPMOVSQD(Z|Z128|Z256)rr",
972 "VPMOVSQW(Z|Z128|Z256)rr",
973 "VPMOVSWB(Z|Z128|Z256)rr",
974 "VPMOVUSDB(Z|Z128|Z256)rr",
975 "VPMOVUSDW(Z|Z128|Z256)rr",
976 "VPMOVUSQB(Z|Z128|Z256)rr",
977 "VPMOVUSQD(Z|Z128|Z256)rr",
978 "VPMOVUSWB(Z|Z128|Z256)rr",
979 "VPMOVWB(Z|Z128|Z256)rr")>;
981 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
982 let Latency = 4;
983 let NumMicroOps = 3;
984 let ResourceCycles = [1,1,1];
985 }
986 def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
987 "IST_F(16|32)m",
988 "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
990 def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
991 let Latency = 4;
992 let NumMicroOps = 4;
993 let ResourceCycles = [4];
994 }
995 def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
997 def SKXWriteResGroup56 : SchedWriteRes<[]> {
998 let Latency = 0;
999 let NumMicroOps = 4;
1000 let ResourceCycles = [];
1001 }
1002 def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
1004 def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
1005 let Latency = 4;
1006 let NumMicroOps = 4;
1007 let ResourceCycles = [1,1,2];
1008 }
1009 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1011 def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> {
1012 let Latency = 5;
1013 let NumMicroOps = 1;
1014 let ResourceCycles = [1];
1015 }
1016 def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
1017 "MOVZX(16|32|64)rm(8|16)",
1018 "(V?)MOVDDUPrm")>; // TODO: Should this be SKXWriteResGroup71?
1020 def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1021 let Latency = 5;
1022 let NumMicroOps = 2;
1023 let ResourceCycles = [1,1];
1024 }
1025 def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr",
1026 "MMX_CVT(T?)PS2PIirr",
1027 "VCVTDQ2PDZ128rr",
1028 "VCVTPD2DQZ128rr",
1029 "(V?)CVT(T?)PD2DQrr",
1030 "VCVTPD2PSZ128rr",
1031 "(V?)CVTPD2PSrr",
1032 "VCVTPD2UDQZ128rr",
1033 "VCVTPS2PDZ128rr",
1034 "(V?)CVTPS2PDrr",
1035 "VCVTPS2QQZ128rr",
1036 "VCVTPS2UQQZ128rr",
1037 "VCVTQQ2PSZ128rr",
1038 "(V?)CVTSD2SS(Z?)rr",
1039 "(V?)CVTSI(64)?2SDrr",
1040 "VCVTSI2SSZrr",
1041 "(V?)CVTSI2SSrr",
1042 "VCVTSI(64)?2SDZrr",
1043 "VCVTSS2SDZrr",
1044 "(V?)CVTSS2SDrr",
1045 "VCVTTPD2DQZ128rr",
1046 "VCVTTPD2UDQZ128rr",
1047 "VCVTTPS2QQZ128rr",
1048 "VCVTTPS2UQQZ128rr",
1049 "VCVTUDQ2PDZ128rr",
1050 "VCVTUQQ2PSZ128rr",
1051 "VCVTUSI2SSZrr",
1052 "VCVTUSI(64)?2SDZrr")>;
1054 def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1055 let Latency = 5;
1056 let NumMicroOps = 3;
1057 let ResourceCycles = [2,1];
1058 }
1059 def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
1061 def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
1062 let Latency = 5;
1063 let NumMicroOps = 3;
1064 let ResourceCycles = [1,1,1];
1065 }
1066 def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
1068 def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> {
1069 let Latency = 5;
1070 let NumMicroOps = 3;
1071 let ResourceCycles = [1,1,1];
1072 }
1073 def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
1074 "VCVTPS2PHZ256mr(b?)",
1075 "VCVTPS2PHZmr(b?)")>;
1077 def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1078 let Latency = 5;
1079 let NumMicroOps = 4;
1080 let ResourceCycles = [1,2,1];
1081 }
1082 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
1083 "VPMOVDW(Z|Z128|Z256)mr(b?)",
1084 "VPMOVQB(Z|Z128|Z256)mr(b?)",
1085 "VPMOVQW(Z|Z128|Z256)mr(b?)",
1086 "VPMOVSDB(Z|Z128|Z256)mr(b?)",
1087 "VPMOVSDW(Z|Z128|Z256)mr(b?)",
1088 "VPMOVSQB(Z|Z128|Z256)mr(b?)",
1089 "VPMOVSQD(Z|Z128|Z256)mr(b?)",
1090 "VPMOVSQW(Z|Z128|Z256)mr(b?)",
1091 "VPMOVSWB(Z|Z128|Z256)mr(b?)",
1092 "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
1093 "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
1094 "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
1095 "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
1096 "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
1097 "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
1098 "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
1100 def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1101 let Latency = 5;
1102 let NumMicroOps = 5;
1103 let ResourceCycles = [1,4];
1104 }
1105 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
1107 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
1108 let Latency = 5;
1109 let NumMicroOps = 6;
1110 let ResourceCycles = [1,1,4];
1111 }
1112 def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
1114 def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
1115 let Latency = 6;
1116 let NumMicroOps = 1;
1117 let ResourceCycles = [1];
1118 }
1119 def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm,
1120 VPBROADCASTDrm,
1121 VPBROADCASTQrm,
1122 VMOVSHDUPrm,
1123 VMOVSLDUPrm,
1124 MOVSHDUPrm,
1125 MOVSLDUPrm)>;
1127 def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
1128 let Latency = 6;
1129 let NumMicroOps = 2;
1130 let ResourceCycles = [2];
1131 }
1132 def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>;
1133 def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
1134 "VCOMPRESSPS(Z|Z128|Z256)rr",
1135 "VPCOMPRESSD(Z|Z128|Z256)rr",
1136 "VPCOMPRESSQ(Z|Z128|Z256)rr",
1137 "VPERMW(Z|Z128|Z256)rr")>;
1139 def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1140 let Latency = 6;
1141 let NumMicroOps = 2;
1142 let ResourceCycles = [1,1];
1143 }
1144 def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBirm,
1145 MMX_PADDSWirm,
1146 MMX_PADDUSBirm,
1147 MMX_PADDUSWirm,
1148 MMX_PAVGBirm,
1149 MMX_PAVGWirm,
1150 MMX_PCMPEQBirm,
1151 MMX_PCMPEQDirm,
1152 MMX_PCMPEQWirm,
1153 MMX_PCMPGTBirm,
1154 MMX_PCMPGTDirm,
1155 MMX_PCMPGTWirm,
1156 MMX_PMAXSWirm,
1157 MMX_PMAXUBirm,
1158 MMX_PMINSWirm,
1159 MMX_PMINUBirm,
1160 MMX_PSUBSBirm,
1161 MMX_PSUBSWirm,
1162 MMX_PSUBUSBirm,
1163 MMX_PSUBUSWirm)>;
1165 def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
1166 let Latency = 6;
1167 let NumMicroOps = 2;
1168 let ResourceCycles = [1,1];
1169 }
1170 def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64)>;
1171 def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
1173 def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
1174 let Latency = 6;
1175 let NumMicroOps = 2;
1176 let ResourceCycles = [1,1];
1177 }
1178 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
1179 "MOVBE(16|32|64)rm")>;
1181 def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1182 let Latency = 6;
1183 let NumMicroOps = 2;
1184 let ResourceCycles = [1,1];
1185 }
1186 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
1187 def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
1189 def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1190 let Latency = 6;
1191 let NumMicroOps = 2;
1192 let ResourceCycles = [1,1];
1193 }
1194 def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
1195 def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
1197 def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1198 let Latency = 6;
1199 let NumMicroOps = 3;
1200 let ResourceCycles = [2,1];
1201 }
1202 def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
1203 "VCVTSI642SSZrr",
1204 "VCVTUSI642SSZrr")>;
1206 def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
1207 let Latency = 6;
1208 let NumMicroOps = 4;
1209 let ResourceCycles = [1,1,1,1];
1210 }
1211 def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
1213 def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1214 let Latency = 6;
1215 let NumMicroOps = 4;
1216 let ResourceCycles = [1,1,1,1];
1217 }
1218 def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
1219 "SHL(8|16|32|64)m(1|i)",
1220 "SHR(8|16|32|64)m(1|i)")>;
1222 def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1223 let Latency = 6;
1224 let NumMicroOps = 4;
1225 let ResourceCycles = [1,1,1,1];
1226 }
1227 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
1228 "PUSH(16|32|64)rmm")>;
1230 def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
1231 let Latency = 6;
1232 let NumMicroOps = 6;
1233 let ResourceCycles = [1,5];
1234 }
1235 def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
1237 def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
1238 let Latency = 7;
1239 let NumMicroOps = 1;
1240 let ResourceCycles = [1];
1241 }
1242 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
1243 def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
1244 VBROADCASTI128,
1245 VBROADCASTSDYrm,
1246 VBROADCASTSSYrm,
1247 VMOVDDUPYrm,
1248 VMOVSHDUPYrm,
1249 VMOVSLDUPYrm,
1250 VPBROADCASTDYrm,
1251 VPBROADCASTQYrm)>;
1253 def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
1254 let Latency = 7;
1255 let NumMicroOps = 2;
1256 let ResourceCycles = [1,1];
1257 }
1258 def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
1260 def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1261 let Latency = 7;
1262 let NumMicroOps = 2;
1263 let ResourceCycles = [1,1];
1264 }
1265 def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
1266 "VMOVSSZrm(b?)")>;
1268 def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
1269 let Latency = 6;
1270 let NumMicroOps = 2;
1271 let ResourceCycles = [1,1];
1272 }
1273 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
1274 "(V?)PMOV(SX|ZX)BQrm",
1275 "(V?)PMOV(SX|ZX)BWrm",
1276 "(V?)PMOV(SX|ZX)DQrm",
1277 "(V?)PMOV(SX|ZX)WDrm",
1278 "(V?)PMOV(SX|ZX)WQrm")>;
1280 def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1281 let Latency = 7;
1282 let NumMicroOps = 2;
1283 let ResourceCycles = [1,1];
1284 }
1285 def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
1286 "VCVTPD2DQ(Y|Z256)rr",
1287 "VCVTPD2PS(Y|Z256)rr",
1288 "VCVTPD2UDQZ256rr",
1289 "VCVTPS2PD(Y|Z256)rr",
1290 "VCVTPS2QQZ256rr",
1291 "VCVTPS2UQQZ256rr",
1292 "VCVTQQ2PSZ256rr",
1293 "VCVTTPD2DQ(Y|Z256)rr",
1294 "VCVTTPD2UDQZ256rr",
1295 "VCVTTPS2QQZ256rr",
1296 "VCVTTPS2UQQZ256rr",
1297 "VCVTUDQ2PDZ256rr",
1298 "VCVTUQQ2PSZ256rr")>;
1300 def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
1301 let Latency = 7;
1302 let NumMicroOps = 2;
1303 let ResourceCycles = [1,1];
1304 }
1305 def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
1306 VCVTPD2DQZrr,
1307 VCVTPD2PSZrr,
1308 VCVTPD2UDQZrr,
1309 VCVTPS2PDZrr,
1310 VCVTPS2QQZrr,
1311 VCVTPS2UQQZrr,
1312 VCVTQQ2PSZrr,
1313 VCVTTPD2DQZrr,
1314 VCVTTPD2UDQZrr,
1315 VCVTTPS2QQZrr,
1316 VCVTTPS2UQQZrr,
1317 VCVTUDQ2PDZrr,
1318 VCVTUQQ2PSZrr)>;
1320 def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1321 let Latency = 7;
1322 let NumMicroOps = 2;
1323 let ResourceCycles = [1,1];
1324 }
1325 def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm,
1326 VPBLENDDrmi)>;
1327 def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd],
1328 (instregex "VBLENDMPDZ128rm(b?)",
1329 "VBLENDMPSZ128rm(b?)",
1330 "VBROADCASTI32X2Z128m(b?)",
1331 "VBROADCASTSSZ128m(b?)",
1332 "VINSERT(F|I)128rm",
1333 "VMOVAPDZ128rm(b?)",
1334 "VMOVAPSZ128rm(b?)",
1335 "VMOVDDUPZ128rm(b?)",
1336 "VMOVDQA32Z128rm(b?)",
1337 "VMOVDQA64Z128rm(b?)",
1338 "VMOVDQU16Z128rm(b?)",
1339 "VMOVDQU32Z128rm(b?)",
1340 "VMOVDQU64Z128rm(b?)",
1341 "VMOVDQU8Z128rm(b?)",
1342 "VMOVSHDUPZ128rm(b?)",
1343 "VMOVSLDUPZ128rm(b?)",
1344 "VMOVUPDZ128rm(b?)",
1345 "VMOVUPSZ128rm(b?)",
1346 "VPADD(B|D|Q|W)Z128rm(b?)",
1347 "(V?)PADD(B|D|Q|W)rm",
1348 "VPBLENDM(B|D|Q|W)Z128rm(b?)",
1349 "VPBROADCASTDZ128m(b?)",
1350 "VPBROADCASTQZ128m(b?)",
1351 "VPSUB(B|D|Q|W)Z128rm(b?)",
1352 "(V?)PSUB(B|D|Q|W)rm",
1353 "VPTERNLOGDZ128rm(b?)i",
1354 "VPTERNLOGQZ128rm(b?)i")>;
1356 def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1357 let Latency = 7;
1358 let NumMicroOps = 3;
1359 let ResourceCycles = [2,1];
1360 }
1361 def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWirm,
1362 MMX_PACKSSWBirm,
1363 MMX_PACKUSWBirm)>;
1365 def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1366 let Latency = 7;
1367 let NumMicroOps = 3;
1368 let ResourceCycles = [2,1];
1369 }
1370 def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
1371 "VPERMI2W256rr",
1372 "VPERMI2Wrr",
1373 "VPERMT2W128rr",
1374 "VPERMT2W256rr",
1375 "VPERMT2Wrr")>;
1377 def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1378 let Latency = 7;
1379 let NumMicroOps = 3;
1380 let ResourceCycles = [1,2];
1381 }
1382 def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
1383 SCASB, SCASL, SCASQ, SCASW)>;
1385 def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
1386 let Latency = 7;
1387 let NumMicroOps = 3;
1388 let ResourceCycles = [1,1,1];
1389 }
1390 def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
1391 "(V?)CVTSS2SI64(Z?)rr",
1392 "(V?)CVTTSS2SI64(Z?)rr",
1393 "VCVTTSS2USI64Zrr")>;
1395 def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
1396 let Latency = 7;
1397 let NumMicroOps = 3;
1398 let ResourceCycles = [1,1,1];
1399 }
1400 def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
1402 def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
1403 let Latency = 7;
1404 let NumMicroOps = 3;
1405 let ResourceCycles = [1,1,1];
1406 }
1407 def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
1409 def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
1410 let Latency = 7;
1411 let NumMicroOps = 3;
1412 let ResourceCycles = [1,1,1];
1413 }
1414 def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>;
1416 def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1417 let Latency = 7;
1418 let NumMicroOps = 4;
1419 let ResourceCycles = [1,2,1];
1420 }
1421 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
1422 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
1423 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
1424 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
1426 def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1427 let Latency = 7;
1428 let NumMicroOps = 5;
1429 let ResourceCycles = [1,1,1,2];
1430 }
1431 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1432 "ROR(8|16|32|64)m(1|i)")>;
1434 def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> {
1435 let Latency = 2;
1436 let NumMicroOps = 2;
1437 let ResourceCycles = [2];
1438 }
1439 def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1440 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1442 def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1443 let Latency = 7;
1444 let NumMicroOps = 5;
1445 let ResourceCycles = [1,1,1,2];
1446 }
1447 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
1449 def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
1450 let Latency = 7;
1451 let NumMicroOps = 5;
1452 let ResourceCycles = [1,1,1,1,1];
1453 }
1454 def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
1455 def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64)>;
1457 def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1458 let Latency = 7;
1459 let NumMicroOps = 7;
1460 let ResourceCycles = [1,2,2,2];
1461 }
1462 def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
1463 VPSCATTERQQZ128mr,
1464 VSCATTERDPDZ128mr,
1465 VSCATTERQPDZ128mr)>;
1467 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
1468 let Latency = 7;
1469 let NumMicroOps = 7;
1470 let ResourceCycles = [1,3,1,2];
1471 }
1472 def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
1474 def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1475 let Latency = 7;
1476 let NumMicroOps = 11;
1477 let ResourceCycles = [1,4,4,2];
1478 }
1479 def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
1480 VPSCATTERQQZ256mr,
1481 VSCATTERDPDZ256mr,
1482 VSCATTERQPDZ256mr)>;
1484 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1485 let Latency = 7;
1486 let NumMicroOps = 19;
1487 let ResourceCycles = [1,8,8,2];
1488 }
1489 def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
1490 VPSCATTERQQZmr,
1491 VSCATTERDPDZmr,
1492 VSCATTERQPDZmr)>;
1494 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1495 let Latency = 7;
1496 let NumMicroOps = 36;
1497 let ResourceCycles = [1,16,1,16,2];
1498 }
1499 def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
1501 def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
1502 let Latency = 8;
1503 let NumMicroOps = 2;
1504 let ResourceCycles = [1,1];
1505 }
1506 def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
1507 "PEXT(32|64)rm")>;
1509 def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1510 let Latency = 8;
1511 let NumMicroOps = 2;
1512 let ResourceCycles = [1,1];
1513 }
1514 def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
1515 "VFPCLASSSDZrm(b?)",
1516 "VPBROADCASTB(Z|Z256)m(b?)",
1517 "VPBROADCASTW(Z|Z256)m(b?)")>;
1518 def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm,
1519 VPBROADCASTWYrm,
1520 VPMOVSXBDYrm,
1521 VPMOVSXBQYrm,
1522 VPMOVSXWQYrm)>;
1524 def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1525 let Latency = 8;
1526 let NumMicroOps = 2;
1527 let ResourceCycles = [1,1];
1528 }
1529 def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm,
1530 VPBLENDDYrmi)>;
1531 def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd],
1532 (instregex "VBLENDMPD(Z|Z256)rm(b?)",
1533 "VBLENDMPS(Z|Z256)rm(b?)",
1534 "VBROADCASTF32X2Z256m(b?)",
1535 "VBROADCASTF32X2Zm(b?)",
1536 "VBROADCASTF32X4Z256rm(b?)",
1537 "VBROADCASTF32X4rm(b?)",
1538 "VBROADCASTF32X8rm(b?)",
1539 "VBROADCASTF64X2Z128rm(b?)",
1540 "VBROADCASTF64X2rm(b?)",
1541 "VBROADCASTF64X4rm(b?)",
1542 "VBROADCASTI32X2Z256m(b?)",
1543 "VBROADCASTI32X2Zm(b?)",
1544 "VBROADCASTI32X4Z256rm(b?)",
1545 "VBROADCASTI32X4rm(b?)",
1546 "VBROADCASTI32X8rm(b?)",
1547 "VBROADCASTI64X2Z128rm(b?)",
1548 "VBROADCASTI64X2rm(b?)",
1549 "VBROADCASTI64X4rm(b?)",
1550 "VBROADCASTSD(Z|Z256)m(b?)",
1551 "VBROADCASTSS(Z|Z256)m(b?)",
1552 "VINSERTF32x4(Z|Z256)rm(b?)",
1553 "VINSERTF32x8Zrm(b?)",
1554 "VINSERTF64x2(Z|Z256)rm(b?)",
1555 "VINSERTF64x4Zrm(b?)",
1556 "VINSERTI32x4(Z|Z256)rm(b?)",
1557 "VINSERTI32x8Zrm(b?)",
1558 "VINSERTI64x2(Z|Z256)rm(b?)",
1559 "VINSERTI64x4Zrm(b?)",
1560 "VMOVAPD(Z|Z256)rm(b?)",
1561 "VMOVAPS(Z|Z256)rm(b?)",
1562 "VMOVDDUP(Z|Z256)rm(b?)",
1563 "VMOVDQA32(Z|Z256)rm(b?)",
1564 "VMOVDQA64(Z|Z256)rm(b?)",
1565 "VMOVDQU16(Z|Z256)rm(b?)",
1566 "VMOVDQU32(Z|Z256)rm(b?)",
1567 "VMOVDQU64(Z|Z256)rm(b?)",
1568 "VMOVDQU8(Z|Z256)rm(b?)",
1569 "VMOVSHDUP(Z|Z256)rm(b?)",
1570 "VMOVSLDUP(Z|Z256)rm(b?)",
1571 "VMOVUPD(Z|Z256)rm(b?)",
1572 "VMOVUPS(Z|Z256)rm(b?)",
1573 "VPADD(B|D|Q|W)Yrm",
1574 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",
1575 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",
1576 "VPBROADCASTD(Z|Z256)m(b?)",
1577 "VPBROADCASTQ(Z|Z256)m(b?)",
1578 "VPSUB(B|D|Q|W)Yrm",
1579 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
1580 "VPTERNLOGD(Z|Z256)rm(b?)i",
1581 "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
1583 def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1584 let Latency = 8;
1585 let NumMicroOps = 4;
1586 let ResourceCycles = [1,2,1];
1587 }
1588 def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1590 def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1591 let Latency = 8;
1592 let NumMicroOps = 5;
1593 let ResourceCycles = [1,1,1,2];
1594 }
1595 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
1596 "RCR(8|16|32|64)m(1|i)")>;
1598 def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1599 let Latency = 8;
1600 let NumMicroOps = 6;
1601 let ResourceCycles = [1,1,1,3];
1602 }
1603 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
1604 "ROR(8|16|32|64)mCL",
1605 "SAR(8|16|32|64)mCL",
1606 "SHL(8|16|32|64)mCL",
1607 "SHR(8|16|32|64)mCL")>;
1609 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1610 let Latency = 8;
1611 let NumMicroOps = 6;
1612 let ResourceCycles = [1,1,1,2,1];
1613 }
1614 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
1616 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1617 let Latency = 8;
1618 let NumMicroOps = 8;
1619 let ResourceCycles = [1,2,1,2,2];
1620 }
1621 def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
1622 VPSCATTERQDZ256mr,
1623 VSCATTERQPSZ128mr,
1624 VSCATTERQPSZ256mr)>;
1626 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1627 let Latency = 8;
1628 let NumMicroOps = 12;
1629 let ResourceCycles = [1,4,1,4,2];
1630 }
1631 def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
1632 VSCATTERDPSZ128mr)>;
1634 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1635 let Latency = 8;
1636 let NumMicroOps = 20;
1637 let ResourceCycles = [1,8,1,8,2];
1638 }
1639 def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
1640 VSCATTERDPSZ256mr)>;
1642 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1643 let Latency = 8;
1644 let NumMicroOps = 36;
1645 let ResourceCycles = [1,16,1,16,2];
1646 }
1647 def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
1649 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1650 let Latency = 9;
1651 let NumMicroOps = 2;
1652 let ResourceCycles = [1,1];
1653 }
1654 def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>;
1656 def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1657 let Latency = 9;
1658 let NumMicroOps = 2;
1659 let ResourceCycles = [1,1];
1660 }
1661 def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm,
1662 VPMOVSXDQYrm,
1663 VPMOVSXWDYrm,
1664 VPMOVZXWDYrm)>;
1665 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
1666 "VCMP(PD|PS)Z128rm(b?)i",
1667 "VCMP(SD|SS)Zrm",
1668 "VFPCLASSSSZrm(b?)",
1669 "VPCMPBZ128rmi(b?)",
1670 "VPCMPDZ128rmi(b?)",
1671 "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
1672 "VPCMPGT(B|D|Q|W)Z128rm(b?)",
1673 "(V?)PCMPGTQrm",
1674 "VPCMPQZ128rmi(b?)",
1675 "VPCMPU(B|D|Q|W)Z128rmi(b?)",
1676 "VPCMPWZ128rmi(b?)",
1677 "VPERMI2D128rm(b?)",
1678 "VPERMI2PD128rm(b?)",
1679 "VPERMI2PS128rm(b?)",
1680 "VPERMI2Q128rm(b?)",
1681 "VPERMT2D128rm(b?)",
1682 "VPERMT2PD128rm(b?)",
1683 "VPERMT2PS128rm(b?)",
1684 "VPERMT2Q128rm(b?)",
1685 "VPMAXSQZ128rm(b?)",
1686 "VPMAXUQZ128rm(b?)",
1687 "VPMINSQZ128rm(b?)",
1688 "VPMINUQZ128rm(b?)",
1689 "VPMOVSXBDZ128rm(b?)",
1690 "VPMOVSXBQZ128rm(b?)",
1691 "VPMOVSXBWZ128rm(b?)",
1692 "VPMOVSXDQZ128rm(b?)",
1693 "VPMOVSXWDZ128rm(b?)",
1694 "VPMOVSXWQZ128rm(b?)",
1695 "VPMOVZXBDZ128rm(b?)",
1696 "VPMOVZXBQZ128rm(b?)",
1697 "VPMOVZXBWZ128rm(b?)",
1698 "VPMOVZXDQZ128rm(b?)",
1699 "VPMOVZXWDZ128rm(b?)",
1700 "VPMOVZXWQZ128rm(b?)",
1701 "VPTESTMBZ128rm(b?)",
1702 "VPTESTMDZ128rm(b?)",
1703 "VPTESTMQZ128rm(b?)",
1704 "VPTESTMWZ128rm(b?)",
1705 "VPTESTNMBZ128rm(b?)",
1706 "VPTESTNMDZ128rm(b?)",
1707 "VPTESTNMQZ128rm(b?)",
1708 "VPTESTNMWZ128rm(b?)")>;
1710 def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1711 let Latency = 9;
1712 let NumMicroOps = 2;
1713 let ResourceCycles = [1,1];
1714 }
1715 def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm",
1716 "(V?)CVTPS2PDrm")>;
1718 def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1719 let Latency = 9;
1720 let NumMicroOps = 4;
1721 let ResourceCycles = [2,1,1];
1722 }
1723 def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
1724 "(V?)PHSUBSWrm")>;
1726 def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
1727 let Latency = 9;
1728 let NumMicroOps = 5;
1729 let ResourceCycles = [1,2,1,1];
1730 }
1731 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
1732 "LSL(16|32|64)rm")>;
1734 def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1735 let Latency = 10;
1736 let NumMicroOps = 2;
1737 let ResourceCycles = [1,1];
1738 }
1739 def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>;
1740 def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1741 "ILD_F(16|32|64)m",
1742 "VALIGND(Z|Z256)rm(b?)i",
1743 "VALIGNQ(Z|Z256)rm(b?)i",
1744 "VCMPPD(Z|Z256)rm(b?)i",
1745 "VCMPPS(Z|Z256)rm(b?)i",
1746 "VPCMPB(Z|Z256)rmi(b?)",
1747 "VPCMPD(Z|Z256)rmi(b?)",
1748 "VPCMPEQB(Z|Z256)rm(b?)",
1749 "VPCMPEQD(Z|Z256)rm(b?)",
1750 "VPCMPEQQ(Z|Z256)rm(b?)",
1751 "VPCMPEQW(Z|Z256)rm(b?)",
1752 "VPCMPGTB(Z|Z256)rm(b?)",
1753 "VPCMPGTD(Z|Z256)rm(b?)",
1754 "VPCMPGTQ(Z|Z256)rm(b?)",
1755 "VPCMPGTW(Z|Z256)rm(b?)",
1756 "VPCMPQ(Z|Z256)rmi(b?)",
1757 "VPCMPU(B|D|Q|W)Z256rmi(b?)",
1758 "VPCMPU(B|D|Q|W)Zrmi(b?)",
1759 "VPCMPW(Z|Z256)rmi(b?)",
1760 "VPMAXSQ(Z|Z256)rm(b?)",
1761 "VPMAXUQ(Z|Z256)rm(b?)",
1762 "VPMINSQ(Z|Z256)rm(b?)",
1763 "VPMINUQ(Z|Z256)rm(b?)",
1764 "VPTESTM(B|D|Q|W)Z256rm(b?)",
1765 "VPTESTM(B|D|Q|W)Zrm(b?)",
1766 "VPTESTNM(B|D|Q|W)Z256rm(b?)",
1767 "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
1769 def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1770 let Latency = 10;
1771 let NumMicroOps = 2;
1772 let ResourceCycles = [1,1];
1773 }
1774 def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
1775 "VCVTDQ2PSZ128rm(b?)",
1776 "(V?)CVTDQ2PSrm",
1777 "VCVTPD2QQZ128rm(b?)",
1778 "VCVTPD2UQQZ128rm(b?)",
1779 "VCVTPH2PSZ128rm(b?)",
1780 "VCVTPS2DQZ128rm(b?)",
1781 "(V?)CVTPS2DQrm",
1782 "VCVTPS2PDZ128rm(b?)",
1783 "VCVTPS2QQZ128rm(b?)",
1784 "VCVTPS2UDQZ128rm(b?)",
1785 "VCVTPS2UQQZ128rm(b?)",
1786 "VCVTQQ2PDZ128rm(b?)",
1787 "VCVTQQ2PSZ128rm(b?)",
1788 "VCVTSS2SDZrm",
1789 "(V?)CVTSS2SDrm",
1790 "VCVTTPD2QQZ128rm(b?)",
1791 "VCVTTPD2UQQZ128rm(b?)",
1792 "VCVTTPS2DQZ128rm(b?)",
1793 "(V?)CVTTPS2DQrm",
1794 "VCVTTPS2QQZ128rm(b?)",
1795 "VCVTTPS2UDQZ128rm(b?)",
1796 "VCVTTPS2UQQZ128rm(b?)",
1797 "VCVTUDQ2PDZ128rm(b?)",
1798 "VCVTUDQ2PSZ128rm(b?)",
1799 "VCVTUQQ2PDZ128rm(b?)",
1800 "VCVTUQQ2PSZ128rm(b?)")>;
1802 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1803 let Latency = 10;
1804 let NumMicroOps = 3;
1805 let ResourceCycles = [2,1];
1806 }
1807 def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
1808 "VEXPANDPSZ128rm(b?)",
1809 "VPEXPANDDZ128rm(b?)",
1810 "VPEXPANDQZ128rm(b?)")>;
1812 def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1813 let Latency = 10;
1814 let NumMicroOps = 3;
1815 let ResourceCycles = [1,1,1];
1816 }
1817 def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>;
1819 def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1820 let Latency = 10;
1821 let NumMicroOps = 4;
1822 let ResourceCycles = [2,1,1];
1823 }
1824 def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,
1825 VPHSUBSWYrm)>;
1827 def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1828 let Latency = 10;
1829 let NumMicroOps = 8;
1830 let ResourceCycles = [1,1,1,1,1,3];
1831 }
1832 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
1834 def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
1835 let Latency = 11;
1836 let NumMicroOps = 1;
1837 let ResourceCycles = [1,3];
1838 }
1839 def : SchedAlias<WriteFDivX, SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair
1841 def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1842 let Latency = 11;
1843 let NumMicroOps = 2;
1844 let ResourceCycles = [1,1];
1845 }
1846 def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
1848 def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1849 let Latency = 11;
1850 let NumMicroOps = 2;
1851 let ResourceCycles = [1,1];
1852 }
1853 def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm,
1854 VCVTPS2PDYrm)>;
1855 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
1856 "VCVTPH2PS(Z|Z256)rm(b?)",
1857 "VCVTPS2PD(Z|Z256)rm(b?)",
1858 "VCVTQQ2PD(Z|Z256)rm(b?)",
1859 "VCVTQQ2PSZ256rm(b?)",
1860 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1861 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1862 "VCVT(T?)PS2DQYrm",
1863 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1864 "VCVT(T?)PS2QQZ256rm(b?)",
1865 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1866 "VCVT(T?)PS2UQQZ256rm(b?)",
1867 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",
1868 "VCVTUQQ2PD(Z|Z256)rm(b?)",
1869 "VCVTUQQ2PSZ256rm(b?)")>;
1871 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1872 let Latency = 11;
1873 let NumMicroOps = 3;
1874 let ResourceCycles = [2,1];
1875 }
1876 def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
1877 "VEXPANDPD(Z|Z256)rm(b?)",
1878 "VEXPANDPS(Z|Z256)rm(b?)",
1879 "VPEXPANDD(Z|Z256)rm(b?)",
1880 "VPEXPANDQ(Z|Z256)rm(b?)")>;
1882 def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1883 let Latency = 11;
1884 let NumMicroOps = 3;
1885 let ResourceCycles = [1,2];
1886 }
1887 def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>;
1889 def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1890 let Latency = 11;
1891 let NumMicroOps = 3;
1892 let ResourceCycles = [1,1,1];
1893 }
1894 def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
1896 def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1897 let Latency = 11;
1898 let NumMicroOps = 3;
1899 let ResourceCycles = [1,1,1];
1900 }
1901 def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2PSrm,
1902 CVTPD2DQrm,
1903 CVTTPD2DQrm,
1904 MMX_CVTPD2PIirm,
1905 MMX_CVTTPD2PIirm)>;
1907 def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1908 let Latency = 11;
1909 let NumMicroOps = 4;
1910 let ResourceCycles = [2,1,1];
1911 }
1912 def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
1914 def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1915 let Latency = 11;
1916 let NumMicroOps = 7;
1917 let ResourceCycles = [2,3,2];
1918 }
1919 def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
1920 "RCR(16|32|64)rCL")>;
1922 def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
1923 let Latency = 11;
1924 let NumMicroOps = 9;
1925 let ResourceCycles = [1,5,1,2];
1926 }
1927 def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>;
1929 def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1930 let Latency = 11;
1931 let NumMicroOps = 11;
1932 let ResourceCycles = [2,9];
1933 }
1934 def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
1936 def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
1937 let Latency = 12;
1938 let NumMicroOps = 3;
1939 let ResourceCycles = [3];
1940 }
1941 def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
1943 def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
1944 let Latency = 12;
1945 let NumMicroOps = 3;
1946 let ResourceCycles = [3];
1947 }
1948 def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
1950 def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1951 let Latency = 12;
1952 let NumMicroOps = 3;
1953 let ResourceCycles = [2,1];
1954 }
1955 def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
1957 def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
1958 let Latency = 12;
1959 let NumMicroOps = 3;
1960 let ResourceCycles = [1,1,1];
1961 }
1962 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
1963 "VCVT(T?)SS2USI64Zrm(b?)")>;
1965 def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1966 let Latency = 12;
1967 let NumMicroOps = 3;
1968 let ResourceCycles = [1,1,1];
1969 }
1970 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
1971 "VCVT(T?)PS2UQQZrm(b?)")>;
1973 def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
1974 let Latency = 12;
1975 let NumMicroOps = 4;
1976 let ResourceCycles = [1,1,1,1];
1977 }
1978 def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
1980 def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1981 let Latency = 13;
1982 let NumMicroOps = 3;
1983 let ResourceCycles = [2,1];
1984 }
1985 def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
1986 "VPERMWZ256rm(b?)",
1987 "VPERMWZrm(b?)")>;
1989 def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1990 let Latency = 13;
1991 let NumMicroOps = 3;
1992 let ResourceCycles = [1,1,1];
1993 }
1994 def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
1996 def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1997 let Latency = 13;
1998 let NumMicroOps = 4;
1999 let ResourceCycles = [2,1,1];
2000 }
2001 def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
2002 "VPERMT2W128rm(b?)")>;
2004 def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2005 let Latency = 14;
2006 let NumMicroOps = 1;
2007 let ResourceCycles = [1,3];
2008 }
2009 def : SchedAlias<WriteFDiv64, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2010 def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2012 def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2013 let Latency = 14;
2014 let NumMicroOps = 1;
2015 let ResourceCycles = [1,5];
2016 }
2017 def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair
2019 def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2020 let Latency = 14;
2021 let NumMicroOps = 3;
2022 let ResourceCycles = [1,1,1];
2023 }
2024 def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
2026 def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2027 let Latency = 14;
2028 let NumMicroOps = 3;
2029 let ResourceCycles = [1,1,1];
2030 }
2031 def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
2032 "VCVTPD2PSZrm(b?)",
2033 "VCVTPD2UDQZrm(b?)",
2034 "VCVTQQ2PSZrm(b?)",
2035 "VCVTTPD2DQZrm(b?)",
2036 "VCVTTPD2UDQZrm(b?)",
2037 "VCVTUQQ2PSZrm(b?)")>;
2039 def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2040 let Latency = 14;
2041 let NumMicroOps = 4;
2042 let ResourceCycles = [2,1,1];
2043 }
2044 def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
2045 "VPERMI2Wrm(b?)",
2046 "VPERMT2W256rm(b?)",
2047 "VPERMT2Wrm(b?)")>;
2049 def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2050 let Latency = 14;
2051 let NumMicroOps = 10;
2052 let ResourceCycles = [2,4,1,3];
2053 }
2054 def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>;
2056 def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
2057 let Latency = 15;
2058 let NumMicroOps = 1;
2059 let ResourceCycles = [1];
2060 }
2061 def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
2063 def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2064 let Latency = 15;
2065 let NumMicroOps = 8;
2066 let ResourceCycles = [1,2,2,1,2];
2067 }
2068 def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
2070 def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2071 let Latency = 15;
2072 let NumMicroOps = 10;
2073 let ResourceCycles = [1,1,1,5,1,1];
2074 }
2075 def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
2077 def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2078 let Latency = 16;
2079 let NumMicroOps = 14;
2080 let ResourceCycles = [1,1,1,4,2,5];
2081 }
2082 def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
2084 def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> {
2085 let Latency = 12;
2086 let NumMicroOps = 34;
2087 let ResourceCycles = [1, 4, 5];
2088 }
2089 def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
2091 def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2092 let Latency = 17;
2093 let NumMicroOps = 2;
2094 let ResourceCycles = [1,1,5];
2095 }
2096 def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair
2098 def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2099 let Latency = 17;
2100 let NumMicroOps = 15;
2101 let ResourceCycles = [2,1,2,4,2,4];
2102 }
2103 def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
2105 def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2106 let Latency = 18;
2107 let NumMicroOps = 4;
2108 let ResourceCycles = [1,3];
2109 }
2110 def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
2112 def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2113 let Latency = 18;
2114 let NumMicroOps = 8;
2115 let ResourceCycles = [1,1,1,5];
2116 }
2117 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
2119 def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2120 let Latency = 18;
2121 let NumMicroOps = 11;
2122 let ResourceCycles = [2,1,1,4,1,2];
2123 }
2124 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
2126 def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2127 let Latency = 19;
2128 let NumMicroOps = 2;
2129 let ResourceCycles = [1,1,4];
2130 }
2131 def : SchedAlias<WriteFDiv64Ld, SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair
2133 def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2134 let Latency = 19;
2135 let NumMicroOps = 4;
2136 let ResourceCycles = [1,3];
2137 }
2138 def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)",
2139 "VPMULLQZrm(b?)")>;
2141 def SKXWriteResGroup214 : SchedWriteRes<[]> {
2142 let Latency = 20;
2143 let NumMicroOps = 0;
2144 }
2145 def: InstRW<[SKXWriteResGroup214], (instrs VGATHERDPSZ128rm,
2146 VGATHERQPSZrm,
2147 VPGATHERDDZ128rm)>;
2149 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
2150 let Latency = 20;
2151 let NumMicroOps = 1;
2152 let ResourceCycles = [1];
2153 }
2154 def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
2156 def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2157 let Latency = 20;
2158 let NumMicroOps = 2;
2159 let ResourceCycles = [1,1,4];
2160 }
2161 def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair
2163 def SKXWriteResGroup218 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2164 let Latency = 20;
2165 let NumMicroOps = 5;
2166 let ResourceCycles = [1,2,1,1];
2167 }
2168 def: InstRW<[SKXWriteResGroup218], (instrs VGATHERQPSZ128rm,
2169 VGATHERQPSZ256rm,
2170 VPGATHERQDZ128rm,
2171 VPGATHERQDZ256rm)>;
2173 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2174 let Latency = 20;
2175 let NumMicroOps = 8;
2176 let ResourceCycles = [1,1,1,1,1,1,2];
2177 }
2178 def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
2180 def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
2181 let Latency = 20;
2182 let NumMicroOps = 10;
2183 let ResourceCycles = [1,2,7];
2184 }
2185 def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
2187 def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2188 let Latency = 21;
2189 let NumMicroOps = 2;
2190 let ResourceCycles = [1,1,8];
2191 }
2192 def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair
2194 def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2195 let Latency = 22;
2196 let NumMicroOps = 2;
2197 let ResourceCycles = [1,1];
2198 }
2199 def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
2201 def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2202 let Latency = 22;
2203 let NumMicroOps = 5;
2204 let ResourceCycles = [1,2,1,1];
2205 }
2206 def: InstRW<[SKXWriteResGroup224], (instrs VGATHERDPDZ128rm,
2207 VGATHERQPDZ128rm,
2208 VPGATHERDQZ128rm,
2209 VPGATHERQQZ128rm)>;
2211 def SKXWriteResGroup224_2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2212 let Latency = 22;
2213 let NumMicroOps = 5;
2214 let ResourceCycles = [1,2,1,1];
2215 }
2216 def: InstRW<[SKXWriteResGroup224_2], (instrs VGATHERDPSrm,
2217 VGATHERDPDrm,
2218 VGATHERQPDrm,
2219 VGATHERQPSrm,
2220 VPGATHERDDrm,
2221 VPGATHERDQrm,
2222 VPGATHERQDrm,
2223 VPGATHERQQrm,
2224 VPGATHERDDrm,
2225 VPGATHERQDrm,
2226 VPGATHERDQrm,
2227 VPGATHERQQrm,
2228 VGATHERDPSrm,
2229 VGATHERQPSrm,
2230 VGATHERDPDrm,
2231 VGATHERQPDrm)>;
2233 def SKXWriteResGroup224_3 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2234 let Latency = 25;
2235 let NumMicroOps = 5;
2236 let ResourceCycles = [1,2,1,1];
2237 }
2238 def: InstRW<[SKXWriteResGroup224_3], (instrs VGATHERDPSYrm,
2239 VGATHERQPDYrm,
2240 VGATHERQPSYrm,
2241 VPGATHERDDYrm,
2242 VPGATHERDQYrm,
2243 VPGATHERQDYrm,
2244 VPGATHERQQYrm,
2245 VPGATHERDDYrm,
2246 VPGATHERQDYrm,
2247 VPGATHERDQYrm,
2248 VPGATHERQQYrm,
2249 VGATHERDPSYrm,
2250 VGATHERQPSYrm,
2251 VGATHERDPDYrm)>;
2253 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2254 let Latency = 22;
2255 let NumMicroOps = 14;
2256 let ResourceCycles = [5,5,4];
2257 }
2258 def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
2259 "VPCONFLICTQZ256rr")>;
2261 def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2262 let Latency = 23;
2263 let NumMicroOps = 19;
2264 let ResourceCycles = [2,1,4,1,1,4,6];
2265 }
2266 def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
2268 def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2269 let Latency = 25;
2270 let NumMicroOps = 3;
2271 let ResourceCycles = [1,1,1];
2272 }
2273 def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
2275 def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2276 let Latency = 25;
2277 let NumMicroOps = 5;
2278 let ResourceCycles = [1,2,1,1];
2279 }
2280 def: InstRW<[SKXWriteResGroup234], (instrs VGATHERDPDZ256rm,
2281 VGATHERQPDZ256rm,
2282 VPGATHERDQZ256rm,
2283 VPGATHERQDZrm,
2284 VPGATHERQQZ256rm)>;
2286 def SKXWriteResGroup238 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2287 let Latency = 26;
2288 let NumMicroOps = 5;
2289 let ResourceCycles = [1,2,1,1];
2290 }
2291 def: InstRW<[SKXWriteResGroup238], (instrs VGATHERDPDZrm,
2292 VGATHERQPDZrm,
2293 VPGATHERDQZrm,
2294 VPGATHERQQZrm)>;
2296 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2297 let Latency = 27;
2298 let NumMicroOps = 2;
2299 let ResourceCycles = [1,1];
2300 }
2301 def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
2303 def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2304 let Latency = 27;
2305 let NumMicroOps = 5;
2306 let ResourceCycles = [1,2,1,1];
2307 }
2308 def: InstRW<[SKXWriteResGroup240], (instrs VGATHERDPSZ256rm,
2309 VPGATHERDDZ256rm)>;
2311 def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2312 let Latency = 29;
2313 let NumMicroOps = 15;
2314 let ResourceCycles = [5,5,1,4];
2315 }
2316 def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
2318 def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2319 let Latency = 30;
2320 let NumMicroOps = 3;
2321 let ResourceCycles = [1,1,1];
2322 }
2323 def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
2325 def SKXWriteResGroup245 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2326 let Latency = 30;
2327 let NumMicroOps = 5;
2328 let ResourceCycles = [1,2,1,1];
2329 }
2330 def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm,
2331 VPGATHERDDZrm)>;
2333 def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
2334 let Latency = 35;
2335 let NumMicroOps = 23;
2336 let ResourceCycles = [1,5,3,4,10];
2337 }
2338 def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
2339 "IN(8|16|32)rr")>;
2341 def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2342 let Latency = 35;
2343 let NumMicroOps = 23;
2344 let ResourceCycles = [1,5,2,1,4,10];
2345 }
2346 def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
2347 "OUT(8|16|32)rr")>;
2349 def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2350 let Latency = 37;
2351 let NumMicroOps = 21;
2352 let ResourceCycles = [9,7,5];
2353 }
2354 def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
2355 "VPCONFLICTQZrr")>;
2357 def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
2358 let Latency = 37;
2359 let NumMicroOps = 31;
2360 let ResourceCycles = [1,8,1,21];
2361 }
2362 def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
2364 def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
2365 let Latency = 40;
2366 let NumMicroOps = 18;
2367 let ResourceCycles = [1,1,2,3,1,1,1,8];
2368 }
2369 def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
2371 def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2372 let Latency = 41;
2373 let NumMicroOps = 39;
2374 let ResourceCycles = [1,10,1,1,26];
2375 }
2376 def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
2378 def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
2379 let Latency = 42;
2380 let NumMicroOps = 22;
2381 let ResourceCycles = [2,20];
2382 }
2383 def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
2385 def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2386 let Latency = 42;
2387 let NumMicroOps = 40;
2388 let ResourceCycles = [1,11,1,1,26];
2389 }
2390 def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
2391 def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
2393 def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2394 let Latency = 44;
2395 let NumMicroOps = 22;
2396 let ResourceCycles = [9,7,1,5];
2397 }
2398 def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
2399 "VPCONFLICTQZrm(b?)")>;
2401 def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
2402 let Latency = 62;
2403 let NumMicroOps = 64;
2404 let ResourceCycles = [2,8,5,10,39];
2405 }
2406 def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
2408 def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2409 let Latency = 63;
2410 let NumMicroOps = 88;
2411 let ResourceCycles = [4,4,31,1,2,1,45];
2412 }
2413 def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
2415 def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2416 let Latency = 63;
2417 let NumMicroOps = 90;
2418 let ResourceCycles = [4,2,33,1,2,1,47];
2419 }
2420 def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
2422 def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2423 let Latency = 67;
2424 let NumMicroOps = 35;
2425 let ResourceCycles = [17,11,7];
2426 }
2427 def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
2429 def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2430 let Latency = 74;
2431 let NumMicroOps = 36;
2432 let ResourceCycles = [17,11,1,7];
2433 }
2434 def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
2436 def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
2437 let Latency = 75;
2438 let NumMicroOps = 15;
2439 let ResourceCycles = [6,3,6];
2440 }
2441 def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
2443 def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
2444 let Latency = 106;
2445 let NumMicroOps = 100;
2446 let ResourceCycles = [9,1,11,16,1,11,21,30];
2447 }
2448 def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
2450 def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
2451 let Latency = 140;
2452 let NumMicroOps = 4;
2453 let ResourceCycles = [1,3];
2454 }
2455 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
2457 def: InstRW<[WriteZero], (instrs CLC)>;
2460 // Intruction variants handled by the renamer. These might not need execution
2461 // ports in certain conditions.
2462 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
2463 // section "Skylake Pipeline" > "Register allocation and renaming".
2464 // These can be investigated with llvm-exegesis, e.g.
2465 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2466 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2468 def SKXWriteZeroLatency : SchedWriteRes<[]> {
2469 let Latency = 0;
2470 }
2472 def SKXWriteZeroIdiom : SchedWriteVariant<[
2473 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2474 SchedVar<NoSchedPred, [WriteALU]>
2475 ]>;
2476 def : InstRW<[SKXWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
2477 XOR32rr, XOR64rr)>;
2479 def SKXWriteFZeroIdiom : SchedWriteVariant<[
2480 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2481 SchedVar<NoSchedPred, [WriteFLogic]>
2482 ]>;
2483 def : InstRW<[SKXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr,
2484 XORPDrr, VXORPDrr,
2485 VXORPSZ128rr,
2486 VXORPDZ128rr)>;
2488 def SKXWriteFZeroIdiomY : SchedWriteVariant<[
2489 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2490 SchedVar<NoSchedPred, [WriteFLogicY]>
2491 ]>;
2492 def : InstRW<[SKXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
2493 VXORPSZ256rr, VXORPDZ256rr)>;
2495 def SKXWriteFZeroIdiomZ : SchedWriteVariant<[
2496 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2497 SchedVar<NoSchedPred, [WriteFLogicZ]>
2498 ]>;
2499 def : InstRW<[SKXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>;
2501 def SKXWriteVZeroIdiomLogicX : SchedWriteVariant<[
2502 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2503 SchedVar<NoSchedPred, [WriteVecLogicX]>
2504 ]>;
2505 def : InstRW<[SKXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr,
2506 VPXORDZ128rr, VPXORQZ128rr)>;
2508 def SKXWriteVZeroIdiomLogicY : SchedWriteVariant<[
2509 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2510 SchedVar<NoSchedPred, [WriteVecLogicY]>
2511 ]>;
2512 def : InstRW<[SKXWriteVZeroIdiomLogicY], (instrs VPXORYrr,
2513 VPXORDZ256rr, VPXORQZ256rr)>;
2515 def SKXWriteVZeroIdiomLogicZ : SchedWriteVariant<[
2516 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2517 SchedVar<NoSchedPred, [WriteVecLogicZ]>
2518 ]>;
2519 def : InstRW<[SKXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>;
2521 def SKXWriteVZeroIdiomALUX : SchedWriteVariant<[
2522 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2523 SchedVar<NoSchedPred, [WriteVecALUX]>
2524 ]>;
2525 def : InstRW<[SKXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,
2526 PCMPGTDrr, VPCMPGTDrr,
2527 PCMPGTWrr, VPCMPGTWrr)>;
2529 def SKXWriteVZeroIdiomALUY : SchedWriteVariant<[
2530 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2531 SchedVar<NoSchedPred, [WriteVecALUY]>
2532 ]>;
2533 def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
2534 VPCMPGTDYrr,
2535 VPCMPGTWYrr)>;
2537 def SKXWritePSUB : SchedWriteRes<[SKXPort015]> {
2538 let Latency = 1;
2539 let NumMicroOps = 1;
2540 let ResourceCycles = [1];
2541 }
2543 def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[
2544 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2545 SchedVar<NoSchedPred, [SKXWritePSUB]>
2546 ]>;
2548 def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr,
2549 PSUBDrr, VPSUBDrr, VPSUBDZ128rr,
2550 PSUBQrr, VPSUBQrr, VPSUBQZ128rr,
2551 PSUBWrr, VPSUBWrr, VPSUBWZ128rr,
2552 VPSUBBYrr, VPSUBBZ256rr,
2553 VPSUBDYrr, VPSUBDZ256rr,
2554 VPSUBQYrr, VPSUBQZ256rr,
2555 VPSUBWYrr, VPSUBWZ256rr,
2556 VPSUBBZrr,
2557 VPSUBDZrr,
2558 VPSUBQZrr,
2559 VPSUBWZrr)>;
2560 def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> {
2561 let Latency = 3;
2562 let NumMicroOps = 1;
2563 let ResourceCycles = [1];
2564 }
2566 def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
2567 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2568 SchedVar<NoSchedPred, [SKXWritePCMPGTQ]>
2569 ]>;
2570 def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
2571 VPCMPGTQYrr)>;
2574 // CMOVs that use both Z and C flag require an extra uop.
2575 def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> {
2576 let Latency = 2;
2577 let ResourceCycles = [2];
2578 let NumMicroOps = 2;
2579 }
2581 def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> {
2582 let Latency = 7;
2583 let ResourceCycles = [1,2];
2584 let NumMicroOps = 3;
2585 }
2587 def SKXCMOVA_CMOVBErr : SchedWriteVariant<[
2588 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKXWriteCMOVA_CMOVBErr]>,
2589 SchedVar<NoSchedPred, [WriteCMOV]>
2590 ]>;
2592 def SKXCMOVA_CMOVBErm : SchedWriteVariant<[
2593 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>,
2594 SchedVar<NoSchedPred, [WriteCMOV.Folded]>
2595 ]>;
2597 def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
2598 def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
2600 // SETCCs that use both Z and C flag require an extra uop.
2601 def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> {
2602 let Latency = 2;
2603 let ResourceCycles = [2];
2604 let NumMicroOps = 2;
2605 }
2607 def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
2608 let Latency = 3;
2609 let ResourceCycles = [1,1,2];
2610 let NumMicroOps = 4;
2611 }
2613 def SKXSETA_SETBErr : SchedWriteVariant<[
2614 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>,
2615 SchedVar<NoSchedPred, [WriteSETCC]>
2616 ]>;
2618 def SKXSETA_SETBErm : SchedWriteVariant<[
2619 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKXWriteSETA_SETBEm]>,
2620 SchedVar<NoSchedPred, [WriteSETCCStore]>
2621 ]>;
2623 def : InstRW<[SKXSETA_SETBErr], (instrs SETCCr)>;
2624 def : InstRW<[SKXSETA_SETBErm], (instrs SETCCm)>;
2626 } // SchedModel