[AMDGPU] Check for immediate SrcC in mfma in AsmParser
[llvm-core.git] / lib / Target / X86 / X86Subtarget.h
blob9f73a821da294a22ba34f8cd9dcfd81fbe2b3bdd
1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the X86 specific subclass of TargetSubtargetInfo.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
14 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
16 #include "X86FrameLowering.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86SelectionDAGInfo.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
24 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
25 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include <climits>
30 #include <memory>
32 #define GET_SUBTARGETINFO_HEADER
33 #include "X86GenSubtargetInfo.inc"
35 namespace llvm {
37 class GlobalValue;
39 /// The X86 backend supports a number of different styles of PIC.
40 ///
41 namespace PICStyles {
43 enum Style {
44 StubPIC, // Used on i386-darwin in pic mode.
45 GOT, // Used on 32 bit elf on when in pic mode.
46 RIPRel, // Used on X86-64 when in pic mode.
47 None // Set when not in pic mode.
50 } // end namespace PICStyles
52 class X86Subtarget final : public X86GenSubtargetInfo {
53 public:
54 // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
55 // are not a good idea. We should be migrating away from these.
56 enum X86ProcFamilyEnum {
57 Others,
58 IntelAtom,
59 IntelSLM,
60 IntelGLM,
61 IntelGLP,
62 IntelTRM
65 protected:
66 enum X86SSEEnum {
67 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
70 enum X863DNowEnum {
71 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
74 /// X86 processor family: Intel Atom, and others
75 X86ProcFamilyEnum X86ProcFamily = Others;
77 /// Which PIC style to use
78 PICStyles::Style PICStyle;
80 const TargetMachine &TM;
82 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
83 X86SSEEnum X86SSELevel = NoSSE;
85 /// MMX, 3DNow, 3DNow Athlon, or none supported.
86 X863DNowEnum X863DNowLevel = NoThreeDNow;
88 /// True if the processor supports X87 instructions.
89 bool HasX87 = false;
91 /// True if the processor supports CMPXCHG8B.
92 bool HasCmpxchg8b = false;
94 /// True if this processor has NOPL instruction
95 /// (generally pentium pro+).
96 bool HasNOPL = false;
98 /// True if this processor has conditional move instructions
99 /// (generally pentium pro+).
100 bool HasCMov = false;
102 /// True if the processor supports X86-64 instructions.
103 bool HasX86_64 = false;
105 /// True if the processor supports POPCNT.
106 bool HasPOPCNT = false;
108 /// True if the processor supports SSE4A instructions.
109 bool HasSSE4A = false;
111 /// Target has AES instructions
112 bool HasAES = false;
113 bool HasVAES = false;
115 /// Target has FXSAVE/FXRESTOR instructions
116 bool HasFXSR = false;
118 /// Target has XSAVE instructions
119 bool HasXSAVE = false;
121 /// Target has XSAVEOPT instructions
122 bool HasXSAVEOPT = false;
124 /// Target has XSAVEC instructions
125 bool HasXSAVEC = false;
127 /// Target has XSAVES instructions
128 bool HasXSAVES = false;
130 /// Target has carry-less multiplication
131 bool HasPCLMUL = false;
132 bool HasVPCLMULQDQ = false;
134 /// Target has Galois Field Arithmetic instructions
135 bool HasGFNI = false;
137 /// Target has 3-operand fused multiply-add
138 bool HasFMA = false;
140 /// Target has 4-operand fused multiply-add
141 bool HasFMA4 = false;
143 /// Target has XOP instructions
144 bool HasXOP = false;
146 /// Target has TBM instructions.
147 bool HasTBM = false;
149 /// Target has LWP instructions
150 bool HasLWP = false;
152 /// True if the processor has the MOVBE instruction.
153 bool HasMOVBE = false;
155 /// True if the processor has the RDRAND instruction.
156 bool HasRDRAND = false;
158 /// Processor has 16-bit floating point conversion instructions.
159 bool HasF16C = false;
161 /// Processor has FS/GS base insturctions.
162 bool HasFSGSBase = false;
164 /// Processor has LZCNT instruction.
165 bool HasLZCNT = false;
167 /// Processor has BMI1 instructions.
168 bool HasBMI = false;
170 /// Processor has BMI2 instructions.
171 bool HasBMI2 = false;
173 /// Processor has VBMI instructions.
174 bool HasVBMI = false;
176 /// Processor has VBMI2 instructions.
177 bool HasVBMI2 = false;
179 /// Processor has Integer Fused Multiply Add
180 bool HasIFMA = false;
182 /// Processor has RTM instructions.
183 bool HasRTM = false;
185 /// Processor has ADX instructions.
186 bool HasADX = false;
188 /// Processor has SHA instructions.
189 bool HasSHA = false;
191 /// Processor has PRFCHW instructions.
192 bool HasPRFCHW = false;
194 /// Processor has RDSEED instructions.
195 bool HasRDSEED = false;
197 /// Processor has LAHF/SAHF instructions.
198 bool HasLAHFSAHF = false;
200 /// Processor has MONITORX/MWAITX instructions.
201 bool HasMWAITX = false;
203 /// Processor has Cache Line Zero instruction
204 bool HasCLZERO = false;
206 /// Processor has Cache Line Demote instruction
207 bool HasCLDEMOTE = false;
209 /// Processor has MOVDIRI instruction (direct store integer).
210 bool HasMOVDIRI = false;
212 /// Processor has MOVDIR64B instruction (direct store 64 bytes).
213 bool HasMOVDIR64B = false;
215 /// Processor has ptwrite instruction.
216 bool HasPTWRITE = false;
218 /// Processor has Prefetch with intent to Write instruction
219 bool HasPREFETCHWT1 = false;
221 /// True if SHLD instructions are slow.
222 bool IsSHLDSlow = false;
224 /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
225 // PMULUDQ.
226 bool IsPMULLDSlow = false;
228 /// True if the PMADDWD instruction is slow compared to PMULLD.
229 bool IsPMADDWDSlow = false;
231 /// True if unaligned memory accesses of 16-bytes are slow.
232 bool IsUAMem16Slow = false;
234 /// True if unaligned memory accesses of 32-bytes are slow.
235 bool IsUAMem32Slow = false;
237 /// True if SSE operations can have unaligned memory operands.
238 /// This may require setting a configuration bit in the processor.
239 bool HasSSEUnalignedMem = false;
241 /// True if this processor has the CMPXCHG16B instruction;
242 /// this is true for most x86-64 chips, but not the first AMD chips.
243 bool HasCmpxchg16b = false;
245 /// True if the LEA instruction should be used for adjusting
246 /// the stack pointer. This is an optimization for Intel Atom processors.
247 bool UseLeaForSP = false;
249 /// True if POPCNT instruction has a false dependency on the destination register.
250 bool HasPOPCNTFalseDeps = false;
252 /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
253 bool HasLZCNTFalseDeps = false;
255 /// True if its preferable to combine to a single shuffle using a variable
256 /// mask over multiple fixed shuffles.
257 bool HasFastVariableShuffle = false;
259 /// True if there is no performance penalty to writing only the lower parts
260 /// of a YMM or ZMM register without clearing the upper part.
261 bool HasFastPartialYMMorZMMWrite = false;
263 /// True if there is no performance penalty for writing NOPs with up to
264 /// 11 bytes.
265 bool HasFast11ByteNOP = false;
267 /// True if there is no performance penalty for writing NOPs with up to
268 /// 15 bytes.
269 bool HasFast15ByteNOP = false;
271 /// True if gather is reasonably fast. This is true for Skylake client and
272 /// all AVX-512 CPUs.
273 bool HasFastGather = false;
275 /// True if hardware SQRTSS instruction is at least as fast (latency) as
276 /// RSQRTSS followed by a Newton-Raphson iteration.
277 bool HasFastScalarFSQRT = false;
279 /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
280 /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
281 bool HasFastVectorFSQRT = false;
283 /// True if 8-bit divisions are significantly faster than
284 /// 32-bit divisions and should be used when possible.
285 bool HasSlowDivide32 = false;
287 /// True if 32-bit divides are significantly faster than
288 /// 64-bit divisions and should be used when possible.
289 bool HasSlowDivide64 = false;
291 /// True if LZCNT instruction is fast.
292 bool HasFastLZCNT = false;
294 /// True if SHLD based rotate is fast.
295 bool HasFastSHLDRotate = false;
297 /// True if the processor supports macrofusion.
298 bool HasMacroFusion = false;
300 /// True if the processor supports branch fusion.
301 bool HasBranchFusion = false;
303 /// True if the processor has enhanced REP MOVSB/STOSB.
304 bool HasERMSB = false;
306 /// True if the short functions should be padded to prevent
307 /// a stall when returning too early.
308 bool PadShortFunctions = false;
310 /// True if two memory operand instructions should use a temporary register
311 /// instead.
312 bool SlowTwoMemOps = false;
314 /// True if the LEA instruction inputs have to be ready at address generation
315 /// (AG) time.
316 bool LEAUsesAG = false;
318 /// True if the LEA instruction with certain arguments is slow
319 bool SlowLEA = false;
321 /// True if the LEA instruction has all three source operands: base, index,
322 /// and offset or if the LEA instruction uses base and index registers where
323 /// the base is EBP, RBP,or R13
324 bool Slow3OpsLEA = false;
326 /// True if INC and DEC instructions are slow when writing to flags
327 bool SlowIncDec = false;
329 /// Processor has AVX-512 PreFetch Instructions
330 bool HasPFI = false;
332 /// Processor has AVX-512 Exponential and Reciprocal Instructions
333 bool HasERI = false;
335 /// Processor has AVX-512 Conflict Detection Instructions
336 bool HasCDI = false;
338 /// Processor has AVX-512 population count Instructions
339 bool HasVPOPCNTDQ = false;
341 /// Processor has AVX-512 Doubleword and Quadword instructions
342 bool HasDQI = false;
344 /// Processor has AVX-512 Byte and Word instructions
345 bool HasBWI = false;
347 /// Processor has AVX-512 Vector Length eXtenstions
348 bool HasVLX = false;
350 /// Processor has PKU extenstions
351 bool HasPKU = false;
353 /// Processor has AVX-512 Vector Neural Network Instructions
354 bool HasVNNI = false;
356 /// Processor has AVX-512 bfloat16 floating-point extensions
357 bool HasBF16 = false;
359 /// Processor supports ENQCMD instructions
360 bool HasENQCMD = false;
362 /// Processor has AVX-512 Bit Algorithms instructions
363 bool HasBITALG = false;
365 /// Processor has AVX-512 vp2intersect instructions
366 bool HasVP2INTERSECT = false;
368 /// Processor supports MPX - Memory Protection Extensions
369 bool HasMPX = false;
371 /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
372 /// using Shadow Stack
373 bool HasSHSTK = false;
375 /// Processor supports Invalidate Process-Context Identifier
376 bool HasINVPCID = false;
378 /// Processor has Software Guard Extensions
379 bool HasSGX = false;
381 /// Processor supports Flush Cache Line instruction
382 bool HasCLFLUSHOPT = false;
384 /// Processor supports Cache Line Write Back instruction
385 bool HasCLWB = false;
387 /// Processor supports Write Back No Invalidate instruction
388 bool HasWBNOINVD = false;
390 /// Processor support RDPID instruction
391 bool HasRDPID = false;
393 /// Processor supports WaitPKG instructions
394 bool HasWAITPKG = false;
396 /// Processor supports PCONFIG instruction
397 bool HasPCONFIG = false;
399 /// Processor has a single uop BEXTR implementation.
400 bool HasFastBEXTR = false;
402 /// Try harder to combine to horizontal vector ops if they are fast.
403 bool HasFastHorizontalOps = false;
405 /// Prefer a left/right scalar logical shifts pair over a shift+and pair.
406 bool HasFastScalarShiftMasks = false;
408 /// Prefer a left/right vector logical shifts pair over a shift+and pair.
409 bool HasFastVectorShiftMasks = false;
411 /// Use a retpoline thunk rather than indirect calls to block speculative
412 /// execution.
413 bool UseRetpolineIndirectCalls = false;
415 /// Use a retpoline thunk or remove any indirect branch to block speculative
416 /// execution.
417 bool UseRetpolineIndirectBranches = false;
419 /// Deprecated flag, query `UseRetpolineIndirectCalls` and
420 /// `UseRetpolineIndirectBranches` instead.
421 bool DeprecatedUseRetpoline = false;
423 /// When using a retpoline thunk, call an externally provided thunk rather
424 /// than emitting one inside the compiler.
425 bool UseRetpolineExternalThunk = false;
427 /// Use software floating point for code generation.
428 bool UseSoftFloat = false;
430 /// The minimum alignment known to hold of the stack frame on
431 /// entry to the function and which must be maintained by every function.
432 unsigned stackAlignment = 4;
434 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
436 // FIXME: this is a known good value for Yonah. How about others?
437 unsigned MaxInlineSizeThreshold = 128;
439 /// Indicates target prefers 256 bit instructions.
440 bool Prefer256Bit = false;
442 /// Threeway branch is profitable in this subtarget.
443 bool ThreewayBranchProfitable = false;
445 /// What processor and OS we're targeting.
446 Triple TargetTriple;
448 /// GlobalISel related APIs.
449 std::unique_ptr<CallLowering> CallLoweringInfo;
450 std::unique_ptr<LegalizerInfo> Legalizer;
451 std::unique_ptr<RegisterBankInfo> RegBankInfo;
452 std::unique_ptr<InstructionSelector> InstSelector;
454 private:
455 /// Override the stack alignment.
456 unsigned StackAlignOverride;
458 /// Preferred vector width from function attribute.
459 unsigned PreferVectorWidthOverride;
461 /// Resolved preferred vector width from function attribute and subtarget
462 /// features.
463 unsigned PreferVectorWidth = UINT32_MAX;
465 /// Required vector width from function attribute.
466 unsigned RequiredVectorWidth;
468 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
469 bool In64BitMode;
471 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
472 bool In32BitMode;
474 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
475 bool In16BitMode;
477 /// Contains the Overhead of gather\scatter instructions
478 int GatherOverhead = 1024;
479 int ScatterOverhead = 1024;
481 X86SelectionDAGInfo TSInfo;
482 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
483 // X86TargetLowering needs.
484 X86InstrInfo InstrInfo;
485 X86TargetLowering TLInfo;
486 X86FrameLowering FrameLowering;
488 public:
489 /// This constructor initializes the data members to match that
490 /// of the specified triple.
492 X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
493 const X86TargetMachine &TM, unsigned StackAlignOverride,
494 unsigned PreferVectorWidthOverride,
495 unsigned RequiredVectorWidth);
497 const X86TargetLowering *getTargetLowering() const override {
498 return &TLInfo;
501 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
503 const X86FrameLowering *getFrameLowering() const override {
504 return &FrameLowering;
507 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
508 return &TSInfo;
511 const X86RegisterInfo *getRegisterInfo() const override {
512 return &getInstrInfo()->getRegisterInfo();
515 /// Returns the minimum alignment known to hold of the
516 /// stack frame on entry to the function and which must be maintained by every
517 /// function for this subtarget.
518 unsigned getStackAlignment() const { return stackAlignment; }
520 /// Returns the maximum memset / memcpy size
521 /// that still makes it profitable to inline the call.
522 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
524 /// ParseSubtargetFeatures - Parses features string setting specified
525 /// subtarget options. Definition of function is auto generated by tblgen.
526 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
528 /// Methods used by Global ISel
529 const CallLowering *getCallLowering() const override;
530 InstructionSelector *getInstructionSelector() const override;
531 const LegalizerInfo *getLegalizerInfo() const override;
532 const RegisterBankInfo *getRegBankInfo() const override;
534 private:
535 /// Initialize the full set of dependencies so we can use an initializer
536 /// list for X86Subtarget.
537 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
538 void initSubtargetFeatures(StringRef CPU, StringRef FS);
540 public:
541 /// Is this x86_64? (disregarding specific ABI / programming model)
542 bool is64Bit() const {
543 return In64BitMode;
546 bool is32Bit() const {
547 return In32BitMode;
550 bool is16Bit() const {
551 return In16BitMode;
554 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
555 bool isTarget64BitILP32() const {
556 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
557 TargetTriple.isOSNaCl());
560 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
561 bool isTarget64BitLP64() const {
562 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
563 !TargetTriple.isOSNaCl());
566 PICStyles::Style getPICStyle() const { return PICStyle; }
567 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
569 bool hasX87() const { return HasX87; }
570 bool hasCmpxchg8b() const { return HasCmpxchg8b; }
571 bool hasNOPL() const { return HasNOPL; }
572 // SSE codegen depends on cmovs, and all SSE1+ processors support them.
573 // All 64-bit processors support cmov.
574 bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
575 bool hasSSE1() const { return X86SSELevel >= SSE1; }
576 bool hasSSE2() const { return X86SSELevel >= SSE2; }
577 bool hasSSE3() const { return X86SSELevel >= SSE3; }
578 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
579 bool hasSSE41() const { return X86SSELevel >= SSE41; }
580 bool hasSSE42() const { return X86SSELevel >= SSE42; }
581 bool hasAVX() const { return X86SSELevel >= AVX; }
582 bool hasAVX2() const { return X86SSELevel >= AVX2; }
583 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
584 bool hasInt256() const { return hasAVX2(); }
585 bool hasSSE4A() const { return HasSSE4A; }
586 bool hasMMX() const { return X863DNowLevel >= MMX; }
587 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
588 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
589 bool hasPOPCNT() const { return HasPOPCNT; }
590 bool hasAES() const { return HasAES; }
591 bool hasVAES() const { return HasVAES; }
592 bool hasFXSR() const { return HasFXSR; }
593 bool hasXSAVE() const { return HasXSAVE; }
594 bool hasXSAVEOPT() const { return HasXSAVEOPT; }
595 bool hasXSAVEC() const { return HasXSAVEC; }
596 bool hasXSAVES() const { return HasXSAVES; }
597 bool hasPCLMUL() const { return HasPCLMUL; }
598 bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
599 bool hasGFNI() const { return HasGFNI; }
600 // Prefer FMA4 to FMA - its better for commutation/memory folding and
601 // has equal or better performance on all supported targets.
602 bool hasFMA() const { return HasFMA; }
603 bool hasFMA4() const { return HasFMA4; }
604 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
605 bool hasXOP() const { return HasXOP; }
606 bool hasTBM() const { return HasTBM; }
607 bool hasLWP() const { return HasLWP; }
608 bool hasMOVBE() const { return HasMOVBE; }
609 bool hasRDRAND() const { return HasRDRAND; }
610 bool hasF16C() const { return HasF16C; }
611 bool hasFSGSBase() const { return HasFSGSBase; }
612 bool hasLZCNT() const { return HasLZCNT; }
613 bool hasBMI() const { return HasBMI; }
614 bool hasBMI2() const { return HasBMI2; }
615 bool hasVBMI() const { return HasVBMI; }
616 bool hasVBMI2() const { return HasVBMI2; }
617 bool hasIFMA() const { return HasIFMA; }
618 bool hasRTM() const { return HasRTM; }
619 bool hasADX() const { return HasADX; }
620 bool hasSHA() const { return HasSHA; }
621 bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
622 bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
623 bool hasSSEPrefetch() const {
624 // We implicitly enable these when we have a write prefix supporting cache
625 // level OR if we have prfchw, but don't already have a read prefetch from
626 // 3dnow.
627 return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
629 bool hasRDSEED() const { return HasRDSEED; }
630 bool hasLAHFSAHF() const { return HasLAHFSAHF; }
631 bool hasMWAITX() const { return HasMWAITX; }
632 bool hasCLZERO() const { return HasCLZERO; }
633 bool hasCLDEMOTE() const { return HasCLDEMOTE; }
634 bool hasMOVDIRI() const { return HasMOVDIRI; }
635 bool hasMOVDIR64B() const { return HasMOVDIR64B; }
636 bool hasPTWRITE() const { return HasPTWRITE; }
637 bool isSHLDSlow() const { return IsSHLDSlow; }
638 bool isPMULLDSlow() const { return IsPMULLDSlow; }
639 bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
640 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
641 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
642 int getGatherOverhead() const { return GatherOverhead; }
643 int getScatterOverhead() const { return ScatterOverhead; }
644 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
645 bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); }
646 bool useLeaForSP() const { return UseLeaForSP; }
647 bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
648 bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
649 bool hasFastVariableShuffle() const {
650 return HasFastVariableShuffle;
652 bool hasFastPartialYMMorZMMWrite() const {
653 return HasFastPartialYMMorZMMWrite;
655 bool hasFastGather() const { return HasFastGather; }
656 bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
657 bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
658 bool hasFastLZCNT() const { return HasFastLZCNT; }
659 bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
660 bool hasFastBEXTR() const { return HasFastBEXTR; }
661 bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
662 bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
663 bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
664 bool hasMacroFusion() const { return HasMacroFusion; }
665 bool hasBranchFusion() const { return HasBranchFusion; }
666 bool hasERMSB() const { return HasERMSB; }
667 bool hasSlowDivide32() const { return HasSlowDivide32; }
668 bool hasSlowDivide64() const { return HasSlowDivide64; }
669 bool padShortFunctions() const { return PadShortFunctions; }
670 bool slowTwoMemOps() const { return SlowTwoMemOps; }
671 bool LEAusesAG() const { return LEAUsesAG; }
672 bool slowLEA() const { return SlowLEA; }
673 bool slow3OpsLEA() const { return Slow3OpsLEA; }
674 bool slowIncDec() const { return SlowIncDec; }
675 bool hasCDI() const { return HasCDI; }
676 bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
677 bool hasPFI() const { return HasPFI; }
678 bool hasERI() const { return HasERI; }
679 bool hasDQI() const { return HasDQI; }
680 bool hasBWI() const { return HasBWI; }
681 bool hasVLX() const { return HasVLX; }
682 bool hasPKU() const { return HasPKU; }
683 bool hasVNNI() const { return HasVNNI; }
684 bool hasBF16() const { return HasBF16; }
685 bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
686 bool hasBITALG() const { return HasBITALG; }
687 bool hasMPX() const { return HasMPX; }
688 bool hasSHSTK() const { return HasSHSTK; }
689 bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
690 bool hasCLWB() const { return HasCLWB; }
691 bool hasWBNOINVD() const { return HasWBNOINVD; }
692 bool hasRDPID() const { return HasRDPID; }
693 bool hasWAITPKG() const { return HasWAITPKG; }
694 bool hasPCONFIG() const { return HasPCONFIG; }
695 bool hasSGX() const { return HasSGX; }
696 bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
697 bool hasINVPCID() const { return HasINVPCID; }
698 bool hasENQCMD() const { return HasENQCMD; }
699 bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
700 bool useRetpolineIndirectBranches() const {
701 return UseRetpolineIndirectBranches;
703 bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
705 unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
706 unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
708 // Helper functions to determine when we should allow widening to 512-bit
709 // during codegen.
710 // TODO: Currently we're always allowing widening on CPUs without VLX,
711 // because for many cases we don't have a better option.
712 bool canExtendTo512DQ() const {
713 return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
715 bool canExtendTo512BW() const {
716 return hasBWI() && canExtendTo512DQ();
719 // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
720 // disable them in the legalizer.
721 bool useAVX512Regs() const {
722 return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
725 bool useBWIRegs() const {
726 return hasBWI() && useAVX512Regs();
729 bool isXRaySupported() const override { return is64Bit(); }
731 X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
733 /// TODO: to be removed later and replaced with suitable properties
734 bool isAtom() const { return X86ProcFamily == IntelAtom; }
735 bool isSLM() const { return X86ProcFamily == IntelSLM; }
736 bool isGLM() const {
737 return X86ProcFamily == IntelGLM ||
738 X86ProcFamily == IntelGLP ||
739 X86ProcFamily == IntelTRM;
741 bool useSoftFloat() const { return UseSoftFloat; }
743 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
744 /// no-sse2). There isn't any reason to disable it if the target processor
745 /// supports it.
746 bool hasMFence() const { return hasSSE2() || is64Bit(); }
748 const Triple &getTargetTriple() const { return TargetTriple; }
750 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
751 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
752 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
753 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
754 bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
756 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
757 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
758 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
760 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
761 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
762 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
763 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
764 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
765 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
766 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
767 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
768 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
770 bool isTargetWindowsMSVC() const {
771 return TargetTriple.isWindowsMSVCEnvironment();
774 bool isTargetWindowsCoreCLR() const {
775 return TargetTriple.isWindowsCoreCLREnvironment();
778 bool isTargetWindowsCygwin() const {
779 return TargetTriple.isWindowsCygwinEnvironment();
782 bool isTargetWindowsGNU() const {
783 return TargetTriple.isWindowsGNUEnvironment();
786 bool isTargetWindowsItanium() const {
787 return TargetTriple.isWindowsItaniumEnvironment();
790 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
792 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
794 bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
796 bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
798 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
799 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
801 bool isPICStyleStubPIC() const {
802 return PICStyle == PICStyles::StubPIC;
805 bool isPositionIndependent() const { return TM.isPositionIndependent(); }
807 bool isCallingConvWin64(CallingConv::ID CC) const {
808 switch (CC) {
809 // On Win64, all these conventions just use the default convention.
810 case CallingConv::C:
811 case CallingConv::Fast:
812 case CallingConv::Swift:
813 case CallingConv::X86_FastCall:
814 case CallingConv::X86_StdCall:
815 case CallingConv::X86_ThisCall:
816 case CallingConv::X86_VectorCall:
817 case CallingConv::Intel_OCL_BI:
818 return isTargetWin64();
819 // This convention allows using the Win64 convention on other targets.
820 case CallingConv::Win64:
821 return true;
822 // This convention allows using the SysV convention on Windows targets.
823 case CallingConv::X86_64_SysV:
824 return false;
825 // Otherwise, who knows what this is.
826 default:
827 return false;
831 /// Classify a global variable reference for the current subtarget according
832 /// to how we should reference it in a non-pcrel context.
833 unsigned char classifyLocalReference(const GlobalValue *GV) const;
835 unsigned char classifyGlobalReference(const GlobalValue *GV,
836 const Module &M) const;
837 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
839 /// Classify a global function reference for the current subtarget.
840 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
841 const Module &M) const;
842 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
844 /// Classify a blockaddress reference for the current subtarget according to
845 /// how we should reference it in a non-pcrel context.
846 unsigned char classifyBlockAddressReference() const;
848 /// Return true if the subtarget allows calls to immediate address.
849 bool isLegalToCallImmediateAddr() const;
851 /// If we are using retpolines, we need to expand indirectbr to avoid it
852 /// lowering to an actual indirect jump.
853 bool enableIndirectBrExpand() const override {
854 return useRetpolineIndirectBranches();
857 /// Enable the MachineScheduler pass for all X86 subtargets.
858 bool enableMachineScheduler() const override { return true; }
860 bool enableEarlyIfConversion() const override;
862 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
863 &Mutations) const override;
865 AntiDepBreakMode getAntiDepBreakMode() const override {
866 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
869 bool enableAdvancedRASplitCost() const override { return true; }
872 } // end namespace llvm
874 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H