[llvm-exegesis] Implements a cache of Instruction objects.
[llvm-core.git] / tools / llvm-mca / Views / TimelineView.h
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1 //===--------------------- TimelineView.h -----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \brief
10 ///
11 /// This file implements a timeline view for the llvm-mca tool.
12 ///
13 /// Class TimelineView observes events generated by the pipeline. For every
14 /// instruction executed by the pipeline, it stores information related to
15 /// state transition. It then plots that information in the form of a table
16 /// as reported by the example below:
17 ///
18 /// Timeline view:
19 /// 0123456
20 /// Index 0123456789
21 ///
22 /// [0,0] DeER . . .. vmovshdup %xmm0, %xmm1
23 /// [0,1] DeER . . .. vpermilpd $1, %xmm0, %xmm2
24 /// [0,2] .DeER. . .. vpermilps $231, %xmm0, %xmm5
25 /// [0,3] .DeeeER . .. vaddss %xmm1, %xmm0, %xmm3
26 /// [0,4] . D==eeeER. .. vaddss %xmm3, %xmm2, %xmm4
27 /// [0,5] . D=====eeeER .. vaddss %xmm4, %xmm5, %xmm6
28 ///
29 /// [1,0] . DeE------R .. vmovshdup %xmm0, %xmm1
30 /// [1,1] . DeE------R .. vpermilpd $1, %xmm0, %xmm2
31 /// [1,2] . DeE-----R .. vpermilps $231, %xmm0, %xmm5
32 /// [1,3] . D=eeeE--R .. vaddss %xmm1, %xmm0, %xmm3
33 /// [1,4] . D===eeeER .. vaddss %xmm3, %xmm2, %xmm4
34 /// [1,5] . D======eeeER vaddss %xmm4, %xmm5, %xmm6
35 ///
36 /// There is an entry for every instruction in the input assembly sequence.
37 /// The first field is a pair of numbers obtained from the instruction index.
38 /// The first element of the pair is the iteration index, while the second
39 /// element of the pair is a sequence number (i.e. a position in the assembly
40 /// sequence).
41 /// The second field of the table is the actual timeline information; each
42 /// column is the information related to a specific cycle of execution.
43 /// The timeline of an instruction is described by a sequence of character
44 /// where each character represents the instruction state at a specific cycle.
45 ///
46 /// Possible instruction states are:
47 /// D: Instruction Dispatched
48 /// e: Instruction Executing
49 /// E: Instruction Executed (write-back stage)
50 /// R: Instruction retired
51 /// =: Instruction waiting in the Scheduler's queue
52 /// -: Instruction executed, waiting to retire in order.
53 ///
54 /// dots ('.') and empty spaces are cycles where the instruction is not
55 /// in-flight.
56 ///
57 /// The last column is the assembly instruction associated to the entry.
58 ///
59 /// Based on the timeline view information from the example, instruction 0
60 /// at iteration 0 was dispatched at cycle 0, and was retired at cycle 3.
61 /// Instruction [0,1] was also dispatched at cycle 0, and it retired at
62 /// the same cycle than instruction [0,0].
63 /// Instruction [0,4] has been dispatched at cycle 2. However, it had to
64 /// wait for two cycles before being issued. That is because operands
65 /// became ready only at cycle 5.
66 ///
67 /// This view helps further understanding bottlenecks and the impact of
68 /// resource pressure on the code.
69 ///
70 /// To better understand why instructions had to wait for multiple cycles in
71 /// the scheduler's queue, class TimelineView also reports extra timing info
72 /// in another table named "Average Wait times" (see example below).
73 ///
74 ///
75 /// Average Wait times (based on the timeline view):
76 /// [0]: Executions
77 /// [1]: Average time spent waiting in a scheduler's queue
78 /// [2]: Average time spent waiting in a scheduler's queue while ready
79 /// [3]: Average time elapsed from WB until retire stage
80 ///
81 /// [0] [1] [2] [3]
82 /// 0. 2 1.0 1.0 3.0 vmovshdup %xmm0, %xmm1
83 /// 1. 2 1.0 1.0 3.0 vpermilpd $1, %xmm0, %xmm2
84 /// 2. 2 1.0 1.0 2.5 vpermilps $231, %xmm0, %xmm5
85 /// 3. 2 1.5 0.5 1.0 vaddss %xmm1, %xmm0, %xmm3
86 /// 4. 2 3.5 0.0 0.0 vaddss %xmm3, %xmm2, %xmm4
87 /// 5. 2 6.5 0.0 0.0 vaddss %xmm4, %xmm5, %xmm6
88 ///
89 /// By comparing column [2] with column [1], we get an idea about how many
90 /// cycles were spent in the scheduler's queue due to data dependencies.
91 ///
92 /// In this example, instruction 5 spent an average of ~6 cycles in the
93 /// scheduler's queue. As soon as operands became ready, the instruction
94 /// was immediately issued to the pipeline(s).
95 /// That is expected because instruction 5 cannot transition to the "ready"
96 /// state until %xmm4 is written by instruction 4.
97 ///
98 //===----------------------------------------------------------------------===//
100 #ifndef LLVM_TOOLS_LLVM_MCA_TIMELINEVIEW_H
101 #define LLVM_TOOLS_LLVM_MCA_TIMELINEVIEW_H
103 #include "SourceMgr.h"
104 #include "Views/View.h"
105 #include "llvm/MC/MCInstPrinter.h"
106 #include "llvm/MC/MCSubtargetInfo.h"
107 #include "llvm/Support/FormattedStream.h"
108 #include "llvm/Support/raw_ostream.h"
110 namespace mca {
112 /// This class listens to instruction state transition events
113 /// in order to construct a timeline information.
115 /// For every instruction executed by the Pipeline, this class constructs
116 /// a TimelineViewEntry object. TimelineViewEntry objects are then used
117 /// to print the timeline information, as well as the "average wait times"
118 /// for every instruction in the input assembly sequence.
119 class TimelineView : public View {
120 const llvm::MCSubtargetInfo &STI;
121 llvm::MCInstPrinter &MCIP;
122 const SourceMgr &AsmSequence;
124 unsigned CurrentCycle;
125 unsigned MaxCycle;
126 unsigned LastCycle;
128 struct TimelineViewEntry {
129 int CycleDispatched; // A negative value is an "invalid cycle".
130 unsigned CycleReady;
131 unsigned CycleIssued;
132 unsigned CycleExecuted;
133 unsigned CycleRetired;
135 std::vector<TimelineViewEntry> Timeline;
137 struct WaitTimeEntry {
138 unsigned CyclesSpentInSchedulerQueue;
139 unsigned CyclesSpentInSQWhileReady;
140 unsigned CyclesSpentAfterWBAndBeforeRetire;
142 std::vector<WaitTimeEntry> WaitTime;
144 // This field is used to map instructions to buffered resources.
145 // Elements of this vector are <resourceID, BufferSizer> pairs.
146 std::vector<std::pair<unsigned, int>> UsedBuffer;
148 void printTimelineViewEntry(llvm::formatted_raw_ostream &OS,
149 const TimelineViewEntry &E, unsigned Iteration,
150 unsigned SourceIndex) const;
151 void printWaitTimeEntry(llvm::formatted_raw_ostream &OS,
152 const WaitTimeEntry &E, unsigned Index,
153 unsigned Executions) const;
155 const unsigned DEFAULT_ITERATIONS = 10;
157 // Display characters for the TimelineView report output.
158 struct DisplayChar {
159 static const char Dispatched = 'D';
160 static const char Executed = 'E';
161 static const char Retired = 'R';
162 static const char Waiting = '='; // Instruction is waiting in the scheduler.
163 static const char Executing = 'e';
164 static const char RetireLag = '-'; // The instruction is waiting to retire.
167 public:
168 TimelineView(const llvm::MCSubtargetInfo &sti, llvm::MCInstPrinter &Printer,
169 const SourceMgr &Sequence, unsigned MaxIterations,
170 unsigned Cycles);
172 // Event handlers.
173 void onCycleEnd() override { ++CurrentCycle; }
174 void onEvent(const HWInstructionEvent &Event) override;
175 void onReservedBuffers(const InstRef &IR,
176 llvm::ArrayRef<unsigned> Buffers) override;
178 // print functionalities.
179 void printTimeline(llvm::raw_ostream &OS) const;
180 void printAverageWaitTimes(llvm::raw_ostream &OS) const;
181 void printView(llvm::raw_ostream &OS) const override {
182 printTimeline(OS);
183 printAverageWaitTimes(OS);
186 } // namespace mca
188 #endif