| blob | ad7af93fce2f999def6ad5a094653a3fd46ecabf |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
6 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
7 ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
9 ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
11 define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
12 ; RV32I-LABEL: fold_srem_vec_1:
13 ; RV32I: # %bb.0:
14 ; RV32I-NEXT: addi sp, sp, -32
15 ; RV32I-NEXT: .cfi_def_cfa_offset 32
16 ; RV32I-NEXT: sw ra, 28(sp)
17 ; RV32I-NEXT: sw s0, 24(sp)
18 ; RV32I-NEXT: sw s1, 20(sp)
19 ; RV32I-NEXT: sw s2, 16(sp)
20 ; RV32I-NEXT: sw s3, 12(sp)
21 ; RV32I-NEXT: sw s4, 8(sp)
22 ; RV32I-NEXT: sw s5, 4(sp)
23 ; RV32I-NEXT: .cfi_offset ra, -4
24 ; RV32I-NEXT: .cfi_offset s0, -8
25 ; RV32I-NEXT: .cfi_offset s1, -12
26 ; RV32I-NEXT: .cfi_offset s2, -16
27 ; RV32I-NEXT: .cfi_offset s3, -20
28 ; RV32I-NEXT: .cfi_offset s4, -24
29 ; RV32I-NEXT: .cfi_offset s5, -28
30 ; RV32I-NEXT: lh s2, 12(a1)
31 ; RV32I-NEXT: lh s3, 8(a1)
32 ; RV32I-NEXT: lh s0, 4(a1)
33 ; RV32I-NEXT: lh a2, 0(a1)
34 ; RV32I-NEXT: mv s1, a0
35 ; RV32I-NEXT: addi a1, zero, 95
36 ; RV32I-NEXT: mv a0, a2
37 ; RV32I-NEXT: call __modsi3
38 ; RV32I-NEXT: mv s4, a0
39 ; RV32I-NEXT: addi a1, zero, -124
40 ; RV32I-NEXT: mv a0, s0
41 ; RV32I-NEXT: call __modsi3
42 ; RV32I-NEXT: mv s5, a0
43 ; RV32I-NEXT: addi a1, zero, 98
44 ; RV32I-NEXT: mv a0, s3
45 ; RV32I-NEXT: call __modsi3
46 ; RV32I-NEXT: mv s0, a0
47 ; RV32I-NEXT: addi a1, zero, -1003
48 ; RV32I-NEXT: mv a0, s2
49 ; RV32I-NEXT: call __modsi3
50 ; RV32I-NEXT: sh a0, 6(s1)
51 ; RV32I-NEXT: sh s0, 4(s1)
52 ; RV32I-NEXT: sh s5, 2(s1)
53 ; RV32I-NEXT: sh s4, 0(s1)
54 ; RV32I-NEXT: lw s5, 4(sp)
55 ; RV32I-NEXT: lw s4, 8(sp)
56 ; RV32I-NEXT: lw s3, 12(sp)
57 ; RV32I-NEXT: lw s2, 16(sp)
58 ; RV32I-NEXT: lw s1, 20(sp)
59 ; RV32I-NEXT: lw s0, 24(sp)
60 ; RV32I-NEXT: lw ra, 28(sp)
61 ; RV32I-NEXT: .cfi_restore ra
62 ; RV32I-NEXT: .cfi_restore s0
63 ; RV32I-NEXT: .cfi_restore s1
64 ; RV32I-NEXT: .cfi_restore s2
65 ; RV32I-NEXT: .cfi_restore s3
66 ; RV32I-NEXT: .cfi_restore s4
67 ; RV32I-NEXT: .cfi_restore s5
68 ; RV32I-NEXT: addi sp, sp, 32
69 ; RV32I-NEXT: .cfi_def_cfa_offset 0
70 ; RV32I-NEXT: ret
71 ;
72 ; RV32IM-LABEL: fold_srem_vec_1:
73 ; RV32IM: # %bb.0:
74 ; RV32IM-NEXT: lh a6, 12(a1)
75 ; RV32IM-NEXT: lh a3, 8(a1)
76 ; RV32IM-NEXT: lh a4, 0(a1)
77 ; RV32IM-NEXT: lh a1, 4(a1)
78 ; RV32IM-NEXT: lui a5, 706409
79 ; RV32IM-NEXT: addi a5, a5, 389
80 ; RV32IM-NEXT: mulh a5, a4, a5
81 ; RV32IM-NEXT: add a5, a5, a4
82 ; RV32IM-NEXT: srli a2, a5, 31
83 ; RV32IM-NEXT: srli a5, a5, 6
84 ; RV32IM-NEXT: add a2, a5, a2
85 ; RV32IM-NEXT: addi a5, zero, 95
86 ; RV32IM-NEXT: mul a2, a2, a5
87 ; RV32IM-NEXT: sub a2, a4, a2
88 ; RV32IM-NEXT: lui a4, 507375
89 ; RV32IM-NEXT: addi a4, a4, 1981
90 ; RV32IM-NEXT: mulh a4, a1, a4
91 ; RV32IM-NEXT: sub a4, a4, a1
92 ; RV32IM-NEXT: srli a5, a4, 31
93 ; RV32IM-NEXT: srli a4, a4, 6
94 ; RV32IM-NEXT: add a4, a4, a5
95 ; RV32IM-NEXT: addi a5, zero, -124
96 ; RV32IM-NEXT: mul a4, a4, a5
97 ; RV32IM-NEXT: sub a1, a1, a4
98 ; RV32IM-NEXT: lui a4, 342392
99 ; RV32IM-NEXT: addi a4, a4, 669
100 ; RV32IM-NEXT: mulh a4, a3, a4
101 ; RV32IM-NEXT: srli a5, a4, 31
102 ; RV32IM-NEXT: srli a4, a4, 5
103 ; RV32IM-NEXT: add a4, a4, a5
104 ; RV32IM-NEXT: addi a5, zero, 98
105 ; RV32IM-NEXT: mul a4, a4, a5
106 ; RV32IM-NEXT: sub a3, a3, a4
107 ; RV32IM-NEXT: lui a4, 780943
108 ; RV32IM-NEXT: addi a4, a4, 1809
109 ; RV32IM-NEXT: mulh a4, a6, a4
110 ; RV32IM-NEXT: srli a5, a4, 31
111 ; RV32IM-NEXT: srli a4, a4, 8
112 ; RV32IM-NEXT: add a4, a4, a5
113 ; RV32IM-NEXT: addi a5, zero, -1003
114 ; RV32IM-NEXT: mul a4, a4, a5
115 ; RV32IM-NEXT: sub a4, a6, a4
116 ; RV32IM-NEXT: sh a4, 6(a0)
117 ; RV32IM-NEXT: sh a3, 4(a0)
118 ; RV32IM-NEXT: sh a1, 2(a0)
119 ; RV32IM-NEXT: sh a2, 0(a0)
120 ; RV32IM-NEXT: .cfi_def_cfa_offset 0
121 ; RV32IM-NEXT: ret
122 ;
123 ; RV64I-LABEL: fold_srem_vec_1:
124 ; RV64I: # %bb.0:
125 ; RV64I-NEXT: addi sp, sp, -64
126 ; RV64I-NEXT: .cfi_def_cfa_offset 64
127 ; RV64I-NEXT: sd ra, 56(sp)
128 ; RV64I-NEXT: sd s0, 48(sp)
129 ; RV64I-NEXT: sd s1, 40(sp)
130 ; RV64I-NEXT: sd s2, 32(sp)
131 ; RV64I-NEXT: sd s3, 24(sp)
132 ; RV64I-NEXT: sd s4, 16(sp)
133 ; RV64I-NEXT: sd s5, 8(sp)
134 ; RV64I-NEXT: .cfi_offset ra, -8
135 ; RV64I-NEXT: .cfi_offset s0, -16
136 ; RV64I-NEXT: .cfi_offset s1, -24
137 ; RV64I-NEXT: .cfi_offset s2, -32
138 ; RV64I-NEXT: .cfi_offset s3, -40
139 ; RV64I-NEXT: .cfi_offset s4, -48
140 ; RV64I-NEXT: .cfi_offset s5, -56
141 ; RV64I-NEXT: lh s2, 24(a1)
142 ; RV64I-NEXT: lh s3, 16(a1)
143 ; RV64I-NEXT: lh s0, 8(a1)
144 ; RV64I-NEXT: lh a2, 0(a1)
145 ; RV64I-NEXT: mv s1, a0
146 ; RV64I-NEXT: addi a1, zero, 95
147 ; RV64I-NEXT: mv a0, a2
148 ; RV64I-NEXT: call __moddi3
149 ; RV64I-NEXT: mv s4, a0
150 ; RV64I-NEXT: addi a1, zero, -124
151 ; RV64I-NEXT: mv a0, s0
152 ; RV64I-NEXT: call __moddi3
153 ; RV64I-NEXT: mv s5, a0
154 ; RV64I-NEXT: addi a1, zero, 98
155 ; RV64I-NEXT: mv a0, s3
156 ; RV64I-NEXT: call __moddi3
157 ; RV64I-NEXT: mv s0, a0
158 ; RV64I-NEXT: addi a1, zero, -1003
159 ; RV64I-NEXT: mv a0, s2
160 ; RV64I-NEXT: call __moddi3
161 ; RV64I-NEXT: sh a0, 6(s1)
162 ; RV64I-NEXT: sh s0, 4(s1)
163 ; RV64I-NEXT: sh s5, 2(s1)
164 ; RV64I-NEXT: sh s4, 0(s1)
165 ; RV64I-NEXT: ld s5, 8(sp)
166 ; RV64I-NEXT: ld s4, 16(sp)
167 ; RV64I-NEXT: ld s3, 24(sp)
168 ; RV64I-NEXT: ld s2, 32(sp)
169 ; RV64I-NEXT: ld s1, 40(sp)
170 ; RV64I-NEXT: ld s0, 48(sp)
171 ; RV64I-NEXT: ld ra, 56(sp)
172 ; RV64I-NEXT: .cfi_restore ra
173 ; RV64I-NEXT: .cfi_restore s0
174 ; RV64I-NEXT: .cfi_restore s1
175 ; RV64I-NEXT: .cfi_restore s2
176 ; RV64I-NEXT: .cfi_restore s3
177 ; RV64I-NEXT: .cfi_restore s4
178 ; RV64I-NEXT: .cfi_restore s5
179 ; RV64I-NEXT: addi sp, sp, 64
180 ; RV64I-NEXT: .cfi_def_cfa_offset 0
181 ; RV64I-NEXT: ret
182 ;
183 ; RV64IM-LABEL: fold_srem_vec_1:
184 ; RV64IM: # %bb.0:
185 ; RV64IM-NEXT: lh a6, 24(a1)
186 ; RV64IM-NEXT: lh a3, 16(a1)
187 ; RV64IM-NEXT: lh a4, 8(a1)
188 ; RV64IM-NEXT: lh a1, 0(a1)
189 ; RV64IM-NEXT: lui a5, 1045903
190 ; RV64IM-NEXT: addiw a5, a5, -733
191 ; RV64IM-NEXT: slli a5, a5, 15
192 ; RV64IM-NEXT: addi a5, a5, 1035
193 ; RV64IM-NEXT: slli a5, a5, 12
194 ; RV64IM-NEXT: addi a5, a5, -905
195 ; RV64IM-NEXT: slli a5, a5, 12
196 ; RV64IM-NEXT: addi a5, a5, -1767
197 ; RV64IM-NEXT: mulh a5, a1, a5
198 ; RV64IM-NEXT: add a5, a5, a1
199 ; RV64IM-NEXT: srli a2, a5, 63
200 ; RV64IM-NEXT: srli a5, a5, 6
201 ; RV64IM-NEXT: add a2, a5, a2
202 ; RV64IM-NEXT: addi a5, zero, 95
203 ; RV64IM-NEXT: mul a2, a2, a5
204 ; RV64IM-NEXT: sub a1, a1, a2
205 ; RV64IM-NEXT: lui a2, 248
206 ; RV64IM-NEXT: addiw a2, a2, -1057
207 ; RV64IM-NEXT: slli a2, a2, 15
208 ; RV64IM-NEXT: addi a2, a2, -1057
209 ; RV64IM-NEXT: slli a2, a2, 15
210 ; RV64IM-NEXT: addi a2, a2, -1057
211 ; RV64IM-NEXT: slli a2, a2, 13
212 ; RV64IM-NEXT: addi a2, a2, -265
213 ; RV64IM-NEXT: mulh a2, a4, a2
214 ; RV64IM-NEXT: sub a2, a2, a4
215 ; RV64IM-NEXT: srli a5, a2, 63
216 ; RV64IM-NEXT: srli a2, a2, 6
217 ; RV64IM-NEXT: add a2, a2, a5
218 ; RV64IM-NEXT: addi a5, zero, -124
219 ; RV64IM-NEXT: mul a2, a2, a5
220 ; RV64IM-NEXT: sub a2, a4, a2
221 ; RV64IM-NEXT: lui a4, 2675
222 ; RV64IM-NEXT: addiw a4, a4, -251
223 ; RV64IM-NEXT: slli a4, a4, 13
224 ; RV64IM-NEXT: addi a4, a4, 1839
225 ; RV64IM-NEXT: slli a4, a4, 13
226 ; RV64IM-NEXT: addi a4, a4, 167
227 ; RV64IM-NEXT: slli a4, a4, 13
228 ; RV64IM-NEXT: addi a4, a4, 1505
229 ; RV64IM-NEXT: mulh a4, a3, a4
230 ; RV64IM-NEXT: srli a5, a4, 63
231 ; RV64IM-NEXT: srli a4, a4, 5
232 ; RV64IM-NEXT: add a4, a4, a5
233 ; RV64IM-NEXT: addi a5, zero, 98
234 ; RV64IM-NEXT: mul a4, a4, a5
235 ; RV64IM-NEXT: sub a3, a3, a4
236 ; RV64IM-NEXT: lui a4, 1040212
237 ; RV64IM-NEXT: addiw a4, a4, 1977
238 ; RV64IM-NEXT: slli a4, a4, 12
239 ; RV64IM-NEXT: addi a4, a4, -1907
240 ; RV64IM-NEXT: slli a4, a4, 12
241 ; RV64IM-NEXT: addi a4, a4, -453
242 ; RV64IM-NEXT: slli a4, a4, 12
243 ; RV64IM-NEXT: addi a4, a4, -1213
244 ; RV64IM-NEXT: mulh a4, a6, a4
245 ; RV64IM-NEXT: srli a5, a4, 63
246 ; RV64IM-NEXT: srli a4, a4, 7
247 ; RV64IM-NEXT: add a4, a4, a5
248 ; RV64IM-NEXT: addi a5, zero, -1003
249 ; RV64IM-NEXT: mul a4, a4, a5
250 ; RV64IM-NEXT: sub a4, a6, a4
251 ; RV64IM-NEXT: sh a4, 6(a0)
252 ; RV64IM-NEXT: sh a3, 4(a0)
253 ; RV64IM-NEXT: sh a2, 2(a0)
254 ; RV64IM-NEXT: sh a1, 0(a0)
255 ; RV64IM-NEXT: .cfi_def_cfa_offset 0
256 ; RV64IM-NEXT: ret
257 %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
258 ret <4 x i16> %1
259 }
261 define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
262 ; RV32I-LABEL: fold_srem_vec_2:
263 ; RV32I: # %bb.0:
264 ; RV32I-NEXT: addi sp, sp, -32
265 ; RV32I-NEXT: .cfi_def_cfa_offset 32
266 ; RV32I-NEXT: sw ra, 28(sp)
267 ; RV32I-NEXT: sw s0, 24(sp)
268 ; RV32I-NEXT: sw s1, 20(sp)
269 ; RV32I-NEXT: sw s2, 16(sp)
270 ; RV32I-NEXT: sw s3, 12(sp)
271 ; RV32I-NEXT: sw s4, 8(sp)
272 ; RV32I-NEXT: sw s5, 4(sp)
273 ; RV32I-NEXT: .cfi_offset ra, -4
274 ; RV32I-NEXT: .cfi_offset s0, -8
275 ; RV32I-NEXT: .cfi_offset s1, -12
276 ; RV32I-NEXT: .cfi_offset s2, -16
277 ; RV32I-NEXT: .cfi_offset s3, -20
278 ; RV32I-NEXT: .cfi_offset s4, -24
279 ; RV32I-NEXT: .cfi_offset s5, -28
280 ; RV32I-NEXT: lh s2, 12(a1)
281 ; RV32I-NEXT: lh s3, 8(a1)
282 ; RV32I-NEXT: lh s0, 4(a1)
283 ; RV32I-NEXT: lh a2, 0(a1)
284 ; RV32I-NEXT: mv s1, a0
285 ; RV32I-NEXT: addi a1, zero, 95
286 ; RV32I-NEXT: mv a0, a2
287 ; RV32I-NEXT: call __modsi3
288 ; RV32I-NEXT: mv s4, a0
289 ; RV32I-NEXT: addi a1, zero, 95
290 ; RV32I-NEXT: mv a0, s0
291 ; RV32I-NEXT: call __modsi3
292 ; RV32I-NEXT: mv s5, a0
293 ; RV32I-NEXT: addi a1, zero, 95
294 ; RV32I-NEXT: mv a0, s3
295 ; RV32I-NEXT: call __modsi3
296 ; RV32I-NEXT: mv s0, a0
297 ; RV32I-NEXT: addi a1, zero, 95
298 ; RV32I-NEXT: mv a0, s2
299 ; RV32I-NEXT: call __modsi3
300 ; RV32I-NEXT: sh a0, 6(s1)
301 ; RV32I-NEXT: sh s0, 4(s1)
302 ; RV32I-NEXT: sh s5, 2(s1)
303 ; RV32I-NEXT: sh s4, 0(s1)
304 ; RV32I-NEXT: lw s5, 4(sp)
305 ; RV32I-NEXT: lw s4, 8(sp)
306 ; RV32I-NEXT: lw s3, 12(sp)
307 ; RV32I-NEXT: lw s2, 16(sp)
308 ; RV32I-NEXT: lw s1, 20(sp)
309 ; RV32I-NEXT: lw s0, 24(sp)
310 ; RV32I-NEXT: lw ra, 28(sp)
311 ; RV32I-NEXT: .cfi_restore ra
312 ; RV32I-NEXT: .cfi_restore s0
313 ; RV32I-NEXT: .cfi_restore s1
314 ; RV32I-NEXT: .cfi_restore s2
315 ; RV32I-NEXT: .cfi_restore s3
316 ; RV32I-NEXT: .cfi_restore s4
317 ; RV32I-NEXT: .cfi_restore s5
318 ; RV32I-NEXT: addi sp, sp, 32
319 ; RV32I-NEXT: .cfi_def_cfa_offset 0
320 ; RV32I-NEXT: ret
321 ;
322 ; RV32IM-LABEL: fold_srem_vec_2:
323 ; RV32IM: # %bb.0:
324 ; RV32IM-NEXT: lh a6, 12(a1)
325 ; RV32IM-NEXT: lh a3, 8(a1)
326 ; RV32IM-NEXT: lh a4, 0(a1)
327 ; RV32IM-NEXT: lh a1, 4(a1)
328 ; RV32IM-NEXT: lui a5, 706409
329 ; RV32IM-NEXT: addi a5, a5, 389
330 ; RV32IM-NEXT: mulh a2, a4, a5
331 ; RV32IM-NEXT: add a2, a2, a4
332 ; RV32IM-NEXT: srli a7, a2, 31
333 ; RV32IM-NEXT: srli a2, a2, 6
334 ; RV32IM-NEXT: add a2, a2, a7
335 ; RV32IM-NEXT: addi a7, zero, 95
336 ; RV32IM-NEXT: mul a2, a2, a7
337 ; RV32IM-NEXT: sub t0, a4, a2
338 ; RV32IM-NEXT: mulh a4, a1, a5
339 ; RV32IM-NEXT: add a4, a4, a1
340 ; RV32IM-NEXT: srli a2, a4, 31
341 ; RV32IM-NEXT: srli a4, a4, 6
342 ; RV32IM-NEXT: add a2, a4, a2
343 ; RV32IM-NEXT: mul a2, a2, a7
344 ; RV32IM-NEXT: sub a1, a1, a2
345 ; RV32IM-NEXT: mulh a2, a3, a5
346 ; RV32IM-NEXT: add a2, a2, a3
347 ; RV32IM-NEXT: srli a4, a2, 31
348 ; RV32IM-NEXT: srli a2, a2, 6
349 ; RV32IM-NEXT: add a2, a2, a4
350 ; RV32IM-NEXT: mul a2, a2, a7
351 ; RV32IM-NEXT: sub a2, a3, a2
352 ; RV32IM-NEXT: mulh a3, a6, a5
353 ; RV32IM-NEXT: add a3, a3, a6
354 ; RV32IM-NEXT: srli a4, a3, 31
355 ; RV32IM-NEXT: srli a3, a3, 6
356 ; RV32IM-NEXT: add a3, a3, a4
357 ; RV32IM-NEXT: mul a3, a3, a7
358 ; RV32IM-NEXT: sub a3, a6, a3
359 ; RV32IM-NEXT: sh a3, 6(a0)
360 ; RV32IM-NEXT: sh a2, 4(a0)
361 ; RV32IM-NEXT: sh a1, 2(a0)
362 ; RV32IM-NEXT: sh t0, 0(a0)
363 ; RV32IM-NEXT: .cfi_def_cfa_offset 0
364 ; RV32IM-NEXT: ret
365 ;
366 ; RV64I-LABEL: fold_srem_vec_2:
367 ; RV64I: # %bb.0:
368 ; RV64I-NEXT: addi sp, sp, -64
369 ; RV64I-NEXT: .cfi_def_cfa_offset 64
370 ; RV64I-NEXT: sd ra, 56(sp)
371 ; RV64I-NEXT: sd s0, 48(sp)
372 ; RV64I-NEXT: sd s1, 40(sp)
373 ; RV64I-NEXT: sd s2, 32(sp)
374 ; RV64I-NEXT: sd s3, 24(sp)
375 ; RV64I-NEXT: sd s4, 16(sp)
376 ; RV64I-NEXT: sd s5, 8(sp)
377 ; RV64I-NEXT: .cfi_offset ra, -8
378 ; RV64I-NEXT: .cfi_offset s0, -16
379 ; RV64I-NEXT: .cfi_offset s1, -24
380 ; RV64I-NEXT: .cfi_offset s2, -32
381 ; RV64I-NEXT: .cfi_offset s3, -40
382 ; RV64I-NEXT: .cfi_offset s4, -48
383 ; RV64I-NEXT: .cfi_offset s5, -56
384 ; RV64I-NEXT: lh s2, 24(a1)
385 ; RV64I-NEXT: lh s3, 16(a1)
386 ; RV64I-NEXT: lh s0, 8(a1)
387 ; RV64I-NEXT: lh a2, 0(a1)
388 ; RV64I-NEXT: mv s1, a0
389 ; RV64I-NEXT: addi a1, zero, 95
390 ; RV64I-NEXT: mv a0, a2
391 ; RV64I-NEXT: call __moddi3
392 ; RV64I-NEXT: mv s4, a0
393 ; RV64I-NEXT: addi a1, zero, 95
394 ; RV64I-NEXT: mv a0, s0
395 ; RV64I-NEXT: call __moddi3
396 ; RV64I-NEXT: mv s5, a0
397 ; RV64I-NEXT: addi a1, zero, 95
398 ; RV64I-NEXT: mv a0, s3
399 ; RV64I-NEXT: call __moddi3
400 ; RV64I-NEXT: mv s0, a0
401 ; RV64I-NEXT: addi a1, zero, 95
402 ; RV64I-NEXT: mv a0, s2
403 ; RV64I-NEXT: call __moddi3
404 ; RV64I-NEXT: sh a0, 6(s1)
405 ; RV64I-NEXT: sh s0, 4(s1)
406 ; RV64I-NEXT: sh s5, 2(s1)
407 ; RV64I-NEXT: sh s4, 0(s1)
408 ; RV64I-NEXT: ld s5, 8(sp)
409 ; RV64I-NEXT: ld s4, 16(sp)
410 ; RV64I-NEXT: ld s3, 24(sp)
411 ; RV64I-NEXT: ld s2, 32(sp)
412 ; RV64I-NEXT: ld s1, 40(sp)
413 ; RV64I-NEXT: ld s0, 48(sp)
414 ; RV64I-NEXT: ld ra, 56(sp)
415 ; RV64I-NEXT: .cfi_restore ra
416 ; RV64I-NEXT: .cfi_restore s0
417 ; RV64I-NEXT: .cfi_restore s1
418 ; RV64I-NEXT: .cfi_restore s2
419 ; RV64I-NEXT: .cfi_restore s3
420 ; RV64I-NEXT: .cfi_restore s4
421 ; RV64I-NEXT: .cfi_restore s5
422 ; RV64I-NEXT: addi sp, sp, 64
423 ; RV64I-NEXT: .cfi_def_cfa_offset 0
424 ; RV64I-NEXT: ret
425 ;
426 ; RV64IM-LABEL: fold_srem_vec_2:
427 ; RV64IM: # %bb.0:
428 ; RV64IM-NEXT: lh a6, 24(a1)
429 ; RV64IM-NEXT: lh a7, 16(a1)
430 ; RV64IM-NEXT: lh a4, 8(a1)
431 ; RV64IM-NEXT: lh a1, 0(a1)
432 ; RV64IM-NEXT: lui a5, 1045903
433 ; RV64IM-NEXT: addiw a5, a5, -733
434 ; RV64IM-NEXT: slli a5, a5, 15
435 ; RV64IM-NEXT: addi a5, a5, 1035
436 ; RV64IM-NEXT: slli a5, a5, 12
437 ; RV64IM-NEXT: addi a5, a5, -905
438 ; RV64IM-NEXT: slli a5, a5, 12
439 ; RV64IM-NEXT: addi a5, a5, -1767
440 ; RV64IM-NEXT: mulh a2, a1, a5
441 ; RV64IM-NEXT: add a2, a2, a1
442 ; RV64IM-NEXT: srli a3, a2, 63
443 ; RV64IM-NEXT: srli a2, a2, 6
444 ; RV64IM-NEXT: add a2, a2, a3
445 ; RV64IM-NEXT: addi a3, zero, 95
446 ; RV64IM-NEXT: mul a2, a2, a3
447 ; RV64IM-NEXT: sub t0, a1, a2
448 ; RV64IM-NEXT: mulh a2, a4, a5
449 ; RV64IM-NEXT: add a2, a2, a4
450 ; RV64IM-NEXT: srli a1, a2, 63
451 ; RV64IM-NEXT: srli a2, a2, 6
452 ; RV64IM-NEXT: add a1, a2, a1
453 ; RV64IM-NEXT: mul a1, a1, a3
454 ; RV64IM-NEXT: sub a1, a4, a1
455 ; RV64IM-NEXT: mulh a2, a7, a5
456 ; RV64IM-NEXT: add a2, a2, a7
457 ; RV64IM-NEXT: srli a4, a2, 63
458 ; RV64IM-NEXT: srli a2, a2, 6
459 ; RV64IM-NEXT: add a2, a2, a4
460 ; RV64IM-NEXT: mul a2, a2, a3
461 ; RV64IM-NEXT: sub a2, a7, a2
462 ; RV64IM-NEXT: mulh a4, a6, a5
463 ; RV64IM-NEXT: add a4, a4, a6
464 ; RV64IM-NEXT: srli a5, a4, 63
465 ; RV64IM-NEXT: srli a4, a4, 6
466 ; RV64IM-NEXT: add a4, a4, a5
467 ; RV64IM-NEXT: mul a3, a4, a3
468 ; RV64IM-NEXT: sub a3, a6, a3
469 ; RV64IM-NEXT: sh a3, 6(a0)
470 ; RV64IM-NEXT: sh a2, 4(a0)
471 ; RV64IM-NEXT: sh a1, 2(a0)
472 ; RV64IM-NEXT: sh t0, 0(a0)
473 ; RV64IM-NEXT: .cfi_def_cfa_offset 0
474 ; RV64IM-NEXT: ret
475 %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
476 ret <4 x i16> %1
477 }
480 ; Don't fold if we can combine srem with sdiv.
481 define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
482 ; RV32I-LABEL: combine_srem_sdiv:
483 ; RV32I: # %bb.0:
484 ; RV32I-NEXT: addi sp, sp, -48
485 ; RV32I-NEXT: .cfi_def_cfa_offset 48
486 ; RV32I-NEXT: sw ra, 44(sp)
487 ; RV32I-NEXT: sw s0, 40(sp)
488 ; RV32I-NEXT: sw s1, 36(sp)
489 ; RV32I-NEXT: sw s2, 32(sp)
490 ; RV32I-NEXT: sw s3, 28(sp)
491 ; RV32I-NEXT: sw s4, 24(sp)
492 ; RV32I-NEXT: sw s5, 20(sp)
493 ; RV32I-NEXT: sw s6, 16(sp)
494 ; RV32I-NEXT: sw s7, 12(sp)
495 ; RV32I-NEXT: sw s8, 8(sp)
496 ; RV32I-NEXT: sw s9, 4(sp)
497 ; RV32I-NEXT: .cfi_offset ra, -4
498 ; RV32I-NEXT: .cfi_offset s0, -8
499 ; RV32I-NEXT: .cfi_offset s1, -12
500 ; RV32I-NEXT: .cfi_offset s2, -16
501 ; RV32I-NEXT: .cfi_offset s3, -20
502 ; RV32I-NEXT: .cfi_offset s4, -24
503 ; RV32I-NEXT: .cfi_offset s5, -28
504 ; RV32I-NEXT: .cfi_offset s6, -32
505 ; RV32I-NEXT: .cfi_offset s7, -36
506 ; RV32I-NEXT: .cfi_offset s8, -40
507 ; RV32I-NEXT: .cfi_offset s9, -44
508 ; RV32I-NEXT: lh s2, 0(a1)
509 ; RV32I-NEXT: lh s3, 4(a1)
510 ; RV32I-NEXT: lh s4, 8(a1)
511 ; RV32I-NEXT: lh s1, 12(a1)
512 ; RV32I-NEXT: mv s0, a0
513 ; RV32I-NEXT: addi a1, zero, 95
514 ; RV32I-NEXT: mv a0, s1
515 ; RV32I-NEXT: call __modsi3
516 ; RV32I-NEXT: mv s5, a0
517 ; RV32I-NEXT: addi a1, zero, 95
518 ; RV32I-NEXT: mv a0, s4
519 ; RV32I-NEXT: call __modsi3
520 ; RV32I-NEXT: mv s6, a0
521 ; RV32I-NEXT: addi a1, zero, 95
522 ; RV32I-NEXT: mv a0, s3
523 ; RV32I-NEXT: call __modsi3
524 ; RV32I-NEXT: mv s7, a0
525 ; RV32I-NEXT: addi a1, zero, 95
526 ; RV32I-NEXT: mv a0, s2
527 ; RV32I-NEXT: call __modsi3
528 ; RV32I-NEXT: mv s8, a0
529 ; RV32I-NEXT: addi a1, zero, 95
530 ; RV32I-NEXT: mv a0, s1
531 ; RV32I-NEXT: call __divsi3
532 ; RV32I-NEXT: mv s9, a0
533 ; RV32I-NEXT: addi a1, zero, 95
534 ; RV32I-NEXT: mv a0, s4
535 ; RV32I-NEXT: call __divsi3
536 ; RV32I-NEXT: mv s4, a0
537 ; RV32I-NEXT: addi a1, zero, 95
538 ; RV32I-NEXT: mv a0, s3
539 ; RV32I-NEXT: call __divsi3
540 ; RV32I-NEXT: mv s1, a0
541 ; RV32I-NEXT: addi a1, zero, 95
542 ; RV32I-NEXT: mv a0, s2
543 ; RV32I-NEXT: call __divsi3
544 ; RV32I-NEXT: add a0, s8, a0
545 ; RV32I-NEXT: add a1, s7, s1
546 ; RV32I-NEXT: add a2, s6, s4
547 ; RV32I-NEXT: add a3, s5, s9
548 ; RV32I-NEXT: sh a3, 6(s0)
549 ; RV32I-NEXT: sh a2, 4(s0)
550 ; RV32I-NEXT: sh a1, 2(s0)
551 ; RV32I-NEXT: sh a0, 0(s0)
552 ; RV32I-NEXT: lw s9, 4(sp)
553 ; RV32I-NEXT: lw s8, 8(sp)
554 ; RV32I-NEXT: lw s7, 12(sp)
555 ; RV32I-NEXT: lw s6, 16(sp)
556 ; RV32I-NEXT: lw s5, 20(sp)
557 ; RV32I-NEXT: lw s4, 24(sp)
558 ; RV32I-NEXT: lw s3, 28(sp)
559 ; RV32I-NEXT: lw s2, 32(sp)
560 ; RV32I-NEXT: lw s1, 36(sp)
561 ; RV32I-NEXT: lw s0, 40(sp)
562 ; RV32I-NEXT: lw ra, 44(sp)
563 ; RV32I-NEXT: .cfi_restore ra
564 ; RV32I-NEXT: .cfi_restore s0
565 ; RV32I-NEXT: .cfi_restore s1
566 ; RV32I-NEXT: .cfi_restore s2
567 ; RV32I-NEXT: .cfi_restore s3
568 ; RV32I-NEXT: .cfi_restore s4
569 ; RV32I-NEXT: .cfi_restore s5
570 ; RV32I-NEXT: .cfi_restore s6
571 ; RV32I-NEXT: .cfi_restore s7
572 ; RV32I-NEXT: .cfi_restore s8
573 ; RV32I-NEXT: .cfi_restore s9
574 ; RV32I-NEXT: addi sp, sp, 48
575 ; RV32I-NEXT: .cfi_def_cfa_offset 0
576 ; RV32I-NEXT: ret
577 ;
578 ; RV32IM-LABEL: combine_srem_sdiv:
579 ; RV32IM: # %bb.0:
580 ; RV32IM-NEXT: lh a6, 0(a1)
581 ; RV32IM-NEXT: lh a3, 4(a1)
582 ; RV32IM-NEXT: lh a4, 12(a1)
583 ; RV32IM-NEXT: lh a1, 8(a1)
584 ; RV32IM-NEXT: lui a5, 706409
585 ; RV32IM-NEXT: addi a5, a5, 389
586 ; RV32IM-NEXT: mulh a2, a4, a5
587 ; RV32IM-NEXT: add a2, a2, a4
588 ; RV32IM-NEXT: srli a7, a2, 31
589 ; RV32IM-NEXT: srai a2, a2, 6
590 ; RV32IM-NEXT: add t0, a2, a7
591 ; RV32IM-NEXT: addi a7, zero, 95
592 ; RV32IM-NEXT: mul a2, t0, a7
593 ; RV32IM-NEXT: sub t1, a4, a2
594 ; RV32IM-NEXT: mulh a4, a1, a5
595 ; RV32IM-NEXT: add a4, a4, a1
596 ; RV32IM-NEXT: srli a2, a4, 31
597 ; RV32IM-NEXT: srai a4, a4, 6
598 ; RV32IM-NEXT: add a2, a4, a2
599 ; RV32IM-NEXT: mul a4, a2, a7
600 ; RV32IM-NEXT: sub t2, a1, a4
601 ; RV32IM-NEXT: mulh a4, a3, a5
602 ; RV32IM-NEXT: add a4, a4, a3
603 ; RV32IM-NEXT: srli a1, a4, 31
604 ; RV32IM-NEXT: srai a4, a4, 6
605 ; RV32IM-NEXT: add a1, a4, a1
606 ; RV32IM-NEXT: mul a4, a1, a7
607 ; RV32IM-NEXT: sub a3, a3, a4
608 ; RV32IM-NEXT: mulh a4, a6, a5
609 ; RV32IM-NEXT: add a4, a4, a6
610 ; RV32IM-NEXT: srli a5, a4, 31
611 ; RV32IM-NEXT: srai a4, a4, 6
612 ; RV32IM-NEXT: add a4, a4, a5
613 ; RV32IM-NEXT: mul a5, a4, a7
614 ; RV32IM-NEXT: sub a5, a6, a5
615 ; RV32IM-NEXT: add a4, a5, a4
616 ; RV32IM-NEXT: add a1, a3, a1
617 ; RV32IM-NEXT: add a2, t2, a2
618 ; RV32IM-NEXT: add a3, t1, t0
619 ; RV32IM-NEXT: sh a3, 6(a0)
620 ; RV32IM-NEXT: sh a2, 4(a0)
621 ; RV32IM-NEXT: sh a1, 2(a0)
622 ; RV32IM-NEXT: sh a4, 0(a0)
623 ; RV32IM-NEXT: .cfi_def_cfa_offset 0
624 ; RV32IM-NEXT: ret
625 ;
626 ; RV64I-LABEL: combine_srem_sdiv:
627 ; RV64I: # %bb.0:
628 ; RV64I-NEXT: addi sp, sp, -96
629 ; RV64I-NEXT: .cfi_def_cfa_offset 96
630 ; RV64I-NEXT: sd ra, 88(sp)
631 ; RV64I-NEXT: sd s0, 80(sp)
632 ; RV64I-NEXT: sd s1, 72(sp)
633 ; RV64I-NEXT: sd s2, 64(sp)
634 ; RV64I-NEXT: sd s3, 56(sp)
635 ; RV64I-NEXT: sd s4, 48(sp)
636 ; RV64I-NEXT: sd s5, 40(sp)
637 ; RV64I-NEXT: sd s6, 32(sp)
638 ; RV64I-NEXT: sd s7, 24(sp)
639 ; RV64I-NEXT: sd s8, 16(sp)
640 ; RV64I-NEXT: sd s9, 8(sp)
641 ; RV64I-NEXT: .cfi_offset ra, -8
642 ; RV64I-NEXT: .cfi_offset s0, -16
643 ; RV64I-NEXT: .cfi_offset s1, -24
644 ; RV64I-NEXT: .cfi_offset s2, -32
645 ; RV64I-NEXT: .cfi_offset s3, -40
646 ; RV64I-NEXT: .cfi_offset s4, -48
647 ; RV64I-NEXT: .cfi_offset s5, -56
648 ; RV64I-NEXT: .cfi_offset s6, -64
649 ; RV64I-NEXT: .cfi_offset s7, -72
650 ; RV64I-NEXT: .cfi_offset s8, -80
651 ; RV64I-NEXT: .cfi_offset s9, -88
652 ; RV64I-NEXT: lh s2, 0(a1)
653 ; RV64I-NEXT: lh s3, 8(a1)
654 ; RV64I-NEXT: lh s4, 16(a1)
655 ; RV64I-NEXT: lh s1, 24(a1)
656 ; RV64I-NEXT: mv s0, a0
657 ; RV64I-NEXT: addi a1, zero, 95
658 ; RV64I-NEXT: mv a0, s1
659 ; RV64I-NEXT: call __moddi3
660 ; RV64I-NEXT: mv s5, a0
661 ; RV64I-NEXT: addi a1, zero, 95
662 ; RV64I-NEXT: mv a0, s4
663 ; RV64I-NEXT: call __moddi3
664 ; RV64I-NEXT: mv s6, a0
665 ; RV64I-NEXT: addi a1, zero, 95
666 ; RV64I-NEXT: mv a0, s3
667 ; RV64I-NEXT: call __moddi3
668 ; RV64I-NEXT: mv s7, a0
669 ; RV64I-NEXT: addi a1, zero, 95
670 ; RV64I-NEXT: mv a0, s2
671 ; RV64I-NEXT: call __moddi3
672 ; RV64I-NEXT: mv s8, a0
673 ; RV64I-NEXT: addi a1, zero, 95
674 ; RV64I-NEXT: mv a0, s1
675 ; RV64I-NEXT: call __divdi3
676 ; RV64I-NEXT: mv s9, a0
677 ; RV64I-NEXT: addi a1, zero, 95
678 ; RV64I-NEXT: mv a0, s4
679 ; RV64I-NEXT: call __divdi3
680 ; RV64I-NEXT: mv s4, a0
681 ; RV64I-NEXT: addi a1, zero, 95
682 ; RV64I-NEXT: mv a0, s3
683 ; RV64I-NEXT: call __divdi3
684 ; RV64I-NEXT: mv s1, a0
685 ; RV64I-NEXT: addi a1, zero, 95
686 ; RV64I-NEXT: mv a0, s2
687 ; RV64I-NEXT: call __divdi3
688 ; RV64I-NEXT: add a0, s8, a0
689 ; RV64I-NEXT: add a1, s7, s1
690 ; RV64I-NEXT: add a2, s6, s4
691 ; RV64I-NEXT: add a3, s5, s9
692 ; RV64I-NEXT: sh a3, 6(s0)
693 ; RV64I-NEXT: sh a2, 4(s0)
694 ; RV64I-NEXT: sh a1, 2(s0)
695 ; RV64I-NEXT: sh a0, 0(s0)
696 ; RV64I-NEXT: ld s9, 8(sp)
697 ; RV64I-NEXT: ld s8, 16(sp)
698 ; RV64I-NEXT: ld s7, 24(sp)
699 ; RV64I-NEXT: ld s6, 32(sp)
700 ; RV64I-NEXT: ld s5, 40(sp)
701 ; RV64I-NEXT: ld s4, 48(sp)
702 ; RV64I-NEXT: ld s3, 56(sp)
703 ; RV64I-NEXT: ld s2, 64(sp)
704 ; RV64I-NEXT: ld s1, 72(sp)
705 ; RV64I-NEXT: ld s0, 80(sp)
706 ; RV64I-NEXT: ld ra, 88(sp)
707 ; RV64I-NEXT: .cfi_restore ra
708 ; RV64I-NEXT: .cfi_restore s0
709 ; RV64I-NEXT: .cfi_restore s1
710 ; RV64I-NEXT: .cfi_restore s2
711 ; RV64I-NEXT: .cfi_restore s3
712 ; RV64I-NEXT: .cfi_restore s4
713 ; RV64I-NEXT: .cfi_restore s5
714 ; RV64I-NEXT: .cfi_restore s6
715 ; RV64I-NEXT: .cfi_restore s7
716 ; RV64I-NEXT: .cfi_restore s8
717 ; RV64I-NEXT: .cfi_restore s9
718 ; RV64I-NEXT: addi sp, sp, 96
719 ; RV64I-NEXT: .cfi_def_cfa_offset 0
720 ; RV64I-NEXT: ret
721 ;
722 ; RV64IM-LABEL: combine_srem_sdiv:
723 ; RV64IM: # %bb.0:
724 ; RV64IM-NEXT: lh a6, 0(a1)
725 ; RV64IM-NEXT: lh a7, 8(a1)
726 ; RV64IM-NEXT: lh a4, 16(a1)
727 ; RV64IM-NEXT: lh a1, 24(a1)
728 ; RV64IM-NEXT: lui a5, 1045903
729 ; RV64IM-NEXT: addiw a5, a5, -733
730 ; RV64IM-NEXT: slli a5, a5, 15
731 ; RV64IM-NEXT: addi a5, a5, 1035
732 ; RV64IM-NEXT: slli a5, a5, 12
733 ; RV64IM-NEXT: addi a5, a5, -905
734 ; RV64IM-NEXT: slli a5, a5, 12
735 ; RV64IM-NEXT: addi a5, a5, -1767
736 ; RV64IM-NEXT: mulh a2, a1, a5
737 ; RV64IM-NEXT: add a2, a2, a1
738 ; RV64IM-NEXT: srli a3, a2, 63
739 ; RV64IM-NEXT: srai a2, a2, 6
740 ; RV64IM-NEXT: add t3, a2, a3
741 ; RV64IM-NEXT: addi t0, zero, 95
742 ; RV64IM-NEXT: mul a3, t3, t0
743 ; RV64IM-NEXT: sub t1, a1, a3
744 ; RV64IM-NEXT: mulh a3, a4, a5
745 ; RV64IM-NEXT: add a3, a3, a4
746 ; RV64IM-NEXT: srli a1, a3, 63
747 ; RV64IM-NEXT: srai a3, a3, 6
748 ; RV64IM-NEXT: add a1, a3, a1
749 ; RV64IM-NEXT: mul a3, a1, t0
750 ; RV64IM-NEXT: sub t2, a4, a3
751 ; RV64IM-NEXT: mulh a4, a7, a5
752 ; RV64IM-NEXT: add a4, a4, a7
753 ; RV64IM-NEXT: srli a3, a4, 63
754 ; RV64IM-NEXT: srai a4, a4, 6
755 ; RV64IM-NEXT: add a3, a4, a3
756 ; RV64IM-NEXT: mul a4, a3, t0
757 ; RV64IM-NEXT: sub a4, a7, a4
758 ; RV64IM-NEXT: mulh a5, a6, a5
759 ; RV64IM-NEXT: add a5, a5, a6
760 ; RV64IM-NEXT: srli a2, a5, 63
761 ; RV64IM-NEXT: srai a5, a5, 6
762 ; RV64IM-NEXT: add a2, a5, a2
763 ; RV64IM-NEXT: mul a5, a2, t0
764 ; RV64IM-NEXT: sub a5, a6, a5
765 ; RV64IM-NEXT: add a2, a5, a2
766 ; RV64IM-NEXT: add a3, a4, a3
767 ; RV64IM-NEXT: add a1, t2, a1
768 ; RV64IM-NEXT: add a4, t1, t3
769 ; RV64IM-NEXT: sh a4, 6(a0)
770 ; RV64IM-NEXT: sh a1, 4(a0)
771 ; RV64IM-NEXT: sh a3, 2(a0)
772 ; RV64IM-NEXT: sh a2, 0(a0)
773 ; RV64IM-NEXT: .cfi_def_cfa_offset 0
774 ; RV64IM-NEXT: ret
775 %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
776 %2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
777 %3 = add <4 x i16> %1, %2
778 ret <4 x i16> %3
779 }
781 ; Don't fold for divisors that are a power of two.
782 define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
783 ; RV32I-LABEL: dont_fold_srem_power_of_two:
784 ; RV32I: # %bb.0:
785 ; RV32I-NEXT: addi sp, sp, -32
786 ; RV32I-NEXT: .cfi_def_cfa_offset 32
787 ; RV32I-NEXT: sw ra, 28(sp)
788 ; RV32I-NEXT: sw s0, 24(sp)
789 ; RV32I-NEXT: sw s1, 20(sp)
790 ; RV32I-NEXT: sw s2, 16(sp)
791 ; RV32I-NEXT: sw s3, 12(sp)
792 ; RV32I-NEXT: .cfi_offset ra, -4
793 ; RV32I-NEXT: .cfi_offset s0, -8
794 ; RV32I-NEXT: .cfi_offset s1, -12
795 ; RV32I-NEXT: .cfi_offset s2, -16
796 ; RV32I-NEXT: .cfi_offset s3, -20
797 ; RV32I-NEXT: mv s0, a0
798 ; RV32I-NEXT: lh a2, 0(a1)
799 ; RV32I-NEXT: lh a0, 12(a1)
800 ; RV32I-NEXT: lh a3, 8(a1)
801 ; RV32I-NEXT: lh a1, 4(a1)
802 ; RV32I-NEXT: srai a4, a2, 31
803 ; RV32I-NEXT: srli a4, a4, 26
804 ; RV32I-NEXT: add a4, a2, a4
805 ; RV32I-NEXT: lui a6, 16
806 ; RV32I-NEXT: addi a5, a6, -64
807 ; RV32I-NEXT: and a4, a4, a5
808 ; RV32I-NEXT: sub s2, a2, a4
809 ; RV32I-NEXT: srai a2, a1, 31
810 ; RV32I-NEXT: srli a2, a2, 27
811 ; RV32I-NEXT: add a2, a1, a2
812 ; RV32I-NEXT: addi a4, a6, -32
813 ; RV32I-NEXT: and a2, a2, a4
814 ; RV32I-NEXT: sub s3, a1, a2
815 ; RV32I-NEXT: srai a1, a3, 31
816 ; RV32I-NEXT: srli a1, a1, 29
817 ; RV32I-NEXT: add a1, a3, a1
818 ; RV32I-NEXT: addi a2, a6, -8
819 ; RV32I-NEXT: and a1, a1, a2
820 ; RV32I-NEXT: sub s1, a3, a1
821 ; RV32I-NEXT: addi a1, zero, 95
822 ; RV32I-NEXT: call __modsi3
823 ; RV32I-NEXT: sh a0, 6(s0)
824 ; RV32I-NEXT: sh s1, 4(s0)
825 ; RV32I-NEXT: sh s3, 2(s0)
826 ; RV32I-NEXT: sh s2, 0(s0)
827 ; RV32I-NEXT: lw s3, 12(sp)
828 ; RV32I-NEXT: lw s2, 16(sp)
829 ; RV32I-NEXT: lw s1, 20(sp)
830 ; RV32I-NEXT: lw s0, 24(sp)
831 ; RV32I-NEXT: lw ra, 28(sp)
832 ; RV32I-NEXT: .cfi_restore ra
833 ; RV32I-NEXT: .cfi_restore s0
834 ; RV32I-NEXT: .cfi_restore s1
835 ; RV32I-NEXT: .cfi_restore s2
836 ; RV32I-NEXT: .cfi_restore s3
837 ; RV32I-NEXT: addi sp, sp, 32
838 ; RV32I-NEXT: .cfi_def_cfa_offset 0
839 ; RV32I-NEXT: ret
840 ;
841 ; RV32IM-LABEL: dont_fold_srem_power_of_two:
842 ; RV32IM: # %bb.0:
843 ; RV32IM-NEXT: lh a6, 8(a1)
844 ; RV32IM-NEXT: lh a3, 4(a1)
845 ; RV32IM-NEXT: lh a4, 12(a1)
846 ; RV32IM-NEXT: lh a1, 0(a1)
847 ; RV32IM-NEXT: lui a5, 706409
848 ; RV32IM-NEXT: addi a5, a5, 389
849 ; RV32IM-NEXT: mulh a5, a4, a5
850 ; RV32IM-NEXT: add a5, a5, a4
851 ; RV32IM-NEXT: srli a2, a5, 31
852 ; RV32IM-NEXT: srli a5, a5, 6
853 ; RV32IM-NEXT: add a2, a5, a2
854 ; RV32IM-NEXT: addi a5, zero, 95
855 ; RV32IM-NEXT: mul a2, a2, a5
856 ; RV32IM-NEXT: sub a7, a4, a2
857 ; RV32IM-NEXT: srai a4, a1, 31
858 ; RV32IM-NEXT: srli a4, a4, 26
859 ; RV32IM-NEXT: add a4, a1, a4
860 ; RV32IM-NEXT: lui a5, 16
861 ; RV32IM-NEXT: addi a2, a5, -64
862 ; RV32IM-NEXT: and a2, a4, a2
863 ; RV32IM-NEXT: sub a1, a1, a2
864 ; RV32IM-NEXT: srai a2, a3, 31
865 ; RV32IM-NEXT: srli a2, a2, 27
866 ; RV32IM-NEXT: add a2, a3, a2
867 ; RV32IM-NEXT: addi a4, a5, -32
868 ; RV32IM-NEXT: and a2, a2, a4
869 ; RV32IM-NEXT: sub a2, a3, a2
870 ; RV32IM-NEXT: srai a3, a6, 31
871 ; RV32IM-NEXT: srli a3, a3, 29
872 ; RV32IM-NEXT: add a3, a6, a3
873 ; RV32IM-NEXT: addi a4, a5, -8
874 ; RV32IM-NEXT: and a3, a3, a4
875 ; RV32IM-NEXT: sub a3, a6, a3
876 ; RV32IM-NEXT: sh a3, 4(a0)
877 ; RV32IM-NEXT: sh a2, 2(a0)
878 ; RV32IM-NEXT: sh a1, 0(a0)
879 ; RV32IM-NEXT: sh a7, 6(a0)
880 ; RV32IM-NEXT: .cfi_def_cfa_offset 0
881 ; RV32IM-NEXT: ret
882 ;
883 ; RV64I-LABEL: dont_fold_srem_power_of_two:
884 ; RV64I: # %bb.0:
885 ; RV64I-NEXT: addi sp, sp, -48
886 ; RV64I-NEXT: .cfi_def_cfa_offset 48
887 ; RV64I-NEXT: sd ra, 40(sp)
888 ; RV64I-NEXT: sd s0, 32(sp)
889 ; RV64I-NEXT: sd s1, 24(sp)
890 ; RV64I-NEXT: sd s2, 16(sp)
891 ; RV64I-NEXT: sd s3, 8(sp)
892 ; RV64I-NEXT: .cfi_offset ra, -8
893 ; RV64I-NEXT: .cfi_offset s0, -16
894 ; RV64I-NEXT: .cfi_offset s1, -24
895 ; RV64I-NEXT: .cfi_offset s2, -32
896 ; RV64I-NEXT: .cfi_offset s3, -40
897 ; RV64I-NEXT: mv s0, a0
898 ; RV64I-NEXT: lh a2, 0(a1)
899 ; RV64I-NEXT: lh a0, 24(a1)
900 ; RV64I-NEXT: lh a3, 16(a1)
901 ; RV64I-NEXT: lh a1, 8(a1)
902 ; RV64I-NEXT: srai a4, a2, 63
903 ; RV64I-NEXT: srli a4, a4, 58
904 ; RV64I-NEXT: add a4, a2, a4
905 ; RV64I-NEXT: lui a6, 16
906 ; RV64I-NEXT: addiw a5, a6, -64
907 ; RV64I-NEXT: and a4, a4, a5
908 ; RV64I-NEXT: sub s2, a2, a4
909 ; RV64I-NEXT: srai a2, a1, 63
910 ; RV64I-NEXT: srli a2, a2, 59
911 ; RV64I-NEXT: add a2, a1, a2
912 ; RV64I-NEXT: addiw a4, a6, -32
913 ; RV64I-NEXT: and a2, a2, a4
914 ; RV64I-NEXT: sub s3, a1, a2
915 ; RV64I-NEXT: srai a1, a3, 63
916 ; RV64I-NEXT: srli a1, a1, 61
917 ; RV64I-NEXT: add a1, a3, a1
918 ; RV64I-NEXT: addiw a2, a6, -8
919 ; RV64I-NEXT: and a1, a1, a2
920 ; RV64I-NEXT: sub s1, a3, a1
921 ; RV64I-NEXT: addi a1, zero, 95
922 ; RV64I-NEXT: call __moddi3
923 ; RV64I-NEXT: sh a0, 6(s0)
924 ; RV64I-NEXT: sh s1, 4(s0)
925 ; RV64I-NEXT: sh s3, 2(s0)
926 ; RV64I-NEXT: sh s2, 0(s0)
927 ; RV64I-NEXT: ld s3, 8(sp)
928 ; RV64I-NEXT: ld s2, 16(sp)
929 ; RV64I-NEXT: ld s1, 24(sp)
930 ; RV64I-NEXT: ld s0, 32(sp)
931 ; RV64I-NEXT: ld ra, 40(sp)
932 ; RV64I-NEXT: .cfi_restore ra
933 ; RV64I-NEXT: .cfi_restore s0
934 ; RV64I-NEXT: .cfi_restore s1
935 ; RV64I-NEXT: .cfi_restore s2
936 ; RV64I-NEXT: .cfi_restore s3
937 ; RV64I-NEXT: addi sp, sp, 48
938 ; RV64I-NEXT: .cfi_def_cfa_offset 0
939 ; RV64I-NEXT: ret
940 ;
941 ; RV64IM-LABEL: dont_fold_srem_power_of_two:
942 ; RV64IM: # %bb.0:
943 ; RV64IM-NEXT: lh a6, 16(a1)
944 ; RV64IM-NEXT: lh a3, 8(a1)
945 ; RV64IM-NEXT: lh a4, 0(a1)
946 ; RV64IM-NEXT: lh a1, 24(a1)
947 ; RV64IM-NEXT: lui a5, 1045903
948 ; RV64IM-NEXT: addiw a5, a5, -733
949 ; RV64IM-NEXT: slli a5, a5, 15
950 ; RV64IM-NEXT: addi a5, a5, 1035
951 ; RV64IM-NEXT: slli a5, a5, 12
952 ; RV64IM-NEXT: addi a5, a5, -905
953 ; RV64IM-NEXT: slli a5, a5, 12
954 ; RV64IM-NEXT: addi a5, a5, -1767
955 ; RV64IM-NEXT: mulh a5, a1, a5
956 ; RV64IM-NEXT: add a5, a5, a1
957 ; RV64IM-NEXT: srli a2, a5, 63
958 ; RV64IM-NEXT: srli a5, a5, 6
959 ; RV64IM-NEXT: add a2, a5, a2
960 ; RV64IM-NEXT: addi a5, zero, 95
961 ; RV64IM-NEXT: mul a2, a2, a5
962 ; RV64IM-NEXT: sub a7, a1, a2
963 ; RV64IM-NEXT: srai a2, a4, 63
964 ; RV64IM-NEXT: srli a2, a2, 58
965 ; RV64IM-NEXT: add a2, a4, a2
966 ; RV64IM-NEXT: lui a5, 16
967 ; RV64IM-NEXT: addiw a1, a5, -64
968 ; RV64IM-NEXT: and a1, a2, a1
969 ; RV64IM-NEXT: sub a1, a4, a1
970 ; RV64IM-NEXT: srai a2, a3, 63
971 ; RV64IM-NEXT: srli a2, a2, 59
972 ; RV64IM-NEXT: add a2, a3, a2
973 ; RV64IM-NEXT: addiw a4, a5, -32
974 ; RV64IM-NEXT: and a2, a2, a4
975 ; RV64IM-NEXT: sub a2, a3, a2
976 ; RV64IM-NEXT: srai a3, a6, 63
977 ; RV64IM-NEXT: srli a3, a3, 61
978 ; RV64IM-NEXT: add a3, a6, a3
979 ; RV64IM-NEXT: addiw a4, a5, -8
980 ; RV64IM-NEXT: and a3, a3, a4
981 ; RV64IM-NEXT: sub a3, a6, a3
982 ; RV64IM-NEXT: sh a3, 4(a0)
983 ; RV64IM-NEXT: sh a2, 2(a0)
984 ; RV64IM-NEXT: sh a1, 0(a0)
985 ; RV64IM-NEXT: sh a7, 6(a0)
986 ; RV64IM-NEXT: .cfi_def_cfa_offset 0
987 ; RV64IM-NEXT: ret
988 %1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
989 ret <4 x i16> %1
990 }
992 ; Don't fold if the divisor is one.
993 define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
994 ; RV32I-LABEL: dont_fold_srem_one:
995 ; RV32I: # %bb.0:
996 ; RV32I-NEXT: addi sp, sp, -32
997 ; RV32I-NEXT: .cfi_def_cfa_offset 32
998 ; RV32I-NEXT: sw ra, 28(sp)
999 ; RV32I-NEXT: sw s0, 24(sp)
1000 ; RV32I-NEXT: sw s1, 20(sp)
1001 ; RV32I-NEXT: sw s2, 16(sp)
1002 ; RV32I-NEXT: sw s3, 12(sp)
1003 ; RV32I-NEXT: .cfi_offset ra, -4
1004 ; RV32I-NEXT: .cfi_offset s0, -8
1005 ; RV32I-NEXT: .cfi_offset s1, -12
1006 ; RV32I-NEXT: .cfi_offset s2, -16
1007 ; RV32I-NEXT: .cfi_offset s3, -20
1008 ; RV32I-NEXT: lh s2, 12(a1)
1009 ; RV32I-NEXT: lh s1, 8(a1)
1010 ; RV32I-NEXT: lh a2, 4(a1)
1011 ; RV32I-NEXT: mv s0, a0
1012 ; RV32I-NEXT: addi a1, zero, 654
1013 ; RV32I-NEXT: mv a0, a2
1014 ; RV32I-NEXT: call __modsi3
1015 ; RV32I-NEXT: mv s3, a0
1016 ; RV32I-NEXT: addi a1, zero, 23
1017 ; RV32I-NEXT: mv a0, s1
1018 ; RV32I-NEXT: call __modsi3
1019 ; RV32I-NEXT: mv s1, a0
1020 ; RV32I-NEXT: lui a0, 1
1021 ; RV32I-NEXT: addi a1, a0, 1327
1022 ; RV32I-NEXT: mv a0, s2
1023 ; RV32I-NEXT: call __modsi3
1024 ; RV32I-NEXT: sh zero, 0(s0)
1025 ; RV32I-NEXT: sh a0, 6(s0)
1026 ; RV32I-NEXT: sh s1, 4(s0)
1027 ; RV32I-NEXT: sh s3, 2(s0)
1028 ; RV32I-NEXT: lw s3, 12(sp)
1029 ; RV32I-NEXT: lw s2, 16(sp)
1030 ; RV32I-NEXT: lw s1, 20(sp)
1031 ; RV32I-NEXT: lw s0, 24(sp)
1032 ; RV32I-NEXT: lw ra, 28(sp)
1033 ; RV32I-NEXT: .cfi_restore ra
1034 ; RV32I-NEXT: .cfi_restore s0
1035 ; RV32I-NEXT: .cfi_restore s1
1036 ; RV32I-NEXT: .cfi_restore s2
1037 ; RV32I-NEXT: .cfi_restore s3
1038 ; RV32I-NEXT: addi sp, sp, 32
1039 ; RV32I-NEXT: .cfi_def_cfa_offset 0
1040 ; RV32I-NEXT: ret
1041 ;
1042 ; RV32IM-LABEL: dont_fold_srem_one:
1043 ; RV32IM: # %bb.0:
1044 ; RV32IM-NEXT: lh a2, 12(a1)
1045 ; RV32IM-NEXT: lh a3, 4(a1)
1046 ; RV32IM-NEXT: lh a1, 8(a1)
1047 ; RV32IM-NEXT: lui a4, 820904
1048 ; RV32IM-NEXT: addi a4, a4, -1903
1049 ; RV32IM-NEXT: mulh a4, a3, a4
1050 ; RV32IM-NEXT: add a4, a4, a3
1051 ; RV32IM-NEXT: srli a5, a4, 31
1052 ; RV32IM-NEXT: srli a4, a4, 9
1053 ; RV32IM-NEXT: add a4, a4, a5
1054 ; RV32IM-NEXT: addi a5, zero, 654
1055 ; RV32IM-NEXT: mul a4, a4, a5
1056 ; RV32IM-NEXT: sub a3, a3, a4
1057 ; RV32IM-NEXT: lui a4, 729444
1058 ; RV32IM-NEXT: addi a4, a4, 713
1059 ; RV32IM-NEXT: mulh a4, a1, a4
1060 ; RV32IM-NEXT: add a4, a4, a1
1061 ; RV32IM-NEXT: srli a5, a4, 31
1062 ; RV32IM-NEXT: srli a4, a4, 4
1063 ; RV32IM-NEXT: add a4, a4, a5
1064 ; RV32IM-NEXT: addi a5, zero, 23
1065 ; RV32IM-NEXT: mul a4, a4, a5
1066 ; RV32IM-NEXT: sub a1, a1, a4
1067 ; RV32IM-NEXT: lui a4, 395996
1068 ; RV32IM-NEXT: addi a4, a4, -2009
1069 ; RV32IM-NEXT: mulh a4, a2, a4
1070 ; RV32IM-NEXT: srli a5, a4, 31
1071 ; RV32IM-NEXT: srli a4, a4, 11
1072 ; RV32IM-NEXT: add a4, a4, a5
1073 ; RV32IM-NEXT: lui a5, 1
1074 ; RV32IM-NEXT: addi a5, a5, 1327
1075 ; RV32IM-NEXT: mul a4, a4, a5
1076 ; RV32IM-NEXT: sub a2, a2, a4
1077 ; RV32IM-NEXT: sh zero, 0(a0)
1078 ; RV32IM-NEXT: sh a2, 6(a0)
1079 ; RV32IM-NEXT: sh a1, 4(a0)
1080 ; RV32IM-NEXT: sh a3, 2(a0)
1081 ; RV32IM-NEXT: .cfi_def_cfa_offset 0
1082 ; RV32IM-NEXT: ret
1083 ;
1084 ; RV64I-LABEL: dont_fold_srem_one:
1085 ; RV64I: # %bb.0:
1086 ; RV64I-NEXT: addi sp, sp, -48
1087 ; RV64I-NEXT: .cfi_def_cfa_offset 48
1088 ; RV64I-NEXT: sd ra, 40(sp)
1089 ; RV64I-NEXT: sd s0, 32(sp)
1090 ; RV64I-NEXT: sd s1, 24(sp)
1091 ; RV64I-NEXT: sd s2, 16(sp)
1092 ; RV64I-NEXT: sd s3, 8(sp)
1093 ; RV64I-NEXT: .cfi_offset ra, -8
1094 ; RV64I-NEXT: .cfi_offset s0, -16
1095 ; RV64I-NEXT: .cfi_offset s1, -24
1096 ; RV64I-NEXT: .cfi_offset s2, -32
1097 ; RV64I-NEXT: .cfi_offset s3, -40
1098 ; RV64I-NEXT: lh s2, 24(a1)
1099 ; RV64I-NEXT: lh s1, 16(a1)
1100 ; RV64I-NEXT: lh a2, 8(a1)
1101 ; RV64I-NEXT: mv s0, a0
1102 ; RV64I-NEXT: addi a1, zero, 654
1103 ; RV64I-NEXT: mv a0, a2
1104 ; RV64I-NEXT: call __moddi3
1105 ; RV64I-NEXT: mv s3, a0
1106 ; RV64I-NEXT: addi a1, zero, 23
1107 ; RV64I-NEXT: mv a0, s1
1108 ; RV64I-NEXT: call __moddi3
1109 ; RV64I-NEXT: mv s1, a0
1110 ; RV64I-NEXT: lui a0, 1
1111 ; RV64I-NEXT: addiw a1, a0, 1327
1112 ; RV64I-NEXT: mv a0, s2
1113 ; RV64I-NEXT: call __moddi3
1114 ; RV64I-NEXT: sh zero, 0(s0)
1115 ; RV64I-NEXT: sh a0, 6(s0)
1116 ; RV64I-NEXT: sh s1, 4(s0)
1117 ; RV64I-NEXT: sh s3, 2(s0)
1118 ; RV64I-NEXT: ld s3, 8(sp)
1119 ; RV64I-NEXT: ld s2, 16(sp)
1120 ; RV64I-NEXT: ld s1, 24(sp)
1121 ; RV64I-NEXT: ld s0, 32(sp)
1122 ; RV64I-NEXT: ld ra, 40(sp)
1123 ; RV64I-NEXT: .cfi_restore ra
1124 ; RV64I-NEXT: .cfi_restore s0
1125 ; RV64I-NEXT: .cfi_restore s1
1126 ; RV64I-NEXT: .cfi_restore s2
1127 ; RV64I-NEXT: .cfi_restore s3
1128 ; RV64I-NEXT: addi sp, sp, 48
1129 ; RV64I-NEXT: .cfi_def_cfa_offset 0
1130 ; RV64I-NEXT: ret
1131 ;
1132 ; RV64IM-LABEL: dont_fold_srem_one:
1133 ; RV64IM: # %bb.0:
1134 ; RV64IM-NEXT: lh a2, 24(a1)
1135 ; RV64IM-NEXT: lh a3, 8(a1)
1136 ; RV64IM-NEXT: lh a1, 16(a1)
1137 ; RV64IM-NEXT: lui a4, 1043590
1138 ; RV64IM-NEXT: addiw a4, a4, -1781
1139 ; RV64IM-NEXT: slli a4, a4, 13
1140 ; RV64IM-NEXT: addi a4, a4, 1069
1141 ; RV64IM-NEXT: slli a4, a4, 12
1142 ; RV64IM-NEXT: addi a4, a4, -1959
1143 ; RV64IM-NEXT: slli a4, a4, 13
1144 ; RV64IM-NEXT: addi a4, a4, 357
1145 ; RV64IM-NEXT: mulh a4, a1, a4
1146 ; RV64IM-NEXT: add a4, a4, a1
1147 ; RV64IM-NEXT: srli a5, a4, 63
1148 ; RV64IM-NEXT: srli a4, a4, 4
1149 ; RV64IM-NEXT: add a4, a4, a5
1150 ; RV64IM-NEXT: addi a5, zero, 23
1151 ; RV64IM-NEXT: mul a4, a4, a5
1152 ; RV64IM-NEXT: sub a1, a1, a4
1153 ; RV64IM-NEXT: lui a4, 6413
1154 ; RV64IM-NEXT: addiw a4, a4, 1265
1155 ; RV64IM-NEXT: slli a4, a4, 13
1156 ; RV64IM-NEXT: addi a4, a4, 1027
1157 ; RV64IM-NEXT: slli a4, a4, 13
1158 ; RV64IM-NEXT: addi a4, a4, 1077
1159 ; RV64IM-NEXT: slli a4, a4, 12
1160 ; RV64IM-NEXT: addi a4, a4, 965
1161 ; RV64IM-NEXT: mulh a4, a3, a4
1162 ; RV64IM-NEXT: srli a5, a4, 63
1163 ; RV64IM-NEXT: srli a4, a4, 8
1164 ; RV64IM-NEXT: add a4, a4, a5
1165 ; RV64IM-NEXT: addi a5, zero, 654
1166 ; RV64IM-NEXT: mul a4, a4, a5
1167 ; RV64IM-NEXT: sub a3, a3, a4
1168 ; RV64IM-NEXT: lui a4, 12375
1169 ; RV64IM-NEXT: addiw a4, a4, -575
1170 ; RV64IM-NEXT: slli a4, a4, 12
1171 ; RV64IM-NEXT: addi a4, a4, 883
1172 ; RV64IM-NEXT: slli a4, a4, 13
1173 ; RV64IM-NEXT: addi a4, a4, -431
1174 ; RV64IM-NEXT: slli a4, a4, 12
1175 ; RV64IM-NEXT: addi a4, a4, 1959
1176 ; RV64IM-NEXT: mulh a4, a2, a4
1177 ; RV64IM-NEXT: srli a5, a4, 63
1178 ; RV64IM-NEXT: srli a4, a4, 11
1179 ; RV64IM-NEXT: add a4, a4, a5
1180 ; RV64IM-NEXT: lui a5, 1
1181 ; RV64IM-NEXT: addiw a5, a5, 1327
1182 ; RV64IM-NEXT: mul a4, a4, a5
1183 ; RV64IM-NEXT: sub a2, a2, a4
1184 ; RV64IM-NEXT: sh zero, 0(a0)
1185 ; RV64IM-NEXT: sh a2, 6(a0)
1186 ; RV64IM-NEXT: sh a3, 2(a0)
1187 ; RV64IM-NEXT: sh a1, 4(a0)
1188 ; RV64IM-NEXT: .cfi_def_cfa_offset 0
1189 ; RV64IM-NEXT: ret
1190 %1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
1191 ret <4 x i16> %1
1192 }
1194 ; Don't fold if the divisor is 2^15.
1195 define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
1196 ; RV32I-LABEL: dont_fold_urem_i16_smax:
1197 ; RV32I: # %bb.0:
1198 ; RV32I-NEXT: addi sp, sp, -32
1199 ; RV32I-NEXT: .cfi_def_cfa_offset 32
1200 ; RV32I-NEXT: sw ra, 28(sp)
1201 ; RV32I-NEXT: sw s0, 24(sp)
1202 ; RV32I-NEXT: sw s1, 20(sp)
1203 ; RV32I-NEXT: sw s2, 16(sp)
1204 ; RV32I-NEXT: sw s3, 12(sp)
1205 ; RV32I-NEXT: .cfi_offset ra, -4
1206 ; RV32I-NEXT: .cfi_offset s0, -8
1207 ; RV32I-NEXT: .cfi_offset s1, -12
1208 ; RV32I-NEXT: .cfi_offset s2, -16
1209 ; RV32I-NEXT: .cfi_offset s3, -20
1210 ; RV32I-NEXT: lh a2, 4(a1)
1211 ; RV32I-NEXT: mv s0, a0
1212 ; RV32I-NEXT: lh s2, 12(a1)
1213 ; RV32I-NEXT: lh a0, 8(a1)
1214 ; RV32I-NEXT: slli a1, a2, 16
1215 ; RV32I-NEXT: srai a1, a1, 31
1216 ; RV32I-NEXT: srli a1, a1, 17
1217 ; RV32I-NEXT: add a1, a2, a1
1218 ; RV32I-NEXT: lui a3, 8
1219 ; RV32I-NEXT: and a1, a1, a3
1220 ; RV32I-NEXT: sub s3, a2, a1
1221 ; RV32I-NEXT: addi a1, zero, 23
1222 ; RV32I-NEXT: call __modsi3
1223 ; RV32I-NEXT: mv s1, a0
1224 ; RV32I-NEXT: lui a0, 1
1225 ; RV32I-NEXT: addi a1, a0, 1327
1226 ; RV32I-NEXT: mv a0, s2
1227 ; RV32I-NEXT: call __modsi3
1228 ; RV32I-NEXT: sh zero, 0(s0)
1229 ; RV32I-NEXT: sh a0, 6(s0)
1230 ; RV32I-NEXT: sh s1, 4(s0)
1231 ; RV32I-NEXT: sh s3, 2(s0)
1232 ; RV32I-NEXT: lw s3, 12(sp)
1233 ; RV32I-NEXT: lw s2, 16(sp)
1234 ; RV32I-NEXT: lw s1, 20(sp)
1235 ; RV32I-NEXT: lw s0, 24(sp)
1236 ; RV32I-NEXT: lw ra, 28(sp)
1237 ; RV32I-NEXT: .cfi_restore ra
1238 ; RV32I-NEXT: .cfi_restore s0
1239 ; RV32I-NEXT: .cfi_restore s1
1240 ; RV32I-NEXT: .cfi_restore s2
1241 ; RV32I-NEXT: .cfi_restore s3
1242 ; RV32I-NEXT: addi sp, sp, 32
1243 ; RV32I-NEXT: .cfi_def_cfa_offset 0
1244 ; RV32I-NEXT: ret
1245 ;
1246 ; RV32IM-LABEL: dont_fold_urem_i16_smax:
1247 ; RV32IM: # %bb.0:
1248 ; RV32IM-NEXT: lh a2, 4(a1)
1249 ; RV32IM-NEXT: slli a6, a2, 16
1250 ; RV32IM-NEXT: lh a4, 8(a1)
1251 ; RV32IM-NEXT: lh a1, 12(a1)
1252 ; RV32IM-NEXT: lui a5, 729444
1253 ; RV32IM-NEXT: addi a5, a5, 713
1254 ; RV32IM-NEXT: mulh a5, a4, a5
1255 ; RV32IM-NEXT: add a5, a5, a4
1256 ; RV32IM-NEXT: srli a3, a5, 31
1257 ; RV32IM-NEXT: srli a5, a5, 4
1258 ; RV32IM-NEXT: add a3, a5, a3
1259 ; RV32IM-NEXT: addi a5, zero, 23
1260 ; RV32IM-NEXT: mul a3, a3, a5
1261 ; RV32IM-NEXT: sub a3, a4, a3
1262 ; RV32IM-NEXT: lui a4, 395996
1263 ; RV32IM-NEXT: addi a4, a4, -2009
1264 ; RV32IM-NEXT: mulh a4, a1, a4
1265 ; RV32IM-NEXT: srli a5, a4, 31
1266 ; RV32IM-NEXT: srli a4, a4, 11
1267 ; RV32IM-NEXT: add a4, a4, a5
1268 ; RV32IM-NEXT: lui a5, 1
1269 ; RV32IM-NEXT: addi a5, a5, 1327
1270 ; RV32IM-NEXT: mul a4, a4, a5
1271 ; RV32IM-NEXT: sub a1, a1, a4
1272 ; RV32IM-NEXT: srai a4, a6, 31
1273 ; RV32IM-NEXT: srli a4, a4, 17
1274 ; RV32IM-NEXT: add a4, a2, a4
1275 ; RV32IM-NEXT: lui a5, 8
1276 ; RV32IM-NEXT: and a4, a4, a5
1277 ; RV32IM-NEXT: sub a2, a2, a4
1278 ; RV32IM-NEXT: sh zero, 0(a0)
1279 ; RV32IM-NEXT: sh a1, 6(a0)
1280 ; RV32IM-NEXT: sh a3, 4(a0)
1281 ; RV32IM-NEXT: sh a2, 2(a0)
1282 ; RV32IM-NEXT: .cfi_def_cfa_offset 0
1283 ; RV32IM-NEXT: ret
1284 ;
1285 ; RV64I-LABEL: dont_fold_urem_i16_smax:
1286 ; RV64I: # %bb.0:
1287 ; RV64I-NEXT: addi sp, sp, -48
1288 ; RV64I-NEXT: .cfi_def_cfa_offset 48
1289 ; RV64I-NEXT: sd ra, 40(sp)
1290 ; RV64I-NEXT: sd s0, 32(sp)
1291 ; RV64I-NEXT: sd s1, 24(sp)
1292 ; RV64I-NEXT: sd s2, 16(sp)
1293 ; RV64I-NEXT: sd s3, 8(sp)
1294 ; RV64I-NEXT: .cfi_offset ra, -8
1295 ; RV64I-NEXT: .cfi_offset s0, -16
1296 ; RV64I-NEXT: .cfi_offset s1, -24
1297 ; RV64I-NEXT: .cfi_offset s2, -32
1298 ; RV64I-NEXT: .cfi_offset s3, -40
1299 ; RV64I-NEXT: lh a2, 8(a1)
1300 ; RV64I-NEXT: mv s0, a0
1301 ; RV64I-NEXT: lh s2, 24(a1)
1302 ; RV64I-NEXT: lh a0, 16(a1)
1303 ; RV64I-NEXT: slli a1, a2, 48
1304 ; RV64I-NEXT: srai a1, a1, 63
1305 ; RV64I-NEXT: srli a1, a1, 49
1306 ; RV64I-NEXT: add a1, a2, a1
1307 ; RV64I-NEXT: lui a3, 8
1308 ; RV64I-NEXT: and a1, a1, a3
1309 ; RV64I-NEXT: sub s3, a2, a1
1310 ; RV64I-NEXT: addi a1, zero, 23
1311 ; RV64I-NEXT: call __moddi3
1312 ; RV64I-NEXT: mv s1, a0
1313 ; RV64I-NEXT: lui a0, 1
1314 ; RV64I-NEXT: addiw a1, a0, 1327
1315 ; RV64I-NEXT: mv a0, s2
1316 ; RV64I-NEXT: call __moddi3
1317 ; RV64I-NEXT: sh zero, 0(s0)
1318 ; RV64I-NEXT: sh a0, 6(s0)
1319 ; RV64I-NEXT: sh s1, 4(s0)
1320 ; RV64I-NEXT: sh s3, 2(s0)
1321 ; RV64I-NEXT: ld s3, 8(sp)
1322 ; RV64I-NEXT: ld s2, 16(sp)
1323 ; RV64I-NEXT: ld s1, 24(sp)
1324 ; RV64I-NEXT: ld s0, 32(sp)
1325 ; RV64I-NEXT: ld ra, 40(sp)
1326 ; RV64I-NEXT: .cfi_restore ra
1327 ; RV64I-NEXT: .cfi_restore s0
1328 ; RV64I-NEXT: .cfi_restore s1
1329 ; RV64I-NEXT: .cfi_restore s2
1330 ; RV64I-NEXT: .cfi_restore s3
1331 ; RV64I-NEXT: addi sp, sp, 48
1332 ; RV64I-NEXT: .cfi_def_cfa_offset 0
1333 ; RV64I-NEXT: ret
1334 ;
1335 ; RV64IM-LABEL: dont_fold_urem_i16_smax:
1336 ; RV64IM: # %bb.0:
1337 ; RV64IM-NEXT: lh a2, 8(a1)
1338 ; RV64IM-NEXT: slli a6, a2, 48
1339 ; RV64IM-NEXT: lh a4, 24(a1)
1340 ; RV64IM-NEXT: lh a1, 16(a1)
1341 ; RV64IM-NEXT: lui a5, 1043590
1342 ; RV64IM-NEXT: addiw a5, a5, -1781
1343 ; RV64IM-NEXT: slli a5, a5, 13
1344 ; RV64IM-NEXT: addi a5, a5, 1069
1345 ; RV64IM-NEXT: slli a5, a5, 12
1346 ; RV64IM-NEXT: addi a5, a5, -1959
1347 ; RV64IM-NEXT: slli a5, a5, 13
1348 ; RV64IM-NEXT: addi a5, a5, 357
1349 ; RV64IM-NEXT: mulh a5, a1, a5
1350 ; RV64IM-NEXT: add a5, a5, a1
1351 ; RV64IM-NEXT: srli a3, a5, 63
1352 ; RV64IM-NEXT: srli a5, a5, 4
1353 ; RV64IM-NEXT: add a3, a5, a3
1354 ; RV64IM-NEXT: addi a5, zero, 23
1355 ; RV64IM-NEXT: mul a3, a3, a5
1356 ; RV64IM-NEXT: sub a1, a1, a3
1357 ; RV64IM-NEXT: lui a3, 12375
1358 ; RV64IM-NEXT: addiw a3, a3, -575
1359 ; RV64IM-NEXT: slli a3, a3, 12
1360 ; RV64IM-NEXT: addi a3, a3, 883
1361 ; RV64IM-NEXT: slli a3, a3, 13
1362 ; RV64IM-NEXT: addi a3, a3, -431
1363 ; RV64IM-NEXT: slli a3, a3, 12
1364 ; RV64IM-NEXT: addi a3, a3, 1959
1365 ; RV64IM-NEXT: mulh a3, a4, a3
1366 ; RV64IM-NEXT: srli a5, a3, 63
1367 ; RV64IM-NEXT: srli a3, a3, 11
1368 ; RV64IM-NEXT: add a3, a3, a5
1369 ; RV64IM-NEXT: lui a5, 1
1370 ; RV64IM-NEXT: addiw a5, a5, 1327
1371 ; RV64IM-NEXT: mul a3, a3, a5
1372 ; RV64IM-NEXT: sub a3, a4, a3
1373 ; RV64IM-NEXT: srai a4, a6, 63
1374 ; RV64IM-NEXT: srli a4, a4, 49
1375 ; RV64IM-NEXT: add a4, a2, a4
1376 ; RV64IM-NEXT: lui a5, 8
1377 ; RV64IM-NEXT: and a4, a4, a5
1378 ; RV64IM-NEXT: sub a2, a2, a4
1379 ; RV64IM-NEXT: sh zero, 0(a0)
1380 ; RV64IM-NEXT: sh a2, 2(a0)
1381 ; RV64IM-NEXT: sh a3, 6(a0)
1382 ; RV64IM-NEXT: sh a1, 4(a0)
1383 ; RV64IM-NEXT: .cfi_def_cfa_offset 0
1384 ; RV64IM-NEXT: ret
1385 %1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423>
1386 ret <4 x i16> %1
1387 }
1389 ; Don't fold i64 srem.
1390 define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
1391 ; RV32I-LABEL: dont_fold_srem_i64:
1392 ; RV32I: # %bb.0:
1393 ; RV32I-NEXT: addi sp, sp, -48
1394 ; RV32I-NEXT: .cfi_def_cfa_offset 48
1395 ; RV32I-NEXT: sw ra, 44(sp)
1396 ; RV32I-NEXT: sw s0, 40(sp)
1397 ; RV32I-NEXT: sw s1, 36(sp)
1398 ; RV32I-NEXT: sw s2, 32(sp)
1399 ; RV32I-NEXT: sw s3, 28(sp)
1400 ; RV32I-NEXT: sw s4, 24(sp)
1401 ; RV32I-NEXT: sw s5, 20(sp)
1402 ; RV32I-NEXT: sw s6, 16(sp)
1403 ; RV32I-NEXT: sw s7, 12(sp)
1404 ; RV32I-NEXT: sw s8, 8(sp)
1405 ; RV32I-NEXT: sw s9, 4(sp)
1406 ; RV32I-NEXT: .cfi_offset ra, -4
1407 ; RV32I-NEXT: .cfi_offset s0, -8
1408 ; RV32I-NEXT: .cfi_offset s1, -12
1409 ; RV32I-NEXT: .cfi_offset s2, -16
1410 ; RV32I-NEXT: .cfi_offset s3, -20
1411 ; RV32I-NEXT: .cfi_offset s4, -24
1412 ; RV32I-NEXT: .cfi_offset s5, -28
1413 ; RV32I-NEXT: .cfi_offset s6, -32
1414 ; RV32I-NEXT: .cfi_offset s7, -36
1415 ; RV32I-NEXT: .cfi_offset s8, -40
1416 ; RV32I-NEXT: .cfi_offset s9, -44
1417 ; RV32I-NEXT: lw s2, 24(a1)
1418 ; RV32I-NEXT: lw s3, 28(a1)
1419 ; RV32I-NEXT: lw s4, 16(a1)
1420 ; RV32I-NEXT: lw s5, 20(a1)
1421 ; RV32I-NEXT: lw s6, 8(a1)
1422 ; RV32I-NEXT: lw s1, 12(a1)
1423 ; RV32I-NEXT: lw a3, 0(a1)
1424 ; RV32I-NEXT: lw a1, 4(a1)
1425 ; RV32I-NEXT: mv s0, a0
1426 ; RV32I-NEXT: addi a2, zero, 1
1427 ; RV32I-NEXT: mv a0, a3
1428 ; RV32I-NEXT: mv a3, zero
1429 ; RV32I-NEXT: call __moddi3
1430 ; RV32I-NEXT: mv s7, a0
1431 ; RV32I-NEXT: mv s8, a1
1432 ; RV32I-NEXT: addi a2, zero, 654
1433 ; RV32I-NEXT: mv a0, s6
1434 ; RV32I-NEXT: mv a1, s1
1435 ; RV32I-NEXT: mv a3, zero
1436 ; RV32I-NEXT: call __moddi3
1437 ; RV32I-NEXT: mv s6, a0
1438 ; RV32I-NEXT: mv s9, a1
1439 ; RV32I-NEXT: addi a2, zero, 23
1440 ; RV32I-NEXT: mv a0, s4
1441 ; RV32I-NEXT: mv a1, s5
1442 ; RV32I-NEXT: mv a3, zero
1443 ; RV32I-NEXT: call __moddi3
1444 ; RV32I-NEXT: mv s4, a0
1445 ; RV32I-NEXT: mv s1, a1
1446 ; RV32I-NEXT: lui a0, 1
1447 ; RV32I-NEXT: addi a2, a0, 1327
1448 ; RV32I-NEXT: mv a0, s2
1449 ; RV32I-NEXT: mv a1, s3
1450 ; RV32I-NEXT: mv a3, zero
1451 ; RV32I-NEXT: call __moddi3
1452 ; RV32I-NEXT: sw a1, 28(s0)
1453 ; RV32I-NEXT: sw a0, 24(s0)
1454 ; RV32I-NEXT: sw s1, 20(s0)
1455 ; RV32I-NEXT: sw s4, 16(s0)
1456 ; RV32I-NEXT: sw s9, 12(s0)
1457 ; RV32I-NEXT: sw s6, 8(s0)
1458 ; RV32I-NEXT: sw s8, 4(s0)
1459 ; RV32I-NEXT: sw s7, 0(s0)
1460 ; RV32I-NEXT: lw s9, 4(sp)
1461 ; RV32I-NEXT: lw s8, 8(sp)
1462 ; RV32I-NEXT: lw s7, 12(sp)
1463 ; RV32I-NEXT: lw s6, 16(sp)
1464 ; RV32I-NEXT: lw s5, 20(sp)
1465 ; RV32I-NEXT: lw s4, 24(sp)
1466 ; RV32I-NEXT: lw s3, 28(sp)
1467 ; RV32I-NEXT: lw s2, 32(sp)
1468 ; RV32I-NEXT: lw s1, 36(sp)
1469 ; RV32I-NEXT: lw s0, 40(sp)
1470 ; RV32I-NEXT: lw ra, 44(sp)
1471 ; RV32I-NEXT: .cfi_restore ra
1472 ; RV32I-NEXT: .cfi_restore s0
1473 ; RV32I-NEXT: .cfi_restore s1
1474 ; RV32I-NEXT: .cfi_restore s2
1475 ; RV32I-NEXT: .cfi_restore s3
1476 ; RV32I-NEXT: .cfi_restore s4
1477 ; RV32I-NEXT: .cfi_restore s5
1478 ; RV32I-NEXT: .cfi_restore s6
1479 ; RV32I-NEXT: .cfi_restore s7
1480 ; RV32I-NEXT: .cfi_restore s8
1481 ; RV32I-NEXT: .cfi_restore s9
1482 ; RV32I-NEXT: addi sp, sp, 48
1483 ; RV32I-NEXT: .cfi_def_cfa_offset 0
1484 ; RV32I-NEXT: ret
1485 ;
1486 ; RV32IM-LABEL: dont_fold_srem_i64:
1487 ; RV32IM: # %bb.0:
1488 ; RV32IM-NEXT: addi sp, sp, -48
1489 ; RV32IM-NEXT: .cfi_def_cfa_offset 48
1490 ; RV32IM-NEXT: sw ra, 44(sp)
1491 ; RV32IM-NEXT: sw s0, 40(sp)
1492 ; RV32IM-NEXT: sw s1, 36(sp)
1493 ; RV32IM-NEXT: sw s2, 32(sp)
1494 ; RV32IM-NEXT: sw s3, 28(sp)
1495 ; RV32IM-NEXT: sw s4, 24(sp)
1496 ; RV32IM-NEXT: sw s5, 20(sp)
1497 ; RV32IM-NEXT: sw s6, 16(sp)
1498 ; RV32IM-NEXT: sw s7, 12(sp)
1499 ; RV32IM-NEXT: sw s8, 8(sp)
1500 ; RV32IM-NEXT: sw s9, 4(sp)
1501 ; RV32IM-NEXT: .cfi_offset ra, -4
1502 ; RV32IM-NEXT: .cfi_offset s0, -8
1503 ; RV32IM-NEXT: .cfi_offset s1, -12
1504 ; RV32IM-NEXT: .cfi_offset s2, -16
1505 ; RV32IM-NEXT: .cfi_offset s3, -20
1506 ; RV32IM-NEXT: .cfi_offset s4, -24
1507 ; RV32IM-NEXT: .cfi_offset s5, -28
1508 ; RV32IM-NEXT: .cfi_offset s6, -32
1509 ; RV32IM-NEXT: .cfi_offset s7, -36
1510 ; RV32IM-NEXT: .cfi_offset s8, -40
1511 ; RV32IM-NEXT: .cfi_offset s9, -44
1512 ; RV32IM-NEXT: lw s2, 24(a1)
1513 ; RV32IM-NEXT: lw s3, 28(a1)
1514 ; RV32IM-NEXT: lw s4, 16(a1)
1515 ; RV32IM-NEXT: lw s5, 20(a1)
1516 ; RV32IM-NEXT: lw s6, 8(a1)
1517 ; RV32IM-NEXT: lw s1, 12(a1)
1518 ; RV32IM-NEXT: lw a3, 0(a1)
1519 ; RV32IM-NEXT: lw a1, 4(a1)
1520 ; RV32IM-NEXT: mv s0, a0
1521 ; RV32IM-NEXT: addi a2, zero, 1
1522 ; RV32IM-NEXT: mv a0, a3
1523 ; RV32IM-NEXT: mv a3, zero
1524 ; RV32IM-NEXT: call __moddi3
1525 ; RV32IM-NEXT: mv s7, a0
1526 ; RV32IM-NEXT: mv s8, a1
1527 ; RV32IM-NEXT: addi a2, zero, 654
1528 ; RV32IM-NEXT: mv a0, s6
1529 ; RV32IM-NEXT: mv a1, s1
1530 ; RV32IM-NEXT: mv a3, zero
1531 ; RV32IM-NEXT: call __moddi3
1532 ; RV32IM-NEXT: mv s6, a0
1533 ; RV32IM-NEXT: mv s9, a1
1534 ; RV32IM-NEXT: addi a2, zero, 23
1535 ; RV32IM-NEXT: mv a0, s4
1536 ; RV32IM-NEXT: mv a1, s5
1537 ; RV32IM-NEXT: mv a3, zero
1538 ; RV32IM-NEXT: call __moddi3
1539 ; RV32IM-NEXT: mv s4, a0
1540 ; RV32IM-NEXT: mv s1, a1
1541 ; RV32IM-NEXT: lui a0, 1
1542 ; RV32IM-NEXT: addi a2, a0, 1327
1543 ; RV32IM-NEXT: mv a0, s2
1544 ; RV32IM-NEXT: mv a1, s3
1545 ; RV32IM-NEXT: mv a3, zero
1546 ; RV32IM-NEXT: call __moddi3
1547 ; RV32IM-NEXT: sw a1, 28(s0)
1548 ; RV32IM-NEXT: sw a0, 24(s0)
1549 ; RV32IM-NEXT: sw s1, 20(s0)
1550 ; RV32IM-NEXT: sw s4, 16(s0)
1551 ; RV32IM-NEXT: sw s9, 12(s0)
1552 ; RV32IM-NEXT: sw s6, 8(s0)
1553 ; RV32IM-NEXT: sw s8, 4(s0)
1554 ; RV32IM-NEXT: sw s7, 0(s0)
1555 ; RV32IM-NEXT: lw s9, 4(sp)
1556 ; RV32IM-NEXT: lw s8, 8(sp)
1557 ; RV32IM-NEXT: lw s7, 12(sp)
1558 ; RV32IM-NEXT: lw s6, 16(sp)
1559 ; RV32IM-NEXT: lw s5, 20(sp)
1560 ; RV32IM-NEXT: lw s4, 24(sp)
1561 ; RV32IM-NEXT: lw s3, 28(sp)
1562 ; RV32IM-NEXT: lw s2, 32(sp)
1563 ; RV32IM-NEXT: lw s1, 36(sp)
1564 ; RV32IM-NEXT: lw s0, 40(sp)
1565 ; RV32IM-NEXT: lw ra, 44(sp)
1566 ; RV32IM-NEXT: .cfi_restore ra
1567 ; RV32IM-NEXT: .cfi_restore s0
1568 ; RV32IM-NEXT: .cfi_restore s1
1569 ; RV32IM-NEXT: .cfi_restore s2
1570 ; RV32IM-NEXT: .cfi_restore s3
1571 ; RV32IM-NEXT: .cfi_restore s4
1572 ; RV32IM-NEXT: .cfi_restore s5
1573 ; RV32IM-NEXT: .cfi_restore s6
1574 ; RV32IM-NEXT: .cfi_restore s7
1575 ; RV32IM-NEXT: .cfi_restore s8
1576 ; RV32IM-NEXT: .cfi_restore s9
1577 ; RV32IM-NEXT: addi sp, sp, 48
1578 ; RV32IM-NEXT: .cfi_def_cfa_offset 0
1579 ; RV32IM-NEXT: ret
1580 ;
1581 ; RV64I-LABEL: dont_fold_srem_i64:
1582 ; RV64I: # %bb.0:
1583 ; RV64I-NEXT: addi sp, sp, -48
1584 ; RV64I-NEXT: .cfi_def_cfa_offset 48
1585 ; RV64I-NEXT: sd ra, 40(sp)
1586 ; RV64I-NEXT: sd s0, 32(sp)
1587 ; RV64I-NEXT: sd s1, 24(sp)
1588 ; RV64I-NEXT: sd s2, 16(sp)
1589 ; RV64I-NEXT: sd s3, 8(sp)
1590 ; RV64I-NEXT: .cfi_offset ra, -8
1591 ; RV64I-NEXT: .cfi_offset s0, -16
1592 ; RV64I-NEXT: .cfi_offset s1, -24
1593 ; RV64I-NEXT: .cfi_offset s2, -32
1594 ; RV64I-NEXT: .cfi_offset s3, -40
1595 ; RV64I-NEXT: ld s2, 24(a1)
1596 ; RV64I-NEXT: ld s1, 16(a1)
1597 ; RV64I-NEXT: ld a2, 8(a1)
1598 ; RV64I-NEXT: mv s0, a0
1599 ; RV64I-NEXT: addi a1, zero, 654
1600 ; RV64I-NEXT: mv a0, a2
1601 ; RV64I-NEXT: call __moddi3
1602 ; RV64I-NEXT: mv s3, a0
1603 ; RV64I-NEXT: addi a1, zero, 23
1604 ; RV64I-NEXT: mv a0, s1
1605 ; RV64I-NEXT: call __moddi3
1606 ; RV64I-NEXT: mv s1, a0
1607 ; RV64I-NEXT: lui a0, 1
1608 ; RV64I-NEXT: addiw a1, a0, 1327
1609 ; RV64I-NEXT: mv a0, s2
1610 ; RV64I-NEXT: call __moddi3
1611 ; RV64I-NEXT: sd zero, 0(s0)
1612 ; RV64I-NEXT: sd a0, 24(s0)
1613 ; RV64I-NEXT: sd s1, 16(s0)
1614 ; RV64I-NEXT: sd s3, 8(s0)
1615 ; RV64I-NEXT: ld s3, 8(sp)
1616 ; RV64I-NEXT: ld s2, 16(sp)
1617 ; RV64I-NEXT: ld s1, 24(sp)
1618 ; RV64I-NEXT: ld s0, 32(sp)
1619 ; RV64I-NEXT: ld ra, 40(sp)
1620 ; RV64I-NEXT: .cfi_restore ra
1621 ; RV64I-NEXT: .cfi_restore s0
1622 ; RV64I-NEXT: .cfi_restore s1
1623 ; RV64I-NEXT: .cfi_restore s2
1624 ; RV64I-NEXT: .cfi_restore s3
1625 ; RV64I-NEXT: addi sp, sp, 48
1626 ; RV64I-NEXT: .cfi_def_cfa_offset 0
1627 ; RV64I-NEXT: ret
1628 ;
1629 ; RV64IM-LABEL: dont_fold_srem_i64:
1630 ; RV64IM: # %bb.0:
1631 ; RV64IM-NEXT: ld a2, 24(a1)
1632 ; RV64IM-NEXT: ld a3, 8(a1)
1633 ; RV64IM-NEXT: ld a1, 16(a1)
1634 ; RV64IM-NEXT: lui a4, 1043590
1635 ; RV64IM-NEXT: addiw a4, a4, -1781
1636 ; RV64IM-NEXT: slli a4, a4, 13
1637 ; RV64IM-NEXT: addi a4, a4, 1069
1638 ; RV64IM-NEXT: slli a4, a4, 12
1639 ; RV64IM-NEXT: addi a4, a4, -1959
1640 ; RV64IM-NEXT: slli a4, a4, 13
1641 ; RV64IM-NEXT: addi a4, a4, 357
1642 ; RV64IM-NEXT: mulh a4, a1, a4
1643 ; RV64IM-NEXT: add a4, a4, a1
1644 ; RV64IM-NEXT: srli a5, a4, 63
1645 ; RV64IM-NEXT: srai a4, a4, 4
1646 ; RV64IM-NEXT: add a4, a4, a5
1647 ; RV64IM-NEXT: addi a5, zero, 23
1648 ; RV64IM-NEXT: mul a4, a4, a5
1649 ; RV64IM-NEXT: sub a1, a1, a4
1650 ; RV64IM-NEXT: lui a4, 6413
1651 ; RV64IM-NEXT: addiw a4, a4, 1265
1652 ; RV64IM-NEXT: slli a4, a4, 13
1653 ; RV64IM-NEXT: addi a4, a4, 1027
1654 ; RV64IM-NEXT: slli a4, a4, 13
1655 ; RV64IM-NEXT: addi a4, a4, 1077
1656 ; RV64IM-NEXT: slli a4, a4, 12
1657 ; RV64IM-NEXT: addi a4, a4, 965
1658 ; RV64IM-NEXT: mulh a4, a3, a4
1659 ; RV64IM-NEXT: srli a5, a4, 63
1660 ; RV64IM-NEXT: srai a4, a4, 8
1661 ; RV64IM-NEXT: add a4, a4, a5
1662 ; RV64IM-NEXT: addi a5, zero, 654
1663 ; RV64IM-NEXT: mul a4, a4, a5
1664 ; RV64IM-NEXT: sub a3, a3, a4
1665 ; RV64IM-NEXT: lui a4, 12375
1666 ; RV64IM-NEXT: addiw a4, a4, -575
1667 ; RV64IM-NEXT: slli a4, a4, 12
1668 ; RV64IM-NEXT: addi a4, a4, 883
1669 ; RV64IM-NEXT: slli a4, a4, 13
1670 ; RV64IM-NEXT: addi a4, a4, -431
1671 ; RV64IM-NEXT: slli a4, a4, 12
1672 ; RV64IM-NEXT: addi a4, a4, 1959
1673 ; RV64IM-NEXT: mulh a4, a2, a4
1674 ; RV64IM-NEXT: srli a5, a4, 63
1675 ; RV64IM-NEXT: srai a4, a4, 11
1676 ; RV64IM-NEXT: add a4, a4, a5
1677 ; RV64IM-NEXT: lui a5, 1
1678 ; RV64IM-NEXT: addiw a5, a5, 1327
1679 ; RV64IM-NEXT: mul a4, a4, a5
1680 ; RV64IM-NEXT: sub a2, a2, a4
1681 ; RV64IM-NEXT: sd zero, 0(a0)
1682 ; RV64IM-NEXT: sd a2, 24(a0)
1683 ; RV64IM-NEXT: sd a3, 8(a0)
1684 ; RV64IM-NEXT: sd a1, 16(a0)
1685 ; RV64IM-NEXT: .cfi_def_cfa_offset 0
1686 ; RV64IM-NEXT: ret
1687 %1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
1688 ret <4 x i64> %1
1689 }