lib/CodeGen/MachineOperand.cpp

   1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file Methods common to all machine operands.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/MachineOperand.h"
  14 #include "llvm/ADT/StringExtras.h"
  15 #include "llvm/Analysis/Loads.h"
  16 #include "llvm/Analysis/MemoryLocation.h"
  17 #include "llvm/CodeGen/MIRPrinter.h"
  18 #include "llvm/CodeGen/MachineFrameInfo.h"
  19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
  20 #include "llvm/CodeGen/MachineRegisterInfo.h"
  21 #include "llvm/CodeGen/TargetInstrInfo.h"
  22 #include "llvm/CodeGen/TargetRegisterInfo.h"
  23 #include "llvm/Config/llvm-config.h"
  24 #include "llvm/IR/Constants.h"
  25 #include "llvm/IR/IRPrintingPasses.h"
  26 #include "llvm/IR/ModuleSlotTracker.h"
  27 #include "llvm/MC/MCDwarf.h"
  28 #include "llvm/Target/TargetIntrinsicInfo.h"
  29 #include "llvm/Target/TargetMachine.h"
  30
  31 using namespace llvm;
  32
  33 static cl::opt<int>
  34     PrintRegMaskNumRegs("print-regmask-num-regs",
  35                         cl::desc("Number of registers to limit to when "
  36                                  "printing regmask operands in IR dumps. "
  37                                  "unlimited = -1"),
  38                         cl::init(32), cl::Hidden);
  39
  40 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
  41   if (const MachineInstr *MI = MO.getParent())
  42     if (const MachineBasicBlock *MBB = MI->getParent())
  43       if (const MachineFunction *MF = MBB->getParent())
  44         return MF;
  45   return nullptr;
  46 }
  47 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
  48   return const_cast<MachineFunction *>(
  49       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
  50 }
  51
  52 void MachineOperand::setReg(Register Reg) {
  53   if (getReg() == Reg)
  54     return; // No change.
  55
  56   // Clear the IsRenamable bit to keep it conservatively correct.
  57   IsRenamable = false;
  58
  59   // Otherwise, we have to change the register.  If this operand is embedded
  60   // into a machine function, we need to update the old and new register's
  61   // use/def lists.
  62   if (MachineFunction *MF = getMFIfAvailable(*this)) {
  63     MachineRegisterInfo &MRI = MF->getRegInfo();
  64     MRI.removeRegOperandFromUseList(this);
  65     SmallContents.RegNo = Reg;
  66     MRI.addRegOperandToUseList(this);
  67     return;
  68   }
  69
  70   // Otherwise, just change the register, no problem.  :)
  71   SmallContents.RegNo = Reg;
  72 }
  73
  74 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
  75                                   const TargetRegisterInfo &TRI) {
  76   assert(Reg.isVirtual());
  77   if (SubIdx && getSubReg())
  78     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
  79   setReg(Reg);
  80   if (SubIdx)
  81     setSubReg(SubIdx);
  82 }
  83
  84 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
  85   assert(Reg.isPhysical());
  86   if (getSubReg()) {
  87     Reg = TRI.getSubReg(Reg, getSubReg());
  88     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
  89     // That won't happen in legal code.
  90     setSubReg(0);
  91     if (isDef())
  92       setIsUndef(false);
  93   }
  94   setReg(Reg);
  95 }
  96
  97 /// Change a def to a use, or a use to a def.
  98 void MachineOperand::setIsDef(bool Val) {
  99   assert(isReg() && "Wrong MachineOperand accessor");
 100   assert((!Val || !isDebug()) && "Marking a debug operation as def");
 101   if (IsDef == Val)
 102     return;
 103   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
 104   // MRI may keep uses and defs in different list positions.
 105   if (MachineFunction *MF = getMFIfAvailable(*this)) {
 106     MachineRegisterInfo &MRI = MF->getRegInfo();
 107     MRI.removeRegOperandFromUseList(this);
 108     IsDef = Val;
 109     MRI.addRegOperandToUseList(this);
 110     return;
 111   }
 112   IsDef = Val;
 113 }
 114
 115 bool MachineOperand::isRenamable() const {
 116   assert(isReg() && "Wrong MachineOperand accessor");
 117   assert(Register::isPhysicalRegister(getReg()) &&
 118          "isRenamable should only be checked on physical registers");
 119   if (!IsRenamable)
 120     return false;
 121
 122   const MachineInstr *MI = getParent();
 123   if (!MI)
 124     return true;
 125
 126   if (isDef())
 127     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
 128
 129   assert(isUse() && "Reg is not def or use");
 130   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
 131 }
 132
 133 void MachineOperand::setIsRenamable(bool Val) {
 134   assert(isReg() && "Wrong MachineOperand accessor");
 135   assert(Register::isPhysicalRegister(getReg()) &&
 136          "setIsRenamable should only be called on physical registers");
 137   IsRenamable = Val;
 138 }
 139
 140 // If this operand is currently a register operand, and if this is in a
 141 // function, deregister the operand from the register's use/def list.
 142 void MachineOperand::removeRegFromUses() {
 143   if (!isReg() || !isOnRegUseList())
 144     return;
 145
 146   if (MachineFunction *MF = getMFIfAvailable(*this))
 147     MF->getRegInfo().removeRegOperandFromUseList(this);
 148 }
 149
 150 /// ChangeToImmediate - Replace this operand with a new immediate operand of
 151 /// the specified value.  If an operand is known to be an immediate already,
 152 /// the setImm method should be used.
 153 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
 154   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
 155
 156   removeRegFromUses();
 157
 158   OpKind = MO_Immediate;
 159   Contents.ImmVal = ImmVal;
 160 }
 161
 162 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
 163   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
 164
 165   removeRegFromUses();
 166
 167   OpKind = MO_FPImmediate;
 168   Contents.CFP = FPImm;
 169 }
 170
 171 void MachineOperand::ChangeToES(const char *SymName,
 172                                 unsigned TargetFlags) {
 173   assert((!isReg() || !isTied()) &&
 174          "Cannot change a tied operand into an external symbol");
 175
 176   removeRegFromUses();
 177
 178   OpKind = MO_ExternalSymbol;
 179   Contents.OffsetedInfo.Val.SymbolName = SymName;
 180   setOffset(0); // Offset is always 0.
 181   setTargetFlags(TargetFlags);
 182 }
 183
 184 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
 185                                 unsigned TargetFlags) {
 186   assert((!isReg() || !isTied()) &&
 187          "Cannot change a tied operand into a global address");
 188
 189   removeRegFromUses();
 190
 191   OpKind = MO_GlobalAddress;
 192   Contents.OffsetedInfo.Val.GV = GV;
 193   setOffset(Offset);
 194   setTargetFlags(TargetFlags);
 195 }
 196
 197 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
 198   assert((!isReg() || !isTied()) &&
 199          "Cannot change a tied operand into an MCSymbol");
 200
 201   removeRegFromUses();
 202
 203   OpKind = MO_MCSymbol;
 204   Contents.Sym = Sym;
 205 }
 206
 207 void MachineOperand::ChangeToFrameIndex(int Idx) {
 208   assert((!isReg() || !isTied()) &&
 209          "Cannot change a tied operand into a FrameIndex");
 210
 211   removeRegFromUses();
 212
 213   OpKind = MO_FrameIndex;
 214   setIndex(Idx);
 215 }
 216
 217 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
 218                                          unsigned TargetFlags) {
 219   assert((!isReg() || !isTied()) &&
 220          "Cannot change a tied operand into a FrameIndex");
 221
 222   removeRegFromUses();
 223
 224   OpKind = MO_TargetIndex;
 225   setIndex(Idx);
 226   setOffset(Offset);
 227   setTargetFlags(TargetFlags);
 228 }
 229
 230 /// ChangeToRegister - Replace this operand with a new register operand of
 231 /// the specified value.  If an operand is known to be an register already,
 232 /// the setReg method should be used.
 233 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
 234                                       bool isKill, bool isDead, bool isUndef,
 235                                       bool isDebug) {
 236   MachineRegisterInfo *RegInfo = nullptr;
 237   if (MachineFunction *MF = getMFIfAvailable(*this))
 238     RegInfo = &MF->getRegInfo();
 239   // If this operand is already a register operand, remove it from the
 240   // register's use/def lists.
 241   bool WasReg = isReg();
 242   if (RegInfo && WasReg)
 243     RegInfo->removeRegOperandFromUseList(this);
 244
 245   // Change this to a register and set the reg#.
 246   assert(!(isDead && !isDef) && "Dead flag on non-def");
 247   assert(!(isKill && isDef) && "Kill flag on def");
 248   OpKind = MO_Register;
 249   SmallContents.RegNo = Reg;
 250   SubReg_TargetFlags = 0;
 251   IsDef = isDef;
 252   IsImp = isImp;
 253   IsDeadOrKill = isKill | isDead;
 254   IsRenamable = false;
 255   IsUndef = isUndef;
 256   IsInternalRead = false;
 257   IsEarlyClobber = false;
 258   IsDebug = isDebug;
 259   // Ensure isOnRegUseList() returns false.
 260   Contents.Reg.Prev = nullptr;
 261   // Preserve the tie when the operand was already a register.
 262   if (!WasReg)
 263     TiedTo = 0;
 264
 265   // If this operand is embedded in a function, add the operand to the
 266   // register's use/def list.
 267   if (RegInfo)
 268     RegInfo->addRegOperandToUseList(this);
 269 }
 270
 271 /// isIdenticalTo - Return true if this operand is identical to the specified
 272 /// operand. Note that this should stay in sync with the hash_value overload
 273 /// below.
 274 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
 275   if (getType() != Other.getType() ||
 276       getTargetFlags() != Other.getTargetFlags())
 277     return false;
 278
 279   switch (getType()) {
 280   case MachineOperand::MO_Register:
 281     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
 282            getSubReg() == Other.getSubReg();
 283   case MachineOperand::MO_Immediate:
 284     return getImm() == Other.getImm();
 285   case MachineOperand::MO_CImmediate:
 286     return getCImm() == Other.getCImm();
 287   case MachineOperand::MO_FPImmediate:
 288     return getFPImm() == Other.getFPImm();
 289   case MachineOperand::MO_MachineBasicBlock:
 290     return getMBB() == Other.getMBB();
 291   case MachineOperand::MO_FrameIndex:
 292     return getIndex() == Other.getIndex();
 293   case MachineOperand::MO_ConstantPoolIndex:
 294   case MachineOperand::MO_TargetIndex:
 295     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
 296   case MachineOperand::MO_JumpTableIndex:
 297     return getIndex() == Other.getIndex();
 298   case MachineOperand::MO_GlobalAddress:
 299     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
 300   case MachineOperand::MO_ExternalSymbol:
 301     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
 302            getOffset() == Other.getOffset();
 303   case MachineOperand::MO_BlockAddress:
 304     return getBlockAddress() == Other.getBlockAddress() &&
 305            getOffset() == Other.getOffset();
 306   case MachineOperand::MO_RegisterMask:
 307   case MachineOperand::MO_RegisterLiveOut: {
 308     // Shallow compare of the two RegMasks
 309     const uint32_t *RegMask = getRegMask();
 310     const uint32_t *OtherRegMask = Other.getRegMask();
 311     if (RegMask == OtherRegMask)
 312       return true;
 313
 314     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 315       // Calculate the size of the RegMask
 316       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
 317       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
 318
 319       // Deep compare of the two RegMasks
 320       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
 321     }
 322     // We don't know the size of the RegMask, so we can't deep compare the two
 323     // reg masks.
 324     return false;
 325   }
 326   case MachineOperand::MO_MCSymbol:
 327     return getMCSymbol() == Other.getMCSymbol();
 328   case MachineOperand::MO_CFIIndex:
 329     return getCFIIndex() == Other.getCFIIndex();
 330   case MachineOperand::MO_Metadata:
 331     return getMetadata() == Other.getMetadata();
 332   case MachineOperand::MO_IntrinsicID:
 333     return getIntrinsicID() == Other.getIntrinsicID();
 334   case MachineOperand::MO_Predicate:
 335     return getPredicate() == Other.getPredicate();
 336   }
 337   llvm_unreachable("Invalid machine operand type");
 338 }
 339
 340 // Note: this must stay exactly in sync with isIdenticalTo above.
 341 hash_code llvm::hash_value(const MachineOperand &MO) {
 342   switch (MO.getType()) {
 343   case MachineOperand::MO_Register:
 344     // Register operands don't have target flags.
 345     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
 346   case MachineOperand::MO_Immediate:
 347     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
 348   case MachineOperand::MO_CImmediate:
 349     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
 350   case MachineOperand::MO_FPImmediate:
 351     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
 352   case MachineOperand::MO_MachineBasicBlock:
 353     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
 354   case MachineOperand::MO_FrameIndex:
 355     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
 356   case MachineOperand::MO_ConstantPoolIndex:
 357   case MachineOperand::MO_TargetIndex:
 358     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
 359                         MO.getOffset());
 360   case MachineOperand::MO_JumpTableIndex:
 361     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
 362   case MachineOperand::MO_ExternalSymbol:
 363     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
 364                         StringRef(MO.getSymbolName()));
 365   case MachineOperand::MO_GlobalAddress:
 366     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
 367                         MO.getOffset());
 368   case MachineOperand::MO_BlockAddress:
 369     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
 370                         MO.getOffset());
 371   case MachineOperand::MO_RegisterMask:
 372   case MachineOperand::MO_RegisterLiveOut:
 373     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
 374   case MachineOperand::MO_Metadata:
 375     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
 376   case MachineOperand::MO_MCSymbol:
 377     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
 378   case MachineOperand::MO_CFIIndex:
 379     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
 380   case MachineOperand::MO_IntrinsicID:
 381     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
 382   case MachineOperand::MO_Predicate:
 383     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
 384   }
 385   llvm_unreachable("Invalid machine operand type");
 386 }
 387
 388 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
 389 // it.
 390 static void tryToGetTargetInfo(const MachineOperand &MO,
 391                                const TargetRegisterInfo *&TRI,
 392                                const TargetIntrinsicInfo *&IntrinsicInfo) {
 393   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
 394     TRI = MF->getSubtarget().getRegisterInfo();
 395     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
 396   }
 397 }
 398
 399 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
 400   const auto *TII = MF.getSubtarget().getInstrInfo();
 401   assert(TII && "expected instruction info");
 402   auto Indices = TII->getSerializableTargetIndices();
 403   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
 404     return I.first == Index;
 405   });
 406   if (Found != Indices.end())
 407     return Found->second;
 408   return nullptr;
 409 }
 410
 411 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
 412   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
 413   for (const auto &I : Flags) {
 414     if (I.first == TF) {
 415       return I.second;
 416     }
 417   }
 418   return nullptr;
 419 }
 420
 421 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
 422                              const TargetRegisterInfo *TRI) {
 423   if (!TRI) {
 424     OS << "%dwarfreg." << DwarfReg;
 425     return;
 426   }
 427
 428   int Reg = TRI->getLLVMRegNum(DwarfReg, true);
 429   if (Reg == -1) {
 430     OS << "<badreg>";
 431     return;
 432   }
 433   OS << printReg(Reg, TRI);
 434 }
 435
 436 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
 437                                   ModuleSlotTracker &MST) {
 438   OS << "%ir-block.";
 439   if (BB.hasName()) {
 440     printLLVMNameWithoutPrefix(OS, BB.getName());
 441     return;
 442   }
 443   Optional<int> Slot;
 444   if (const Function *F = BB.getParent()) {
 445     if (F == MST.getCurrentFunction()) {
 446       Slot = MST.getLocalSlot(&BB);
 447     } else if (const Module *M = F->getParent()) {
 448       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
 449       CustomMST.incorporateFunction(*F);
 450       Slot = CustomMST.getLocalSlot(&BB);
 451     }
 452   }
 453   if (Slot)
 454     MachineOperand::printIRSlotNumber(OS, *Slot);
 455   else
 456     OS << "<unknown>";
 457 }
 458
 459 static void printIRValueReference(raw_ostream &OS, const Value &V,
 460                                   ModuleSlotTracker &MST) {
 461   if (isa<GlobalValue>(V)) {
 462     V.printAsOperand(OS, /*PrintType=*/false, MST);
 463     return;
 464   }
 465   if (isa<Constant>(V)) {
 466     // Machine memory operands can load/store to/from constant value pointers.
 467     OS << '`';
 468     V.printAsOperand(OS, /*PrintType=*/true, MST);
 469     OS << '`';
 470     return;
 471   }
 472   OS << "%ir.";
 473   if (V.hasName()) {
 474     printLLVMNameWithoutPrefix(OS, V.getName());
 475     return;
 476   }
 477   int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
 478   MachineOperand::printIRSlotNumber(OS, Slot);
 479 }
 480
 481 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
 482                            SyncScope::ID SSID,
 483                            SmallVectorImpl<StringRef> &SSNs) {
 484   switch (SSID) {
 485   case SyncScope::System:
 486     break;
 487   default:
 488     if (SSNs.empty())
 489       Context.getSyncScopeNames(SSNs);
 490
 491     OS << "syncscope(\"";
 492     printEscapedString(SSNs[SSID], OS);
 493     OS << "\") ";
 494     break;
 495   }
 496 }
 497
 498 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
 499                                         unsigned TMMOFlag) {
 500   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
 501   for (const auto &I : Flags) {
 502     if (I.first == TMMOFlag) {
 503       return I.second;
 504     }
 505   }
 506   return nullptr;
 507 }
 508
 509 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
 510                             const MachineFrameInfo *MFI) {
 511   StringRef Name;
 512   if (MFI) {
 513     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
 514     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
 515       if (Alloca->hasName())
 516         Name = Alloca->getName();
 517     if (IsFixed)
 518       FrameIndex -= MFI->getObjectIndexBegin();
 519   }
 520   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
 521 }
 522
 523 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
 524                                     const TargetRegisterInfo *TRI) {
 525   OS << "%subreg.";
 526   if (TRI)
 527     OS << TRI->getSubRegIndexName(Index);
 528   else
 529     OS << Index;
 530 }
 531
 532 void MachineOperand::printTargetFlags(raw_ostream &OS,
 533                                       const MachineOperand &Op) {
 534   if (!Op.getTargetFlags())
 535     return;
 536   const MachineFunction *MF = getMFIfAvailable(Op);
 537   if (!MF)
 538     return;
 539
 540   const auto *TII = MF->getSubtarget().getInstrInfo();
 541   assert(TII && "expected instruction info");
 542   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
 543   OS << "target-flags(";
 544   const bool HasDirectFlags = Flags.first;
 545   const bool HasBitmaskFlags = Flags.second;
 546   if (!HasDirectFlags && !HasBitmaskFlags) {
 547     OS << "<unknown>) ";
 548     return;
 549   }
 550   if (HasDirectFlags) {
 551     if (const auto *Name = getTargetFlagName(TII, Flags.first))
 552       OS << Name;
 553     else
 554       OS << "<unknown target flag>";
 555   }
 556   if (!HasBitmaskFlags) {
 557     OS << ") ";
 558     return;
 559   }
 560   bool IsCommaNeeded = HasDirectFlags;
 561   unsigned BitMask = Flags.second;
 562   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
 563   for (const auto &Mask : BitMasks) {
 564     // Check if the flag's bitmask has the bits of the current mask set.
 565     if ((BitMask & Mask.first) == Mask.first) {
 566       if (IsCommaNeeded)
 567         OS << ", ";
 568       IsCommaNeeded = true;
 569       OS << Mask.second;
 570       // Clear the bits which were serialized from the flag's bitmask.
 571       BitMask &= ~(Mask.first);
 572     }
 573   }
 574   if (BitMask) {
 575     // When the resulting flag's bitmask isn't zero, we know that we didn't
 576     // serialize all of the bit flags.
 577     if (IsCommaNeeded)
 578       OS << ", ";
 579     OS << "<unknown bitmask target flag>";
 580   }
 581   OS << ") ";
 582 }
 583
 584 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
 585   OS << "<mcsymbol " << Sym << ">";
 586 }
 587
 588 void MachineOperand::printStackObjectReference(raw_ostream &OS,
 589                                                unsigned FrameIndex,
 590                                                bool IsFixed, StringRef Name) {
 591   if (IsFixed) {
 592     OS << "%fixed-stack." << FrameIndex;
 593     return;
 594   }
 595
 596   OS << "%stack." << FrameIndex;
 597   if (!Name.empty())
 598     OS << '.' << Name;
 599 }
 600
 601 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
 602   if (Offset == 0)
 603     return;
 604   if (Offset < 0) {
 605     OS << " - " << -Offset;
 606     return;
 607   }
 608   OS << " + " << Offset;
 609 }
 610
 611 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
 612   if (Slot == -1)
 613     OS << "<badref>";
 614   else
 615     OS << Slot;
 616 }
 617
 618 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
 619                      const TargetRegisterInfo *TRI) {
 620   switch (CFI.getOperation()) {
 621   case MCCFIInstruction::OpSameValue:
 622     OS << "same_value ";
 623     if (MCSymbol *Label = CFI.getLabel())
 624       MachineOperand::printSymbol(OS, *Label);
 625     printCFIRegister(CFI.getRegister(), OS, TRI);
 626     break;
 627   case MCCFIInstruction::OpRememberState:
 628     OS << "remember_state ";
 629     if (MCSymbol *Label = CFI.getLabel())
 630       MachineOperand::printSymbol(OS, *Label);
 631     break;
 632   case MCCFIInstruction::OpRestoreState:
 633     OS << "restore_state ";
 634     if (MCSymbol *Label = CFI.getLabel())
 635       MachineOperand::printSymbol(OS, *Label);
 636     break;
 637   case MCCFIInstruction::OpOffset:
 638     OS << "offset ";
 639     if (MCSymbol *Label = CFI.getLabel())
 640       MachineOperand::printSymbol(OS, *Label);
 641     printCFIRegister(CFI.getRegister(), OS, TRI);
 642     OS << ", " << CFI.getOffset();
 643     break;
 644   case MCCFIInstruction::OpDefCfaRegister:
 645     OS << "def_cfa_register ";
 646     if (MCSymbol *Label = CFI.getLabel())
 647       MachineOperand::printSymbol(OS, *Label);
 648     printCFIRegister(CFI.getRegister(), OS, TRI);
 649     break;
 650   case MCCFIInstruction::OpDefCfaOffset:
 651     OS << "def_cfa_offset ";
 652     if (MCSymbol *Label = CFI.getLabel())
 653       MachineOperand::printSymbol(OS, *Label);
 654     OS << CFI.getOffset();
 655     break;
 656   case MCCFIInstruction::OpDefCfa:
 657     OS << "def_cfa ";
 658     if (MCSymbol *Label = CFI.getLabel())
 659       MachineOperand::printSymbol(OS, *Label);
 660     printCFIRegister(CFI.getRegister(), OS, TRI);
 661     OS << ", " << CFI.getOffset();
 662     break;
 663   case MCCFIInstruction::OpRelOffset:
 664     OS << "rel_offset ";
 665     if (MCSymbol *Label = CFI.getLabel())
 666       MachineOperand::printSymbol(OS, *Label);
 667     printCFIRegister(CFI.getRegister(), OS, TRI);
 668     OS << ", " << CFI.getOffset();
 669     break;
 670   case MCCFIInstruction::OpAdjustCfaOffset:
 671     OS << "adjust_cfa_offset ";
 672     if (MCSymbol *Label = CFI.getLabel())
 673       MachineOperand::printSymbol(OS, *Label);
 674     OS << CFI.getOffset();
 675     break;
 676   case MCCFIInstruction::OpRestore:
 677     OS << "restore ";
 678     if (MCSymbol *Label = CFI.getLabel())
 679       MachineOperand::printSymbol(OS, *Label);
 680     printCFIRegister(CFI.getRegister(), OS, TRI);
 681     break;
 682   case MCCFIInstruction::OpEscape: {
 683     OS << "escape ";
 684     if (MCSymbol *Label = CFI.getLabel())
 685       MachineOperand::printSymbol(OS, *Label);
 686     if (!CFI.getValues().empty()) {
 687       size_t e = CFI.getValues().size() - 1;
 688       for (size_t i = 0; i < e; ++i)
 689         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
 690       OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
 691     }
 692     break;
 693   }
 694   case MCCFIInstruction::OpUndefined:
 695     OS << "undefined ";
 696     if (MCSymbol *Label = CFI.getLabel())
 697       MachineOperand::printSymbol(OS, *Label);
 698     printCFIRegister(CFI.getRegister(), OS, TRI);
 699     break;
 700   case MCCFIInstruction::OpRegister:
 701     OS << "register ";
 702     if (MCSymbol *Label = CFI.getLabel())
 703       MachineOperand::printSymbol(OS, *Label);
 704     printCFIRegister(CFI.getRegister(), OS, TRI);
 705     OS << ", ";
 706     printCFIRegister(CFI.getRegister2(), OS, TRI);
 707     break;
 708   case MCCFIInstruction::OpWindowSave:
 709     OS << "window_save ";
 710     if (MCSymbol *Label = CFI.getLabel())
 711       MachineOperand::printSymbol(OS, *Label);
 712     break;
 713   case MCCFIInstruction::OpNegateRAState:
 714     OS << "negate_ra_sign_state ";
 715     if (MCSymbol *Label = CFI.getLabel())
 716       MachineOperand::printSymbol(OS, *Label);
 717     break;
 718   default:
 719     // TODO: Print the other CFI Operations.
 720     OS << "<unserializable cfi directive>";
 721     break;
 722   }
 723 }
 724
 725 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
 726                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 727   print(OS, LLT{}, TRI, IntrinsicInfo);
 728 }
 729
 730 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
 731                            const TargetRegisterInfo *TRI,
 732                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 733   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
 734   ModuleSlotTracker DummyMST(nullptr);
 735   print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
 736         /*ShouldPrintRegisterTies=*/true,
 737         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
 738 }
 739
 740 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
 741                            LLT TypeToPrint, bool PrintDef, bool IsStandalone,
 742                            bool ShouldPrintRegisterTies,
 743                            unsigned TiedOperandIdx,
 744                            const TargetRegisterInfo *TRI,
 745                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 746   printTargetFlags(OS, *this);
 747   switch (getType()) {
 748   case MachineOperand::MO_Register: {
 749     unsigned Reg = getReg();
 750     if (isImplicit())
 751       OS << (isDef() ? "implicit-def " : "implicit ");
 752     else if (PrintDef && isDef())
 753       // Print the 'def' flag only when the operand is defined after '='.
 754       OS << "def ";
 755     if (isInternalRead())
 756       OS << "internal ";
 757     if (isDead())
 758       OS << "dead ";
 759     if (isKill())
 760       OS << "killed ";
 761     if (isUndef())
 762       OS << "undef ";
 763     if (isEarlyClobber())
 764       OS << "early-clobber ";
 765     if (Register::isPhysicalRegister(getReg()) && isRenamable())
 766       OS << "renamable ";
 767     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
 768     // simply infer it when parsing and do not need to print it.
 769
 770     const MachineRegisterInfo *MRI = nullptr;
 771     if (Register::isVirtualRegister(Reg)) {
 772       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 773         MRI = &MF->getRegInfo();
 774       }
 775     }
 776
 777     OS << printReg(Reg, TRI, 0, MRI);
 778     // Print the sub register.
 779     if (unsigned SubReg = getSubReg()) {
 780       if (TRI)
 781         OS << '.' << TRI->getSubRegIndexName(SubReg);
 782       else
 783         OS << ".subreg" << SubReg;
 784     }
 785     // Print the register class / bank.
 786     if (Register::isVirtualRegister(Reg)) {
 787       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 788         const MachineRegisterInfo &MRI = MF->getRegInfo();
 789         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
 790           OS << ':';
 791           OS << printRegClassOrBank(Reg, MRI, TRI);
 792         }
 793       }
 794     }
 795     // Print ties.
 796     if (ShouldPrintRegisterTies && isTied() && !isDef())
 797       OS << "(tied-def " << TiedOperandIdx << ")";
 798     // Print types.
 799     if (TypeToPrint.isValid())
 800       OS << '(' << TypeToPrint << ')';
 801     break;
 802   }
 803   case MachineOperand::MO_Immediate:
 804     OS << getImm();
 805     break;
 806   case MachineOperand::MO_CImmediate:
 807     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
 808     break;
 809   case MachineOperand::MO_FPImmediate:
 810     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
 811     break;
 812   case MachineOperand::MO_MachineBasicBlock:
 813     OS << printMBBReference(*getMBB());
 814     break;
 815   case MachineOperand::MO_FrameIndex: {
 816     int FrameIndex = getIndex();
 817     bool IsFixed = false;
 818     const MachineFrameInfo *MFI = nullptr;
 819     if (const MachineFunction *MF = getMFIfAvailable(*this))
 820       MFI = &MF->getFrameInfo();
 821     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
 822     break;
 823   }
 824   case MachineOperand::MO_ConstantPoolIndex:
 825     OS << "%const." << getIndex();
 826     printOperandOffset(OS, getOffset());
 827     break;
 828   case MachineOperand::MO_TargetIndex: {
 829     OS << "target-index(";
 830     const char *Name = "<unknown>";
 831     if (const MachineFunction *MF = getMFIfAvailable(*this))
 832       if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
 833         Name = TargetIndexName;
 834     OS << Name << ')';
 835     printOperandOffset(OS, getOffset());
 836     break;
 837   }
 838   case MachineOperand::MO_JumpTableIndex:
 839     OS << printJumpTableEntryReference(getIndex());
 840     break;
 841   case MachineOperand::MO_GlobalAddress:
 842     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
 843     printOperandOffset(OS, getOffset());
 844     break;
 845   case MachineOperand::MO_ExternalSymbol: {
 846     StringRef Name = getSymbolName();
 847     OS << '&';
 848     if (Name.empty()) {
 849       OS << "\"\"";
 850     } else {
 851       printLLVMNameWithoutPrefix(OS, Name);
 852     }
 853     printOperandOffset(OS, getOffset());
 854     break;
 855   }
 856   case MachineOperand::MO_BlockAddress: {
 857     OS << "blockaddress(";
 858     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
 859                                                      MST);
 860     OS << ", ";
 861     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
 862     OS << ')';
 863     MachineOperand::printOperandOffset(OS, getOffset());
 864     break;
 865   }
 866   case MachineOperand::MO_RegisterMask: {
 867     OS << "<regmask";
 868     if (TRI) {
 869       unsigned NumRegsInMask = 0;
 870       unsigned NumRegsEmitted = 0;
 871       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
 872         unsigned MaskWord = i / 32;
 873         unsigned MaskBit = i % 32;
 874         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
 875           if (PrintRegMaskNumRegs < 0 ||
 876               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
 877             OS << " " << printReg(i, TRI);
 878             NumRegsEmitted++;
 879           }
 880           NumRegsInMask++;
 881         }
 882       }
 883       if (NumRegsEmitted != NumRegsInMask)
 884         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
 885     } else {
 886       OS << " ...";
 887     }
 888     OS << ">";
 889     break;
 890   }
 891   case MachineOperand::MO_RegisterLiveOut: {
 892     const uint32_t *RegMask = getRegLiveOut();
 893     OS << "liveout(";
 894     if (!TRI) {
 895       OS << "<unknown>";
 896     } else {
 897       bool IsCommaNeeded = false;
 898       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
 899         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
 900           if (IsCommaNeeded)
 901             OS << ", ";
 902           OS << printReg(Reg, TRI);
 903           IsCommaNeeded = true;
 904         }
 905       }
 906     }
 907     OS << ")";
 908     break;
 909   }
 910   case MachineOperand::MO_Metadata:
 911     getMetadata()->printAsOperand(OS, MST);
 912     break;
 913   case MachineOperand::MO_MCSymbol:
 914     printSymbol(OS, *getMCSymbol());
 915     break;
 916   case MachineOperand::MO_CFIIndex: {
 917     if (const MachineFunction *MF = getMFIfAvailable(*this))
 918       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
 919     else
 920       OS << "<cfi directive>";
 921     break;
 922   }
 923   case MachineOperand::MO_IntrinsicID: {
 924     Intrinsic::ID ID = getIntrinsicID();
 925     if (ID < Intrinsic::num_intrinsics)
 926       OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
 927     else if (IntrinsicInfo)
 928       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
 929     else
 930       OS << "intrinsic(" << ID << ')';
 931     break;
 932   }
 933   case MachineOperand::MO_Predicate: {
 934     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
 935     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
 936        << CmpInst::getPredicateName(Pred) << ')';
 937     break;
 938   }
 939   }
 940 }
 941
 942 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 943 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
 944 #endif
 945
 946 //===----------------------------------------------------------------------===//
 947 // MachineMemOperand Implementation
 948 //===----------------------------------------------------------------------===//
 949
 950 /// getAddrSpace - Return the LLVM IR address space number that this pointer
 951 /// points into.
 952 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
 953
 954 /// isDereferenceable - Return true if V is always dereferenceable for
 955 /// Offset + Size byte.
 956 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
 957                                            const DataLayout &DL) const {
 958   if (!V.is<const Value *>())
 959     return false;
 960
 961   const Value *BasePtr = V.get<const Value *>();
 962   if (BasePtr == nullptr)
 963     return false;
 964
 965   return isDereferenceableAndAlignedPointer(
 966       BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
 967 }
 968
 969 /// getConstantPool - Return a MachinePointerInfo record that refers to the
 970 /// constant pool.
 971 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
 972   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
 973 }
 974
 975 /// getFixedStack - Return a MachinePointerInfo record that refers to the
 976 /// the specified FrameIndex.
 977 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
 978                                                      int FI, int64_t Offset) {
 979   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
 980 }
 981
 982 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
 983   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
 984 }
 985
 986 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
 987   return MachinePointerInfo(MF.getPSVManager().getGOT());
 988 }
 989
 990 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
 991                                                 int64_t Offset, uint8_t ID) {
 992   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
 993 }
 994
 995 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
 996   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
 997 }
 998
 999 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1000                                      uint64_t s, uint64_t a,
1001                                      const AAMDNodes &AAInfo,
1002                                      const MDNode *Ranges, SyncScope::ID SSID,
1003                                      AtomicOrdering Ordering,
1004                                      AtomicOrdering FailureOrdering)
1005     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
1006       AAInfo(AAInfo), Ranges(Ranges) {
1007   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1008           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1009          "invalid pointer value");
1010   assert(getBaseAlignment() == a && a != 0 && "Alignment is not a power of 2!");
1011   assert((isLoad() || isStore()) && "Not a load/store!");
1012
1013   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1014   assert(getSyncScopeID() == SSID && "Value truncated");
1015   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1016   assert(getOrdering() == Ordering && "Value truncated");
1017   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1018   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1019 }
1020
1021 /// Profile - Gather unique data for the object.
1022 ///
1023 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1024   ID.AddInteger(getOffset());
1025   ID.AddInteger(Size);
1026   ID.AddPointer(getOpaqueValue());
1027   ID.AddInteger(getFlags());
1028   ID.AddInteger(getBaseAlignment());
1029 }
1030
1031 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1032   // The Value and Offset may differ due to CSE. But the flags and size
1033   // should be the same.
1034   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1035   assert(MMO->getSize() == getSize() && "Size mismatch!");
1036
1037   if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1038     // Update the alignment value.
1039     BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1040     // Also update the base and offset, because the new alignment may
1041     // not be applicable with the old ones.
1042     PtrInfo = MMO->PtrInfo;
1043   }
1044 }
1045
1046 /// getAlignment - Return the minimum known alignment in bytes of the
1047 /// actual memory reference.
1048 uint64_t MachineMemOperand::getAlignment() const {
1049   return MinAlign(getBaseAlignment(), getOffset());
1050 }
1051
1052 void MachineMemOperand::print(raw_ostream &OS) const {
1053   ModuleSlotTracker DummyMST(nullptr);
1054   print(OS, DummyMST);
1055 }
1056
1057 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
1058   SmallVector<StringRef, 0> SSNs;
1059   LLVMContext Ctx;
1060   print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1061 }
1062
1063 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1064                               SmallVectorImpl<StringRef> &SSNs,
1065                               const LLVMContext &Context,
1066                               const MachineFrameInfo *MFI,
1067                               const TargetInstrInfo *TII) const {
1068   OS << '(';
1069   if (isVolatile())
1070     OS << "volatile ";
1071   if (isNonTemporal())
1072     OS << "non-temporal ";
1073   if (isDereferenceable())
1074     OS << "dereferenceable ";
1075   if (isInvariant())
1076     OS << "invariant ";
1077   if (getFlags() & MachineMemOperand::MOTargetFlag1)
1078     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1079        << "\" ";
1080   if (getFlags() & MachineMemOperand::MOTargetFlag2)
1081     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1082        << "\" ";
1083   if (getFlags() & MachineMemOperand::MOTargetFlag3)
1084     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1085        << "\" ";
1086
1087   assert((isLoad() || isStore()) &&
1088          "machine memory operand must be a load or store (or both)");
1089   if (isLoad())
1090     OS << "load ";
1091   if (isStore())
1092     OS << "store ";
1093
1094   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1095
1096   if (getOrdering() != AtomicOrdering::NotAtomic)
1097     OS << toIRString(getOrdering()) << ' ';
1098   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1099     OS << toIRString(getFailureOrdering()) << ' ';
1100
1101   if (getSize() == MemoryLocation::UnknownSize)
1102     OS << "unknown-size";
1103   else
1104     OS << getSize();
1105
1106   if (const Value *Val = getValue()) {
1107     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1108     printIRValueReference(OS, *Val, MST);
1109   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1110     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1111     assert(PVal && "Expected a pseudo source value");
1112     switch (PVal->kind()) {
1113     case PseudoSourceValue::Stack:
1114       OS << "stack";
1115       break;
1116     case PseudoSourceValue::GOT:
1117       OS << "got";
1118       break;
1119     case PseudoSourceValue::JumpTable:
1120       OS << "jump-table";
1121       break;
1122     case PseudoSourceValue::ConstantPool:
1123       OS << "constant-pool";
1124       break;
1125     case PseudoSourceValue::FixedStack: {
1126       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1127       bool IsFixed = true;
1128       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1129       break;
1130     }
1131     case PseudoSourceValue::GlobalValueCallEntry:
1132       OS << "call-entry ";
1133       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1134           OS, /*PrintType=*/false, MST);
1135       break;
1136     case PseudoSourceValue::ExternalSymbolCallEntry:
1137       OS << "call-entry &";
1138       printLLVMNameWithoutPrefix(
1139           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1140       break;
1141     default:
1142       // FIXME: This is not necessarily the correct MIR serialization format for
1143       // a custom pseudo source value, but at least it allows
1144       // -print-machineinstrs to work on a target with custom pseudo source
1145       // values.
1146       OS << "custom ";
1147       PVal->printCustom(OS);
1148       break;
1149     }
1150   }
1151   MachineOperand::printOperandOffset(OS, getOffset());
1152   if (getBaseAlignment() != getSize())
1153     OS << ", align " << getBaseAlignment();
1154   auto AAInfo = getAAInfo();
1155   if (AAInfo.TBAA) {
1156     OS << ", !tbaa ";
1157     AAInfo.TBAA->printAsOperand(OS, MST);
1158   }
1159   if (AAInfo.Scope) {
1160     OS << ", !alias.scope ";
1161     AAInfo.Scope->printAsOperand(OS, MST);
1162   }
1163   if (AAInfo.NoAlias) {
1164     OS << ", !noalias ";
1165     AAInfo.NoAlias->printAsOperand(OS, MST);
1166   }
1167   if (getRanges()) {
1168     OS << ", !range ";
1169     getRanges()->printAsOperand(OS, MST);
1170   }
1171   // FIXME: Implement addrspace printing/parsing in MIR.
1172   // For now, print this even though parsing it is not available in MIR.
1173   if (unsigned AS = getAddrSpace())
1174     OS << ", addrspace " << AS;
1175
1176   OS << ')';
1177 }