lib/Target/AMDGPU/AMDGPUInstructionSelector.h

   1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file declares the targeting of the InstructionSelector class for
  10 /// AMDGPU.
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
  14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
  15
  16 #include "AMDGPU.h"
  17 #include "AMDGPUArgumentUsageInfo.h"
  18 #include "llvm/ADT/ArrayRef.h"
  19 #include "llvm/ADT/SmallVector.h"
  20 #include "llvm/CodeGen/Register.h"
  21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  22 #include "llvm/IR/InstrTypes.h"
  23
  24 namespace {
  25 #define GET_GLOBALISEL_PREDICATE_BITSET
  26 #define AMDGPUSubtarget GCNSubtarget
  27 #include "AMDGPUGenGlobalISel.inc"
  28 #undef GET_GLOBALISEL_PREDICATE_BITSET
  29 #undef AMDGPUSubtarget
  30 }
  31
  32 namespace llvm {
  33
  34 class AMDGPUInstrInfo;
  35 class AMDGPURegisterBankInfo;
  36 class GCNSubtarget;
  37 class MachineInstr;
  38 class MachineIRBuilder;
  39 class MachineOperand;
  40 class MachineRegisterInfo;
  41 class SIInstrInfo;
  42 class SIMachineFunctionInfo;
  43 class SIRegisterInfo;
  44
  45 class AMDGPUInstructionSelector : public InstructionSelector {
  46 public:
  47   AMDGPUInstructionSelector(const GCNSubtarget &STI,
  48                             const AMDGPURegisterBankInfo &RBI,
  49                             const AMDGPUTargetMachine &TM);
  50
  51   bool select(MachineInstr &I) override;
  52   static const char *getName();
  53
  54 private:
  55   struct GEPInfo {
  56     const MachineInstr &GEP;
  57     SmallVector<unsigned, 2> SgprParts;
  58     SmallVector<unsigned, 2> VgprParts;
  59     int64_t Imm;
  60     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
  61   };
  62
  63   bool isInstrUniform(const MachineInstr &MI) const;
  64   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
  65
  66   /// tblgen-erated 'select' implementation.
  67   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
  68
  69   MachineOperand getSubOperand64(MachineOperand &MO,
  70                                  const TargetRegisterClass &SubRC,
  71                                  unsigned SubIdx) const;
  72   bool selectCOPY(MachineInstr &I) const;
  73   bool selectPHI(MachineInstr &I) const;
  74   bool selectG_TRUNC(MachineInstr &I) const;
  75   bool selectG_SZA_EXT(MachineInstr &I) const;
  76   bool selectG_CONSTANT(MachineInstr &I) const;
  77   bool selectG_AND_OR_XOR(MachineInstr &I) const;
  78   bool selectG_ADD_SUB(MachineInstr &I) const;
  79   bool selectG_EXTRACT(MachineInstr &I) const;
  80   bool selectG_MERGE_VALUES(MachineInstr &I) const;
  81   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
  82   bool selectG_GEP(MachineInstr &I) const;
  83   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
  84   bool selectG_INSERT(MachineInstr &I) const;
  85   bool selectG_INTRINSIC(MachineInstr &I) const;
  86
  87   std::tuple<Register, unsigned, unsigned>
  88   splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
  89
  90   bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const;
  91
  92   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
  93   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
  94   bool selectG_ICMP(MachineInstr &I) const;
  95   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
  96   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
  97                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
  98   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
  99
 100   void initM0(MachineInstr &I) const;
 101   bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
 102   bool selectG_STORE(MachineInstr &I) const;
 103   bool selectG_SELECT(MachineInstr &I) const;
 104   bool selectG_BRCOND(MachineInstr &I) const;
 105   bool selectG_FRAME_INDEX(MachineInstr &I) const;
 106   bool selectG_PTR_MASK(MachineInstr &I) const;
 107
 108   std::pair<Register, unsigned>
 109   selectVOP3ModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
 110
 111   InstructionSelector::ComplexRendererFns
 112   selectVCSRC(MachineOperand &Root) const;
 113
 114   InstructionSelector::ComplexRendererFns
 115   selectVSRC0(MachineOperand &Root) const;
 116
 117   InstructionSelector::ComplexRendererFns
 118   selectVOP3Mods0(MachineOperand &Root) const;
 119   InstructionSelector::ComplexRendererFns
 120   selectVOP3Mods0Clamp0OMod(MachineOperand &Root) const;
 121   InstructionSelector::ComplexRendererFns
 122   selectVOP3OMods(MachineOperand &Root) const;
 123   InstructionSelector::ComplexRendererFns
 124   selectVOP3Mods(MachineOperand &Root) const;
 125
 126   InstructionSelector::ComplexRendererFns
 127   selectVOP3OpSelMods0(MachineOperand &Root) const;
 128   InstructionSelector::ComplexRendererFns
 129   selectVOP3OpSelMods(MachineOperand &Root) const;
 130
 131   InstructionSelector::ComplexRendererFns
 132   selectSmrdImm(MachineOperand &Root) const;
 133   InstructionSelector::ComplexRendererFns
 134   selectSmrdImm32(MachineOperand &Root) const;
 135   InstructionSelector::ComplexRendererFns
 136   selectSmrdSgpr(MachineOperand &Root) const;
 137
 138   template <bool Signed>
 139   InstructionSelector::ComplexRendererFns
 140   selectFlatOffsetImpl(MachineOperand &Root) const;
 141   InstructionSelector::ComplexRendererFns
 142   selectFlatOffset(MachineOperand &Root) const;
 143
 144   InstructionSelector::ComplexRendererFns
 145   selectFlatOffsetSigned(MachineOperand &Root) const;
 146
 147   InstructionSelector::ComplexRendererFns
 148   selectMUBUFScratchOffen(MachineOperand &Root) const;
 149   InstructionSelector::ComplexRendererFns
 150   selectMUBUFScratchOffset(MachineOperand &Root) const;
 151
 152   bool isDSOffsetLegal(const MachineRegisterInfo &MRI,
 153                        const MachineOperand &Base,
 154                        int64_t Offset, unsigned OffsetBits) const;
 155
 156   InstructionSelector::ComplexRendererFns
 157   selectDS1Addr1Offset(MachineOperand &Root) const;
 158
 159   const SIInstrInfo &TII;
 160   const SIRegisterInfo &TRI;
 161   const AMDGPURegisterBankInfo &RBI;
 162   const AMDGPUTargetMachine &TM;
 163   const GCNSubtarget &STI;
 164   bool EnableLateStructurizeCFG;
 165 #define GET_GLOBALISEL_PREDICATES_DECL
 166 #define AMDGPUSubtarget GCNSubtarget
 167 #include "AMDGPUGenGlobalISel.inc"
 168 #undef GET_GLOBALISEL_PREDICATES_DECL
 169 #undef AMDGPUSubtarget
 170
 171 #define GET_GLOBALISEL_TEMPORARIES_DECL
 172 #include "AMDGPUGenGlobalISel.inc"
 173 #undef GET_GLOBALISEL_TEMPORARIES_DECL
 174 };
 175
 176 } // End llvm namespace.
 177 #endif